synopsys_formality指导手册_概述说明

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【VIP专享】Formality使用指南

push_ctrl.v, gray2bin.v, pop_ctrl.v, rs_flop.v。
Lib：门级网表需要的技术库；包含lsi_10k.db。 Gate：综合的门级网表；包含fifo.vg 和fifo_mod.vg。 Gate_with_scan：插入扫描链的门级网表；
包含fifo_with_scan.v。
由于fifo.v 是源代码，fifo.vg只是综合的源代码，没有添加SCAN和JTAG链。故可以省略这一步
检查reference design4和.MImatpclehmention design的比较
点是否匹配点击Match按钮，选择Run Matching按钮，进行匹
配检查。出现下图结果：没有不匹配的比较点，可以进入下
在点击Set Top Design按钮，出现下图。
在choose a library 中选择WORK，在choose a design中选择fifo（顶层设计的模块名）在Set and link the top design中点击Set Top，出现下图同时在Reference按钮上出现绿色的对号符：
（一）图形用户界面进行形式验证
在UNXI提示符下进入 tutorial目录：输入fm（或 formality）。
1.设置reference design
点击formality图形界面的reference按钮，进入Read Design File
点击Verilog按钮，出现添加Verilog文件的对话框。如下图：
由于验证失败，系统直接进入DEBUG工作区。在 Failing Points的报告工作区里显示两设计的出不一致的比较点
在Failing Points的报告工作区内点击鼠标右键，选择Show All Cone Size ,在Size栏里显示每个compar point所包含的cell的数目

Synopsys Formality EC Solution说明书

DATASHEETOverview Formality ® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent.Formality delivers capabilities for ECO assistance and advanced debugging to help guide the user in implementing and verifying ECOs. These capabilities significantly shorten the ECO implementation cycle.The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable.Formality supports all of the out-of- the-box Design Compiler ® and Fusion Compiler™ optimizations and so provides the highest quality of results that are fully verifiable.Formality supports verification of power-up and power-down states, multi-voltage, multi- supply and clock gated designs.Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time.Figure 1: Formality equivalence checking solutionIndependent formalverification of DesignCompiler and FusionCompiler synthesisresults, with built-in intelligencedelivering the highestverifiable QoRFormality Equivalence Checking and Interactive ECOKey Benefits• Perfect companion to Design Compiler and Fusion Compiler—supports all default optimizations• Intuitive flow-based graphical user interface• Verifies low-power designs including power-up and power-down states• ECO implementation assistance, fast verification of the ECO, and advanced debugging• Auto setup mode reduces “false failures” caused by incorrect or missing setup information• Multicore verification boosts performance• Automated guidance boosts completion with Design Compiler and Fusion Compiler• Verifies full-custom and memory designs when including ESP technologyFormalityThe Most Comprehensive Equivalence Checking SolutionFormality delivers superior completion on designs compiled with Design Compiler or Fusion Compiler. Design Compiler is the industry leading family of RTL Synthesis solutions. Fusion Compiler is the next generation RTL-to-GDSII implementation system architected to address the complexities of advanced process node design. Designers no longer need to disable the powerful optimizations available with Design Compiler or Fusion Compiler to get equivalence checking to pass. Design Compiler/Fusion Compiler combined with Formality delivers maximum quality of results (QoR) that are fully verifiable.Easy to Use with Auto-setup modeFormality’s auto-setup mode simplifies verification by reducing false failures caused by incorrect or missing setup information. Auto-setup applies setup information in Formality to match the assumptions made by Design Compiler or Fusion Compiler, including naming styles, unused pins, test inputs and clock gating.Critical files such as RTL, netlists and libraries are automatically located. All auto-setup information is listed in a summary report.Guided SetupFormality can account for synthesis optimizations using a guided setup file automatically generated by Design Compiler or Fusion Compiler. Guided setup includes information about name changes, register optimizations, multiplier architectures and many other transformations that may occur during synthesis. This correct-by-construction information improves performance and first-pass completion by utilizing the most efficient algorithms during matching and verification.Formality-guided setup is a standard, documented format that removes unpredictability found in tools relying on log file parsing.Independent VerificationEvery aspect of a guided setup flow is either implicitly or explicitly verified, and all content is available for inspection in an ASCII file.Figure 2: Automatic cone pruning improves schematic readability when debuggingHier-IQ TechnologyPatented Hier-IQ technology provides the performance benefits of hierarchical verification with flat verification’s out-of- the-box usability.Error-ID TechnologyError-ID identifies the exact logic causing real functional differences between two design representations. Error-ID can isolate and report several logic differences when multiple discrepancies exist. Error-ID will also present alternative logic that can be changed to correct a given functional difference; this flexibility allows the designer to select the change that is easiest to implement.Failing Pattern Display WindowAll failing input patterns can be viewed in a familiar spreadsheet-like format. The failing pattern window is an ideal way to quickly identify trends indicating the cause of a failing verification or improper setup.Figure 3: Problem areas can be easy identified by visual inspection of the Failing Pattern WindowPower-aware VerificationFormality is fully compatible with Power Compiler™ and verifies power-up and power-down states, multi-voltage, multi-supply and clock gated designs.When a reference design block is powered up, Formality verifies functionality. If the implementation design powers up differently, failing points will occur.Formality functionally verifies that the implementation powers down when the reference powers down and will detectfunctional states where the implementation does not power down as expected. The valid power states are defined in the power state table (PST).Power intent is supplied to Formality through IEEE 1801 Unified Power Format (UPF).Figure 4: Power connectivity is easy to see and debug from the schematic viewAccelerated Time to ResultsFormality’s performance is enhanced with multicore verification. This Formality capability allows verification of the design using up to four cores simultaneously to reduce verification time.Other Time-Saving FeaturesFormality’s Hierarchical Scripting provides a method to investigate sub-blocks without additional setup and is ideal for isolating problems and verifying fixes.The Source Browser opens RTL and netlist source files to highlight occurrences of a selected instance. This can help users correlate between the RTL and gate-level design versions.Error Region Correlation provides a quick, visual identification of the logic from one design that correspond to the errors isolated by Error-ID within the other.Command Line Editing allows you to take advantage of history and common text editor commands when working from Formality’s command line.Interactive ECOKey BenefitsProvides GUI-driven ECO implementation assistance, fast ECO verification, and advanced debugging. Formality guides the user through the implementation of ECOs, and then quickly verifies only the changed logic.Formality Interactive ECO FlowFormality uses the ECO RTL and an unmodified netlist. Guided GUI driven changes are made to the netlist. Once the ECO has been implemented, a quick verification is run on only the affected logic cones, eliminating the need for a full verification run on the design to verify that the ECO was implemented correctly.Once all ECO’s are implemented and fully verified, a list of IC Compiler™ commands is generated to assist in implementing the physical changes to the design.ECO GuidanceFormality highlights equivalent nets between the reference and implementation designs, and nets that have lost their equivalence due to the ECO changes in the reference. This helps the designer quickly identify where the change should be made in the implementation.Implementing the ECOEditing commands in Formality are used to modify the netlist in-place using the GUI.Rapid ECO VerificationFormality can identify and verify just the portion of the design affected by the ECO. This ensures that the ECO was implemented correctly. If the ECO verification fails, the ECO can be interactively “undone” and new edits can be made again. Once the partial verification passes, the changes are committed. This partial verification eliminates having to verify the entire design to assure that the ECO was implemented correctly, dramatically reducing the total time required to implement and verify the ECO.Figure 5: Equivalent net is highlighted between Reference design (left) and Implementation design (right)Figure 6: On a completed ECO, the schematic shows the nets affected by ECO in yellow, and the new component and net in orangeFigure 7: Formality transcript shows a successful partial verification of the portion of the design that was affected by the ECOInterface with IC Compiler IIOnce the ECO’s are implemented and verified, a final complete verification run is performed to assure that the ECO RTL and the ECO netlist are functionally equivalent.Formality produces IC Compiler II compatible ECO command file, easing the implementation in the physical design.Advanced DebuggingFormality incorporates advanced debugging capabilities that help the designer identify and debug verifications that do not pass. The designer can find compare points, equivalences (and inverted-equivalences) between reference and implementation designs, perform “what if” analysis by interactively modifying the designs, and verify equivalence between two (or multiple) points.Transistor VerificationESP combines with Formality to offer fast verification of custom circuits, embedded memories and complex I/Os. ESP technology directly reads existing SPICE and behavioral RTL models and does not require restrictive mapping or translation.Input Formats• Synopsys DC, DDC, Milkyway™• IEEE 1800 SystemVerilog• Verilog-95, Verilog-2001• VHDL-87, VHDL-93• IEEE 1801 Unified Power Format (UPF)Guided Setup Formats• Synopsys V-SDC• Formality Guide Files (SVF)Platform Support• Linux Suse, Red Hat and Enterprise• SPARC SolarisFor more information about Synopsys products, support services or training, visit us on the web at: , contact your local sales representative or call 650.584.5000.©2019 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks isavailable at /copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.。

Synopsys应用安全（AppSec）指南说明书

The CISO’s Ultimate Guide to Securing Applications11 Best Practices to Minimize Risk and Protect Your DataTable of contentsGetting started (1)Address the No. 1 attack vector—your applications (2)Put the right tools in place (4)Ensure your team has sufficient skills and resources (6)Address changing AppSec risks when moving to the cloud (6)The bottom line (7)Find out how Synopsys can help (7)Getting startedNo organization wants to be susceptible to cyber attacks that can compromise sensitive customer, employee, and business data. By now, the consequences of data breaches are both familiar and painful: brand damage, loss ofcustomer confidence, potentially costly litigation, and regulatory fines.To eliminate your threats, or at least reduce them, your primary focus has to be on where the risk is greatest. Ifforced to choose between repairing a front door that’s been smashed in or a small hole in the backyard fence, nosane homeowner would opt for the fence.Unfortunately, when it comes to cyber threats, too many organizations are figuratively focused on the fence andignoring the smashed-in door.According to SAP , 84% of cyber attacks happen on the application layer.1 In other words, application vulnerabilities are the No. 1 attack surface for hackers. Yet where do organizations spend the most time and treasure? Onnetwork security.It’s true that for most organizations, software isn’t their core business. But virtually every modern enterprise—from retail to finance , healthcare , manufacturing, automotive , and more —has an online presence. Mobile and webapplications enable their businesses—and those applications are built with, and run by, software. They operate both outside and across whatever security perimeter exists. Obviously, if they’re not secure, they put an enterprise at risk.If you lead a modern enterprise, the mobile and web applications you create represent the figurative smashed-in door that threatens your business. To fix the door, you need to address application security holistically,across people, process, and technology, and throughout the software development life cycle (SDLC). Why? Fortwo main reasons:1. To protect your sensitive data from leaks that could cripple your organization’s reputation and cut into your bottom line.2. To minimize the risk from security defects in the software you build, effortlessly and cost-effectively.1.2.Understandably, in a hypercompetitive world, you want to do that without slowing application development ormaking the process too complex.That’s a challenge. But it can be done. In this eBook you’ll learn about 11 best practices you can follow to protectyour sensitive data and minimize risk.Address the No. 1 attack vector—your applicationsEnterprise applications, which are mostly web and mobile, are the new perimeter of your organization. Since they operate outside and through the firewall, network security protections alone aren’t enough; you must secure theapplications themselves.Three fundamental best practices can help you do that:Best practice 1: Eliminate vulnerabilities before applications go into production.To address application security before development is complete, it’s essential to build security into yourdevelopment teams (people), processes, and tools (technology). An increasingly popular term for that is “shiftleft”—make security part of the SDLC from the concept and design stage right through the entire developmentprocess to production.The common perception is that security testing throughout development slows the process down. But the opposite is true. Finding and fixing application vulnerabilities during development and testing is more efficient and lessexpensive than doing so at the end of the process, when an application is already in production. In other words,you’ll save time and money by shifting left.84% of cyber attacks happen on the application layer.2Best practice 2: Address security in architecture, design, and opensource and third-party components.If you’re only checking for bugs in your proprietary code or running penetration tests against your system, you’re likely missing a substantial number of the vulnerabilities in your software.• Architecture and design. Design flaws account for 50% of the security vulnerabilities that increase your system’s susceptibility to an attack. Therefore, it’s important to identify potential weaknesses in your architecture, including secure design violations, security control omissions, and control misconfiguration, weakness, and misuse. You can do this with architecture risk analysis and threat modeling.• Open source and third-party components. Today’s applications contain up to 90% open source components. Because open source is so ubiquitous—and so rarely tracked—it’s become a prime target for hackers. Exploits are readily available almost immediately after a vulnerability becomes public, and these vulnerabilities provide the keys to thousands of applications—potentially yours. To manage these risks, it’s important to track open source through development and into production with a solution such as software composition analysis that gives you immediate notifications of vulnerabilities that affect your applications.For a deeper look into these tools, check out our Enterprise AppSec Buying Guide.Today’s applicationscontain up to90% open sourcecomponentsBest practice 3: Enable application security from the start with tools thatwork within the developer’s environment.One way to do this is with an IDE (integrated development environment) plugin, which lets developers see the results of security tests directly in the IDE as they work on their code. That analysis happens automatically as the developer works, delivering results in near real time.Put the right tools in placeYou don’t build a house (or fix a door) with nothing but a hammer. Such a project involves a variety of materials, tasks, and requirements. If all you have is a hammer, pounding on everything as if it were a nail will do more damage than good. Using a single tool definitely won’t get the job done.No single AppSec tool does it all.Similarly, no single AppSec tool does it all. Applications are developed using different languages and frameworks. They’re hosted in different environments, whether in the cloud or on-premises. They use open source and third-party libraries to different degrees. And they differ from one another in many other critical ways that can affect application security testing results.Therefore, strengthening your application security requires multiple analysis tools, all of which must work within your team’s environment to maximize productivity while enabling you to minimize the risk of vulnerabilities ending up in the final product.You can maximize productivity while minimizing your risk using the following two best practices:Best practice 4: Build an “AppSec toolbelt” that brings together thesolutions needed to address your risks.The field of software security is both crowded and confusing. Don’t be seduced by a pitch that a single tool or solution will eliminate your risk. It won’t. It may let you check a compliance box, but you will still be vulnerable. Instead, you need the AppSec version of what a building contractor carries—a “toolbelt” that brings together the many solutions you need to address your risks.An effective AppSec toolbelt should include integrated solutions that address application security risksend-to-end, providing analysis of vulnerabilities in proprietary code, open source components, and runtime configuration and behavior.Some tools to consider for your toolbelt:• DAST (dynamic application security testing), sometimes called black box testing, tests running applications early in the SDLC.• IAST (interactive application security testing) helps teams accurately identify and verify vulnerabilities and sensitive-data leakage with automated testing of running web applications.• SAST (static application security testing) helps teams find and fix security and quality weaknesses in proprietary code as it’s being developed.• SCA (software composition analysis) helps teams manage open source security and license compliance risks through automated analysis and policy enforcement.• Pen testing focuses on exploratory risk analysis and business logic by finding vulnerabilities in web applications and services and trying to exploit them so developers can address and fix them.Each solution addresses specific types of application security weaknesses. By deploying multiple solutions together, teams can ensure there are no holes in their coverage.Check out our Enterprise AppSec Buying Guide to learn more about these tools.Best practice 5: Analyze and understand your application security riskprofile so you can focus your efforts.There’s no such thing as a silver bullet for software security. Instead, every organization can manage its risk by knowing what’s most important to protect and focusing its efforts (and budget) there. Knowing what’s important requires a team of experienced security experts to analyze an application portfolio quickly and effectively and identify the specific risk profile for each app and its environment. Security experts provide services such as these:• Threat modeling helps teams design more secure software by analyzing the specific types of attacks they’re likely to face.• Architecture risk analysis (ARA) helps teams ensure that the architecture and design of their applications don’t make them easier to hack.• Red teaming helps an organization identify immediately exploitable security holes across its entire attack surface using a variety of composite attack methods.Ensure your team has sufficient skills and resources Application development has become a part of organizations of every size and in everyindustry. Customers and users care about the timely delivery of application featuresand functionality. But given the potential for loss of privacy, identity theft, and financialdamages from vulnerabilities, they care even more about security.That creates a problem for many organizations because the growth in their applicationportfolio has exceeded their application security capacity.You can close the gap between your application security needs and resources byimplementing the following three best practices.Best practice 6: Develop a program to raise the level of AppSeccompetency in your organization.Be sure you’re focusing on the actions that will have the biggest positive impact on your software security program at the least possible cost. You can do this by setting objectives, outlining a clear strategy for achieving your objectives, and clarifying the resources you’ll need to get there.Best practice 7: Provide development and security staff with sufficienttraining in AppSec risks and skills.High-quality training solutions can help security teams raise the level of application security skills in their organizations. Consider these types of security training:• eLearning lets staff members learn at their own pace and on their own time.• Instructor-led training (ILT) offers an extensive menu of courses delivered in a live online forum or on-premises. Courses are developed and taught by certified security professionals with hands-on experience working directly with clients facing software security challenges.Best practice 8: Augment internal staff when needed to address skill and resource gaps.Find a trusted partner that can provide on-demand expert testing, optimize resource allocation, and cost-effectively ensure complete testing coverage of your portfolio. You may even explore professional services to help you solve a wide variety of software security initiative challenges.Check out our Managed Services Buying Guide to learn more about finding a trusted partner.Address changing AppSec risks when moving to the cloudIf you’re like most development and operations teams, you’re highly motivated to move application deployment and operations to the public cloud for its obvious advantages: increased agility and reduced operating costs.But such a move also comes with well-known risks: loss of visibility and control over the infrastructure and services that affect application security. If teams don’t understand and address the risks of the cloud environment, it can lead to breaches and data loss.So if you’re planning to migrate existing applications to the cloud or building new applications to deploy in the cloud, you also need to plan for the unique security risks of the cloud. You can achieve that with the following three best practices.Best practice 9: Understand the cloud security provider’s risks andcontrols before you move your applications.It’s essential that your security, development, and operations teams know how to handle the new security risks that emerge as you migrate to the cloud. Start with a cloud security assessment that identifies specific security risks and opportunities associated with a target cloud platform.Best practice 10: Develop a structured plan to coordinate securityinitiative improvements with cloud migration.Once you fully understand the risks, you can create a roadmap for your cloud migration to ensure all teams are in alignment and your priorities are clear.Best practice 11: Establish security blueprints to help your developmentand operations teams implement cloud security best practices.Security blueprints lay out your cloud migration’s architectural structure with baseline security controls. They can help guide development teams and systems integrators in building and deploying cloud applications more securely.Check out The Ultimate Guide to Securing Your Cloud Apps.The bottom lineApplication security is not a one-time event. It’s a continuous journey. To do it effectively means building security into your SDLC without slowing down delivery times. Following some or more of the best practices described above will get you headed in the right direction.Not sure where to start? Synopsys has all the tools and services you need to get your application security program on track. We can help you deal with obstacles and accomplish your security goals better than anyone else, with a portfolio of solutions and services that address each problem and enable each best practice that’s necessary for you. At Synopsys, we help organizations build secure, high-quality software faster.Find out how Synopsys can helpReferences1. Tim Clark, Most Cyber Attacks Occur From This Common Vulnerability, Forbes, Mar. 10, 2015.2. Ibid.3. Amy DeMartine, The Forrester Wave™: Software Composition Analysis, Q1 2017, Forrester, Feb. 23, 2017.。

formality简介

Formality简介Formality，synopsis的工具，我们常说的形式验证、formal check 都是用它做的。

作用就是比较两者“r、i”在功能上是否一致，跟时序一点儿关系都没有！在数字ic的flow中，一般会做两次formal check：一．rtl对DC netlist做一次；二．DC netlist对PR后的netlist做一次。

先看个rtl对DC netlist的脚本：#-------------------------------------------------------------------------# Formal check for Capture.vhd ( rtl vs dc_nlist )#-------------------------------------------------------------------------set TOP_REF Captureset TOP_IMP Captureset REF_NAME Capture.vhdset IMP_NAME Capture.vset REF_PATH /home/project/9602-360-100/Dig/d1/work_jh/synop199/rtlset IMP_PATH /home/project/9602-360-100/Dig/d1/work_jh/synop199/dc1/nlist set RPT /home/project/9602-360-100/Dig/d1/work_jh/synop199/fm/rptset hdlin_dwroot /edatools/synopsys/syn_vX-2008.9-SP4set verification_failing_point_limit 2000set synopsys_auto_setup trueset_svf /home/project/9602-360-100/Dig/d1/work_jh/synop199/dc1/default.svf set search_path ". /home/project/9602-360-100/Dig/d1/synop199 //edatools/synopsys/syn_vX-2008.9-SP4/libraries/syn"read_db {chrt35_ss_75_1pt3_SYNOPSYS2_MMSIM.db dw_foundation.sldb}read_vhdl -r $REF_PATH/$REF_NAME -l work > $RPT/read_design.rptset_top $TOP_REF > $RPT/set_top.rptreport_hdlin_mismatch > $RPT/rpt_hdlin_mismatch.rptread_verilog -i $IMP_PATH/$IMP_NAME -l work >> $RPT/read_design.rpt set_top $TOP_IMP >> $RPT/set_top.rpt#set_constant -type port r:/.../ 0#set_constant -type port i:/.../ 0match > $RPT/match.rptreport_matched_points > $RPT/matched_point.rptreport_unmatched_points > $RPT/unmatched_point.rptreport_loops -limit 0 -unfold > $RPT/loops.rptverify#以上内容可以放在一个文件里作为脚本，调用方法就是在fm_work下$ fm_shell –f ../scripts/fm_rtl2dc.tcl如果成功要看详细信息或者失败要debug的话，再输入start_gui，进入-GUI模式。

Formality使用指南【精选】

一步。
5.Verify
点击OK键，完成。现在你已经准备好，可以进行 fifo.v和fifo.vg功能是否一致。
选择Verify按钮，点击Verify All，进行形式验证。
验证结束，结果出现 “ Verify”fail 的对话框，提示两种功能不一致。
6. Debug
2.设置Implementation Design
点击Implement按钮，在Read Design Files 中点击 Verilog，出现Add verilog files对话框，
选择gate目录下的verlog网表文件fifo.vg，点击Load Files加载网表文件fifo.vg，
由于fifo.v 是源代码，fifo.vg只是综合的源代码，没有添加SCAN和JTAG链。故可以省略这一步
检查reference design4和.MImatpclehmention design的比较
点是否匹配点击Match按钮，选择Run Matching按钮，进行匹
配检查。出现下图结果：没有不匹配的比较点，可以进入下
2.1加载Technology library
选择Read DB Libraries按钮，点击DB…按钮，出现 Add DB Files对话框
选择lib目录下的lsi_10k.db库文件，（确保Read as share library被选中）点击LOAD Files，加载库文件。
选择 Set Top Design, 在 Choose a library 中选择 WORK (Design Library),
1.1读取源文件
在对话框中选择：Rtl目录下的fifo.v文件，点击Open按钮,打开fifo.v源代码。如图：

synopsys iC Compiler II 数据手册说明书

DATASHEETOverview IC Compiler™ II is the industry leading place and route solution that delivers best-in-class quality-of-results (QoR) for next-generation designs across all market verticals and process technologies while enabling unprecedented productivity. IC Compiler II includes innovative for flat and hierarchical design planning, early design exploration, congestion aware placement and optimization, clock tree synthesis, advanced node routing convergence, manufacturing compliance, and signoff closure.IC Compiler II is specifically architected to address aggressive performance, power, area (PPA), and time-to-market pressures of leading-edge designs. Key technologies include a pervasively parallel optimization framework, multi-objective global placement, routing driven placement optimization, full flow Arc based concurrent clock and data optimization, total power optimization, multi-pattern and FinFET aware flow and machine learning (ML) driven optimization for fast and predictive design closure. Advanced Fusion technologies offer signoff IR drop driven optimization, PrimeTime ® delay calculation within IC Compiler II, exhaustive path-based analysis (PBA) and signoff ECO within place and route for unmatched QoR and design convergence. F U S I O N D E S I G N P L A T F O R M PrimeTime, StarRC, PrimePower,IC Validator, RedHawk Analysis Fusion Fusion Compiler IC Compiler II Design Compiler NXT TestMAX F o r m a l i t y ECO Fusion S i g n o f f F u s i o n S i g n o f f F u s i o n Test Fusion Figure 1: IC Compiler II Anchor in Synopsys Design PlatformAccelerating DesignClosure on AdvancedDesignsIC Compiler II Industry Leading Place and Route SystemKey BenefitsProductivity• The highest capacity solution that supports 500M+ instances with a scalable and compact data model• A full suite of design planning features including transparent hierarchical optimization• Out-of-the-box simple reference methodology for easy setup• Multi-threaded and distributed computing for all major flow steps• Golden signoff accuracy with direct access to PrimeTime delay calculationPPA• Unified TNS driven optimization framework• Congestion, timing, and power-driven logic re-synthesis• IEEE 1801 UPF/multi-voltage support• Arc-based concurrent clock and data optimization• Global minima driven total power optimizationAdvanced Nodes• Multi-pattern and FinFET aware design flow• Next generation advanced 2D placement and legalization• Routing layer driven optimization, auto NDR, and via pillar optimization• Machine learning driven congestion prediction and DRC closure• Highest level of foundry support and certification for advanced process nodes• IC Validator in the loop signoff driven DRC validation and fixingAdvanced Fusion Technology• Physically aware logic re-synthesis• IR drop driven optimization during all major flow steps• PrimeTime delay calculation based routing optimization for golden accuracy• Integrated PrimeTime ECO flow during routing optimization for fastest turnaround timeEmpowering Design Across Diversified ApplicationsThe dizzying pace of innovation and highly diversified applications across the design spectrum is forcing a complete rethink of the place and route systems to design and implement differentiated designs in a highly competitive semiconductor market on schedule. Designers on emerging process nodes must meet aggressive PPA and productivity goals. It essentially means efficient and intelligent handling of 100s of millions of place-able instances, multiple levels of hierarchy, 1000s of hard macros, 100s of clocks, wide busses, and 10s of modes and corners power domains and complex design constraints and process technology mandates. Emphasis on Designer ProductivityIC Compiler II is architected from the ground up for speed and scalability. Its hierarchical data model consumes 2-3X less memory than conventional tools, boosting the limits of capacity to 500M placeable instances and beyond. Adaptive abstraction and on-the-fly data management minimize memory requirements and enable fast responsive data manipulation. Near-linear multi-core threading of key infrastructural components and core algorithms such as database access and timing analysis speed up optimization at all phases of design. Patented, lossless compact modeling and independent R and C extraction allow handling more modes and corners (MCMM scenarios) with minimal runtime impact.IC Compiler II has built-in Reference Methodology(RM) that ensures fast flow bring up. This RM Flow is Foundry Process/Design Type specific to ensure a robust starting point and seamless bring up. IC Compiler II has direct access to the Golden PrimeTime delay calculation engine to minimize ECO iterations.IC Compiler II’s new data model enables designers to perform fast exploration and floorplanning with complex layout requirements. IC Compiler II can create bus structures, handle designs with n-levels of physical hierarchy, and support Multiply Instantiated Blocks (MIBs) in addition to global route driven pin assignment/feedthrough flow, timing driven macro placement, MV area design planning.A design data mismatch inferencing engine analyzes the quality of inputs and drives construct creation on the fly, delivering design insights even with “incomplete” data early in the design cycle. Concurrent traversal of logical and physical data models enables hierarchical Data-Flow Analysis (DFA) and fast interactive analysis through multi-level design hierarchies and MIBs. Data flow and feedthrough paths highlighted in Figure 2 allow analysis and manipulation through n-levels of hierarchy to complete early design exploration and prototyping.Figure 2: Fast interactive analysis through multiple-levels of physical hierarchy and MIBPipeline-register-planning shown in Figure 3, provides guidance for optimal placement to meet the stringent timing requirementsof high-performance designs. Interactive route editor integrated which is advanced node aware shown in Figure 4, allows intricate editing and routing functions, including the creation of special signal routes, buses, etc.Figure 3: Pipeline register placement enables superior QoR for designs with complex busesAchieving Best Performance, Power, Area, and TATIC Compiler II features a new optimization framework built on global analytics. This Unified TNS Driven Optimization framework is shared with Design Compiler NXT synthesis to enable physically-aware synthesis, layer assignment, and route-based optimization for improved PPA and TAT. Multi-Corner Multi-Mode (MCMM) and Multi-Voltage (MV) aware, level-based analytical algorithms continuously optimize using parallel heuristic algorithms. Multi-factor costing functions deliver faster results on both broad and targeted design goals. Concurrent PPA driven logic remapping, rewiring, and legalization interleaved with placement minimizes congested logic, resulting in simple localized logic cones that maximize routability and QoR.IC Compiler II minimizes leakage with fast and efficient cell-by-cell power selection across HVT, SVT and LVT cells and varying channel lengths. Activity-driven power optimization uses VCD/ SAIF, net toggle rates, or probability functions to drive placement decisions and minimize pin capacitances. Multi-bit register banking optimizes clock tree structures, reduces area, and net length, while automatically managing clock, data, and scan chain connections.Advanced modeling of congestion across all layers highlighted in Figure 4 provides accurate feedback throughput the flow from design planning to post- route optimization.Figure 4: Intelligent and accurate analysis for congestion and powerIC Compiler II introduces a new Concurrent Clock and Data (CCD) analysis and optimization engine that is built-in to every flow step resulting in meeting both aggressive performance and minimizing total power footprint. ARC-based CCD optimization performs clock tree traversal across all modes/corners in path-based fashion to ensure optimal delay budgeting.Robust support for clock distribution enables virtually any clock style, including mesh, multi-source, or H-tree topologies. Advanced analysis and debugging features perform accurate clock QoR analysis and debugging as highlighted in Figure 5.Figure 5: Accurate clock QoR analysis and debugging (a & b) Abstracted clock graph and schematic.(c) Latency clock graph. (d) Colored clock tree in layout.IC Compiler II features many innovative technologies that make it the ideal choice for high-performance, energy-efficient Arm®processor core implementation, resulting in industry-best milliwatts/megahertz (mW/MHz) for mobile and other applications across the board. Synopsys and Arm work closely together to offer optimized implementation of popular Arm cores for IC Compiler II,with reference flows available for Arm Cortex®-A high-performance processors and Mali GPUs. In addition, Arm offers off-the-shelf Artisan® standard cell and memory models that have been optimally tuned and tested for fast deployment in an IC Compiler II environment. Continuous technology innovation and close collaboration makes IC Compiler II the leading choice for Arm-based high- performance design.Highest Level of Advanced Node Certification and SupportIC Compiler II provides advanced node design enablement across major foundries and technology nodes—including 16/14nm,12/10nm, 7/5nm, and sub-5nm geometries. Zroute digital router technology ensures early and full compliance with the latest design rules required for these advanced node technologies. Synopsys collaborates closely with all the leading foundries to ensure that IC Compiler II is the first to deliver support for early prototype design rules and support for the final production design rules. IC Compiler II design technologies maximize the benefits of new process technologies and offer optimal return on investment for cutting-edge silicon applications.IC Compiler II advanced node design support includes multi-pattern/FinFET aware placement and routing, Next-generation advanced 2D placement and legalization, routing layer driven optimization, auto NDR, and via pillar optimization. IC Validator in the loop provides signoff DRC feedback during Implementation.Foundry ﬁll Track based ﬁllFigure 6: IC Validator In-Design metal fill color aware metal fill, optimized for density and foundry requirementsMachine learning driven congestion prediction and DRC closure allow for fastest routing convergence with best PPA. Multiple sets of training data are used to extract key predictive elements that guide the pre-route flow.Advanced Fusion TechnologyThe Fusion Design Platform™ delivers unprecedented full-flow QoR and time-to-results (TTR) to accelerate the next wave of semiconductor industry innovation. The industry’s first AI-enhanced, cloud-ready Design Platform with Fusion Technology™ isbuilt from Synopsys’ market-leading, massively-parallel digital design tools, and augmented with innovative capabilities to tacklethe escalating challenges in cloud computing, automotive, mobile, and IoT market segments and accelerate the next wave of industry innovation.Fusion Technology redefines conventional EDA tool boundaries across synthesis, place-and-route, and signoff, sharing integrated engines across the industry’s premier digital design products. It enables designers to accelerate the delivery of their next-generation designs with the industry-best QoR and the TTR.©2019 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks isavailable at /copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.。

Synopsys软件安装步骤及说明

Fatal: At least
这是license没有正确的启动。这是有可能是因为license制作过程有问题。
在制作时需要注意license工具里面的两个文件：一为EFALicGen0.4b文件加里面的licgen.dll，该文件不能是老版本的。另一文件为EFALicGen0.4b/packs/synopsys.src,license启动不成功很有可能是因为该文件导致生成的license不能启动。
SERVER计算机主机名MAC端口
DAEMONsnpslmdSCL文件夹路径/linux/bin/snpslmd
例如：我安装SCL的目录为/eda_tools/synopsys/scl10.9，查询计算机信息如图。
故：SERVER和DAEMON行应该为(端口可根据需要填写，我这里只是示例)：
SERVERlocalhost.localdomain000c2988ffc628000
2、软件安装….………………………………………………………..3
3、SCL安装….………………………………………………………...5
4、制作license……………………………………………………....6
5、环境配置………………………………..…………………..…..11
6、说明……………………………………………………………..…..12
Unable to obtain feature 'Design-Analyzer ' because:
Error: Can't communicate with the license server. (SEC-12)
Pleasecontact atroot@(none), who isyour local Synopsys license administrator for Synopsys site 000.

Synopsys SoC 架构设计指南说明书

IP加速DesignWare IP，针对您的SoC进行调整从一开始就保证正确的 SoC 架构每一个复杂的 SoC 设计都是在巨大的上市时间压力下创建出来的。

随着软件内容的增加以及更多IP （以及更复杂IP）被集成，设计人员面临着在不过度设计 SoC 的情况下性能、功耗和面积目标等诸多挑战。

作为您的设计团队的一员，Synopsys 的 SoC 架构设计顾问将帮助您的 SoC 在正确的起点开始。

顾问们已经准备好将他们多年的设计手机、汽车、网络和物联网 SoC 的专业技能应用到您独特的设计中。

这些顾问将在以下方面应用并分享他们的深厚知识：• CPU、DSP和 ASIP 功能• 制定低功耗策略• 关键模块的设计（RTL，ASIP）• PPA 估算• 内存架构，总线带宽/延迟• 验证和基于 FPGA 的原型设计与您的 SoC 一样独特的 IP在为您的快节奏的市场打造 SoC 时，如果能够把针对您的设计调整的 IP 整合到一起，这将会为您带来竞争力上的优势。

然而现成的 IP 已经不足以应对您的设计挑战。

我们期待 IP 供应商能提供更多解决方案，包括简化 IP 配置和集成以及加速软件开发等。

Synopsys的“ IP 加速”计划将重新定义您对 IP 供应商的期望，它能帮助您以更少的功夫、更低的风险和更快的上市速度成功地将IP集成到您的 SoC 中。

“Synopsys团队提出了详细的建议来测试并构建我们 AI SoC的复杂接口，帮助确保我们按时启动项目。

”〜一家领先的人工智能计算公司的研发总监预先验证的 IP 子系统，可由您或我们的团队进行定制随着硬件和软件复杂性的增加，您需要更先进的集成 IP 解决方案来满足您快速的项目进度，同时还不能影响质量。

无论您需要单个控制器和 PHY 集成、多种协议的组合或者是需要具有处理器及软件堆栈的完整子系统，Synopsys 专家都能够交付针对您的 SoC 进行优化的 IP 子系统。

Formality使用指南

目录说明 (2)一.验证RTL与GATE网表 (2)（一）图形用户界面进行形式验证 (2)1.设置reference design (3)1.1读取源文件 (3)1.2设置搜索目录 (4)1.3设置搜索目录 (4)1.4加载源文件 (5)1.5设置fifo为reference的顶层 (6)2.设置Implementation Design (7)2.1加载Technology library (7)3.设置环境(Setup) (8)4.Match (8)5.Verify (9)6. Debug (9)7.清理工作 (13)（二）命令行方式进行形式验证 (13)命令行方式运行 (13)二. 验证GATE网表和插入扫描链的GATE网表 (14)1. set referenc design (14)2. set implementation design (15)3. setup (16)设置SCAN链的功能无效 (16)4. match (17)5. verify (18)三. 验证带有扫描链和JTAG链的GA TE网表和插入扫描链的GATE网表 (19)检查fifo_with_scan_jtag.v和fifo_with_scan.v一致性 (19)禁止scan和jtag功能 (20)运行match (21)Verify (21)说明FiFo的Tutorial目录下包含以下几个子目录：Rtl：fifo的RTL源代码；包含fifo.v, gray_counter.v, push_ctrl.v, gray2bin.v, pop_ctrl.v, rs_flop.v。

Lib：门级网表需要的技术库；包含lsi_10k.db。

Gate：综合的门级网表；包含fifo.vg 和fifo_mod.vg。

Gate_with_scan：插入扫描链的门级网表；包含fifo_with_scan.v。

Gate_with_scan_jtag：带有扫描链和JTAG链的门级网表；包含fifo_with_scan_jtag.v。

Formality使用指南

Lib：门级网表需要的技术库；包含lsi_10k.db。

Gate：综合的门级网表；包含fifo.vg 和fifo_mod.vg。

Gate_with_scan：插入扫描链的门级网表；包含fifo_with_scan.v。

Gate_with_scan_jtag：带有扫描链和JTAG链的门级网表；包含fifo_with_scan_jtag.v。

Synopsys IC Complier设计流程指导书_Basic Flow

mem.db
1- 16
Shortcuts…
import_designs orca.v \ -format verilog \ -top ORCA_TOP
Format can be verilog, db, ddc
Replaces: read_verilog –netlist orca.v current_design ORCA_TOP uniquify link save_mw_cel –as ORCA_TOP
1- 1
Unit Objectives
After completing this unit, you should be able to: Create a Milkyway library to hold your design Read all necessary files required to run
DEF MW
1- 6
Unit Flow: From Setup to Output
Logical Data Setup Physical Data Setup
place_opt clock_opt route_opt
Analysis Output
1- 7
Logical Data
LLooggicicaal lDDaatata Physical Data
Unit 1 Unit 5 Unit 2 Unit 3 Unit 6 Unit 7
1- 4
Placement, CTS, Routing with Optimizations
Gate-Level Netlist
IC Compiler
IP Optional: Floorplan
Placed, Routed & Optimized Design with Clock Trees

synopsys formality工具的工作原理

synopsys formality工具的工作原理
Formality工具是一种静态形式化验证工具，用于验证硬件设
计中的等价性和功能正确性。

Formality工具的工作原理如下：
1. 输入处理：Formality工具从设计的RTL源代码和目标网表
中获取输入。

它还将读取指定的约束、特定的规范和目标等。

2. 优化：Formality工具将对输入进行优化，以简化设计结构
并提高验证效率。

它可以识别并删除冗余的逻辑，并应用一系列规则和算法来缩小设计。

3. 等价性检查：Formality工具会通过比较源代码和目标网表，验证其等效性。

它会检查所有的语义变化、优化和转换，以确保两者之间的行为一致。

4. 错误检测：如果Formality工具发现了有不一致的设计部分，它将生成错误报告，指示检查器发现了源代码和目标网表之间的等效性问题。

报告将包含有关问题的详细信息和调试建议。

5. 快速复核：如果源代码和目标网表之间的等效性已经验证过，Formality工具可以生成一个快速复核文件，以便在日后快速
重新验证设计的等效性。

通过这些步骤，Formality工具能够在不依赖仿真的情况下验
证设计的等效性和正确性。

它可以在RTL和后端设计之间进行综合和验证，提供了更加全面和准确的验证结果。

Synopsys系列软件安装说明

Synopsys系列软件安装说明magellan。

Synopsys软件一共有三个：VCS、formality、安装这是一套验证软件，现在我们说一下它们的安装流程：VWmare1.安装执行可执行文件。

安装无注意事项。

按照步骤安装直到完成。

REDHAT4.22.安装REDHAT 。

加载运行虚拟机，在file选项下选择new下的virtual mashine在左下角虚拟光驱中加载接下来按照提示加载在提示加载其他的光盘时，disc1.这。

加载之后记得connect（安装前提是硬盘空间最小要15G）剩下的光盘镜像，样直到安装完成。

3.安装VMware Tools开始启动系统，然后用安装完系统后，点击start this virtual machine账号登陆，密码就是在安装系统时自己设置的密码。

在上面的工具栏菜单root界面外，不LINUX选择VM\install VMware Tools（目的是鼠标可以直接移动到共享文件windowsLINUX界面的大小,同时也可以实现和再需要Ctrl+Alt;设置拷贝到任何目VMwareTools-6.0.0-45731.tar.gz夹），生成VmWare Tools后将zxvf录下，然后在终端中的该目录下用tar –命令进行解压，然后进入解压后得到的VMwareTools-7.8.4-126130.tar.gz一切选择./ vmware-install.pl进行安装(vmware-tools-distrib的目录，执行默认就行)。

安装目录下的一个另一种方法：如果第一种方法不行，出现错误，就加载VM里面有个文件linux.iso镜像，在系统中打开cd-romhomeTools压缩包。

把它拷贝到VMwareTools-8.1.3-203739.tar.gz就是VMwarexvzfVMwareTools-8.1.3-203739.tar.gz 解压缩文件，文件夹下，然后用tar – ./vmware-install.pl 进行安装。

PrimeTime使用说明(中文)

摘要：
本文介绍了数字集成电路设计中静态时序分析（Static Timing Analysis）和形式验证（Formal Verification）的一般方法和流程。这两项技术提高了时序分析和验证的速度，在一定程度上缩短了数字电路设计的周期。本文使用 Synopsys 公司的 PrimeTime 进行静态时序分析，用 Formality 进行形式验证。由于它们都是基于 Tcl（Tool Command Language）的工具，本文对 Tcl 也作了简单的介绍。
Tcl 与 pt_shell 的使用
6
第三章 Tcl 与 pt_shell 的使用
Tcl 是 Tool Command Language 的缩写，由于 PrimeTime 的命令语言是基于 Tcl 标准的，所以在这一章里我想大致介绍一下 Tcl 在 PrimeTime 中的基本使用。除了一些最常用的 Tcl 命令之外，主要介绍了 pt_shell 中有关对象和属性的操作。
7.2 一些基本概念
7.2.1 Reference Design 和 Implementation Design
7.2.2 container
7.3 读入共享技术库
7.4 设置 Reference Design
7.5 设置 Implementation Design
7.6 保存及恢复所作的设置
7.7 验证
PrimeTime 简介
4
在数字集成电路设计的流程中，版图前、全局布线之后已经版图后，都可以使用 PrimeTime 进行静态时序分析。
§2.2 PrimeTime 进行时序分析的流程使用 PrimeTime 对一个电路设计进行静态时序分析，一般要经过下面的步骤： 1）设置设计环境在可以进行时序分析之前，首先要进行一些必要的设置和准备工作。具体来说包括了： ² 设置查找路径和链接路径 ² 读入设计和库文件 ² 链接顶层设计 ² 对必要的操作条件进行设置，这里包括了线上负载的模型、端口负载、驱动、以及转换时间等 ² 设置基本的时序约束并进行检查 2）指定时序约束 (？？timing assertions/constraints) 包括定义时钟周期、波形、不确定度(uncertainty)、潜伏性(latency)，以及指明输入输出端口的延时等。 3）设置时序例外(？？timing exceptions)：这里包括了： ² 设置多循环路径（multicycle paths） ² 设置虚假路径（false paths） ² 定义最大最小延时、路径的分段(path segmentation)以及无效的 arcs 4）进行时序分析：在作好以上准备工作的基础上，可以对电路进行静态时序分析，生成 constra -int reports 和 path timing reports。以上仅仅是 PrimeTime 进行静态时序分析的简单流程，在本文以下的部份中将会有更详细的叙述。

Synopsys系列软件安装说明

Synopsys系列软件安装说明安装Synopsys软件一共有三个：VCS、formality、magellan。

这是一套验证软件，现在我们说一下它们的安装流程：1.安装VWmare执行可执行文件。

安装无注意事项。

按照步骤安装直到完成。

2.安装REDHAT4.2运行虚拟机，在file选项下选择new下的virtual mashine。

加载REDHAT disc1.在提示加载其他的光盘时，在左下角虚拟光驱中加载接下来按照提示加载剩下的光盘镜像，加载之后记得connect（安装前提是硬盘空间最小要15G）。

这样直到安装完成。

3.安装VMware Tools安装完系统后，点击start this virtual machine开始启动系统，然后用root账号登陆，密码就是在安装系统时自己设置的密码。

在上面的工具栏菜单选择VM\install VMware Tools（目的是鼠标可以直接移动到LINUX界面外，不再需要Ctrl+Alt;设置LINUX界面的大小,同时也可以实现和windows共享文件夹），生成VmWare Tools后将VMwareTools-6.0.0-45731.tar.gz拷贝到任何目录下，然后在终端中的该目录下用tar –zxvfVMwareTools-7.8.4-126130.tar.gz命令进行解压，然后进入解压后得到的vmware-tools-distrib的目录，执行./ vmware-install.pl进行安装(一切选择默认就行)。

另一种方法：如果第一种方法不行，出现错误，就加载VM安装目录下的一个linux.iso镜像，在系统中打开cd-rom里面有个文件VMwareTools-8.1.3-203739.tar.gz就是VMware Tools压缩包。

把它拷贝到home 文件夹下，然后用tar –xvzfVMwareTools-8.1.3-203739.tar.gz 解压缩文件，然后执行在解压好的文件路径下输入命令执行./vmware-install.pl 进行安装。

Synopsys软件质量与合规性指南说明书

How to Bypass Code Issues, Keep Regulators Away, and Stay Out of the News4 Software Compliance Gotchas to AvoidTable of contentsIntroduction to software quality and compliance (1)Who really cares about software compliance? (2)‘Checkbox’ standards compliance won’t prevent massive web app data breaches (3)How to avoid it (4)Documenting compliance with data privacy regulations is difficult (5)How to avoid it (6)Modern software compliance standards in regulated markets are complex (7)How to avoid it (8)Software compliance can slow down development (9)How to avoid it (10)Bringing it all together (11)Introduction to software quality and complianceWho really cares about software compliance?Organizations rely more and more on software to handle sensitive data, automate business processes, and even protect people’s safety. As a result, the consequences of software flaws have grown exponentially. For this reason, auditors and government agencies have drafted coding standards to help ensure mission-critical applications don’t contain key software problems.‘Checkbox’ standards compliance won’t prevent massive web app data breachesMany of these vulnerabilities are tracked by the communities that maintain web app security standards such as OWASP Top 10 and CWE/ Clearly, software standards can help organizations reduce the vulnerabilities in their software, but compliance alone isn’t enough.A software standard can demand that you encrypt all data at rest, for example, but it can’t detect whether you’ve implemented a cryptographic function correctly. In addition, software standards often lag behind new technologies (e.g., cloud, blockchain), opening up other opportunities for hackers.Therefore, instead of focusing on perimeter security or checking boxes on software standards, organizations can better address web app security by building secure software that is difficult to hack.The outcome of having tens of millions of customers’ personally identifiable information (PII) exposed is a PR, financial, and legalDocumenting compliance with data privacy regulations is difficultOrganizations that deal with PII in areas governed by data privacy regulations have to create and maintain a great deal of documentation. For example, they must assemble reports manually (including screenshots of security settings), fill out questionnaires, update policies and procedures, and complete self-assessments and/or undergo lengthy, expensive third-party audits—annually in some cases. They must update all this documentation with regular security scans to make sure PII is still secure as it flows through the organization or sits in storage.Government and industry data privacy regulations make it public policy to protect customer data adequately—with substantial financial penalties and possible criminal charges for extreme violations. Many data privacy standards extend well beyond the realm of application security to provide guidelines for a complete sensitive-data protection program. Considering the increasing rate and consequences of hacks via exploitable software vulnerabilities, organizations are starting to recognize that application security must be part of their data protection strategy.How to avoid itWhen it comes to government and industry data privacy standards, getting the official stamp of compliance is essential to your go-to-market strategy. So it’s critical to demonstrate compliance through well-documented reporting. Auditors, top executives, and concerned customers all demand proof of compliance, so being able to generate an electronic paper trail is vital.What you need: Tools with extensive reporting functionality, or a tool or platform that can combine data from other tools and generate the reports you need. Customizable reports will help you meet proof-of-compliance requirements for complex industry standards such as AUTOSAR and DO-178C.Modern software compliance standards in regulated markets are complexFor organizations that operate in highly regulated markets (e.g., automotive, aviation, financial services) with complex standards, software development teams need solutions that make testing, enforcing, and demonstrating software quality and software compliance easier.On any development team, skill sets vary as to secure coding practices and writing functional code. Development leaders struggle to create consistent, repeatable processes that enable developers with different strengths to find and fix security weaknesses quickly.In addition, the raw volume of applications in modern organizations can be overwhelming. Going through them manually to achieve software compliance is neither scalable nor realistic. Whatever the compliance strategy, it needs to scale to hundreds of projects and millions of lines of code (LOC).But before implementing a strategy to achieve compliance, organizations must understand the unique requirements demanded by the software standards that apply to them.How to avoid itIn embedded applications, software issues can manifest themselves physically—potentially causing harm to consumers.What you need: Tools that can help your developers write clean software and find bugs in embedded applications early in the SDLC, before products ship.Considering the scale and complexity of modern application portfolios, the ability to track and manage specific issues named in regulations will keep your team focused on the most important items.What you need: Tools that automatically assign severity—based on compliance—to issues and triage them accordingly. The ability to sort and filter issues by severity, standard, and other criteria is also valuable.Software compliance can slow down developmentSoftware compliance requires software security and quality testing. A key challenge to producing compliant applications is to conduct this testing without disrupting existing development processes.The developer’s primary job is to produce functional software by a certain deadline. But as stakeholders pile on feature requests and competitive timeframes shrink, development teams have become overburdened, understaffed, and time-crunched. And while DevOps has accelerated application delivery by supporting continuous development with quick release cycles, it has also changed how development teams should approach software compliance.Faced with continuing pressure to do more with less, developers resist new processes that add friction and complexity to their day-to-day routine. In addition, anything that disrupts their development workflows, causing them to push or miss their project deadlines, puts the organization at a competitive disadvantage.So even though testing is essential for compliance, many developers have already become disenchanted by their experiences using testing tools that can’t match the pace of modern software development. Treating compliance and testing as a separate step from development—basically, asking developers to “bolt compliance on” late in the workflow to conform with standards—is a surefire way to slow down development.How to avoid itTo integrate software compliance into the SDLC without slowing down development, managers must give developers the flexibility to test for compliance in a way that works best for them. Again, developers’ No. 1 objective is to produce functional applications on time.If compliance strategies work against this goal, developers are unlikely to embrace them. But if developers can code in their integrated development environment (IDE) and perform compliance processes at the same time, they can catch errors earlier, when it’s easier and less costly to correct them—reducing the number of issues in long revision loops. Other teams may prefer to add compliance as a gate in the CI/CD pipeline to align with their automation strategy. Either way, managers should strive to implement compliance organically into the SDLC and developers’ day-to-day processes and avoid changing existing workflows too much.What you need: Tools that fit into existing pipelines and don’t force developers to add even more work to their workflow. Tools that offer a range of integrations, plugins, and APIs can help you inject security into existing processes rather than adding a new process.Bringing it all togetherWhether you’re trying to move beyond mere “checkbox” software compliance and protect web applications under constant assault from multiple attack vectors, create and maintain customer data privacy documentation per government requirements, conform to complex modern software compliance standards in regulated markets, integrate application security into the development process, or some combination of the above, the world of software quality and compliance is tricky. Gotchas lurk in the least likely places and sometimes hide in plain sight, waiting to ensnare the less vigilant.No single software testing solution has all the answers. But a fully thought-out, comprehensive application security program that combines technology and best practices is the strongest strategy for keeping the regulators out of your offices and your organization out of the headlines. It will pre-empt these gotchas by bypassing coding issues and finding as many bugs and vulnerabilities as possible, as early as possible.But application security must not come at the expense of development efficiency. It must be a seamless part of the workflow, not a separate process, so that developers see security as an organic part of making high-quality software. Finally, documentation mustbe an integrated part of the solution, not a manual process that takes weeks or even months to complete. An automated testing and reporting methodology must be available to help document compliance with government and industry security standards and data privacy regulations.Not sure where to start?Let Synopsys help you build secure, high-qualitysoftware faster.READY TOLEARN MORE?Synopsys helps development teams build secure, high-quality software, minimizing risks while maximizing speed and productivity. Synopsys, a recognized leader in application security, provides static analysis, software composition analysis, and dynamic analysis solutions that enable teams to quickly find and fix vulnerabilities and defects in proprietary code, open source components, and application behavior. With a combination of industry-leading tools, services, and expertise, only Synopsys helps organizations optimize security and quality in DevSecOps and throughout the software development life cycle.For more information, go to /software.Synopsys, Inc.185 Berry Street, Suite 6500San Francisco, CA 94107 USAContact us:U.S. Sales: 800.873.8193International Sales: +1 415.321.5237Email: *********************。

formality简介

formality简介Formality简介Formality，synopsis的工具，我们常说的形式验证、formal check 都是用它做的。

先看个rtl对DC netlist的脚本：#-------------------------------------------------------------------------# Formal check for Capture.vhd ( rtl vs dc_nlist )#-------------------------------------------------------------------------set TOP_REF Captureset TOP_IMP Captureset REF_NAME Capture.vhdset IMP_NAME Capture.vset REF_PATH /home/project/9602-360-100/Dig/d1/work_jh/synop199/rtlset IMP_PATH /home/project/9602-360-100/Dig/d1/work_jh/synop199/dc1/nlist set RPT /home/project/9602-360-100/Dig/d1/work_jh/synop199/fm/rpt set hdlin_dwroot /edatools/synopsys/syn_vX-2008.9-SP4set verification_failing_point_limit 2000set synopsys_auto_setup trueset_svf /home/project/9602-360-100/Dig/d1/work_jh/synop199/dc1/default.svf set search_path ". /home/project/9602-360-100/Dig/d1/synop199 //edatools/synopsys/syn_vX-2008.9-SP4/libraries/syn"read_db {chrt35_ss_75_1pt3_SYNOPSYS2_MMSIM.db dw_foundation.sldb}read_vhdl -r $REF_PATH/$REF_NAME -l work > $RPT/read_design.rptset_top $TOP_REF > $RPT/set_top.rptreport_hdlin_mismatch > $RPT/rpt_hdlin_mismatch.rptread_verilog -i $IMP_PATH/$IMP_NAME -l work >> $RPT/read_design.rpt set_top $TOP_IMP >> $RPT/set_top.rpt #set_constant -type port r:/.../ 0#set_constant -type port i:/.../ 0match > $RPT/match.rptreport_matched_points > $RPT/matched_point.rptreport_unmatched_points > $RPT/unmatched_point.rptreport_loops -limit 0 -unfold > $RPT/loops.rptverify#以上内容可以放在一个文件里作为脚本，调用方法就是在fm_work下$ fm_shell –f ../scripts/fm_rtl2dc.tcl如果成功要看详细信息或者失败要debug的话，再输入start_gui，进入-GUI模式。

Synopsys coreTools IP基于设计和验证概述说明书

Synopsys coreToolsIP Based Design and VerificationOverviewThe Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in SoC or platform design time and achieve the highest QoR in the implementation of the design.The coreTool family includes:coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge and design intent of the IPand provide graphical or command based configuration menus for the IP. It supports the packaging of all the different model views of the IP needed engineering teams. This reduces IP support costs, improves quality and IP packaged with coreBuilder is fully compliant with the IP-XACT specification.coreAssembler™– an open IP assembly tool that automatically generates the interconnect and configured RTL, as well as documenting the block and system configuration details and design testbench. When combined with coreBuilder, entire subsystems can be packaged as coreKits enabling the easy creation configurable market targeted platforms. In addition to assembly and configuration designers are able to generate a starting testbench configured for the design so they can begin to validate there design. coreAssembler also will generate the IP-XACT XML for the design.coreConsultant™– the utility package for configuring, implementing and validating individual IP blocks packaged with coreBuilder. coreConsultant will also generate the IP-XACT XML for the IP block.FeaturesIntuitive graphical or script-based environment•Built-in interfaces to Synopsys tools, including:•Design Compiler—®Physical Compiler—®Power Compiler—®TetraMAX—®PrimeTime—®Formality—®VCS—®Automatic testbench generation with DesignWare VIP for •AMBA and AXI which supports VMM and/or traditional testbenchesSupports mixed-language HDL designs•Flexible TCL interface for tool customization•Knowledge-based assembly of IP blocks•Full IP-XACT support including TGI with automatic XML •generationBenefitsFull support for packaging, integrating, and assembling IP •Allows packaging of IP at multiple levels of abstraction, •including:RTL—Instruction set models—Transaction level models—Bus functional models—Verification test suites—Hard macros—Automatic assembly of pre-designed IP blocks reduces •design timeReduces design integration and support costs•Figure 1. IP Capture with coreBuilder.Figure 2. Using coreAssembler with coreBuilder for packaging IP-based design platforms and IP integration.coreBuilderThe coreBuilder tool is language-independent, which enables the packaging of IP blocks with a step-by-step process.This ensures that all of the design requirements have been followed, allowing the easy enforcement of an IP quality flow. Additionally, the design intent is captured, bringing the detailed knowledge of the IP to the designers’ desktop. IP packaged with coreBuilder can be easily configured and integrated inthe SoC. Figure 1 shows the IP capture flow with coreBuilder. coreBuilder not only provides the environment to capture all of the files related to the IP block, but also allows the IP designer to capture the IP intent as well. IP packaged with coreBuilder is fully compliant with the IP-XACT specification.coreAssemblerThe coreAssembler tool has an intuitive graphic or command based interface that speeds the designer through the assembly, configuration, and implementation of an IP-based design. The coreAssembler tool also provides the infrastructure for building a complete SoC design and verification environment.coreAssembler uses a knowledge-based design and verification flow that automates the tedious task of connecting, configuring and verifying all of the IP components in the SoC. This eliminates the risk of assembly and configuration errors by automatically generating the configured RTL and with the interface to the Galaxy™ platform implementation scripts are generated based on the designers intent helping to ensure highest QoR with significant reductions in design time. IP-XACT XML is also generated from coreAssembler.In addition to integrating packaged IP into the design, coreAssembler allows the easy integration of new, unpackaged IP or IP compliant with the IP-XACT specification. With the open TCL interface, designers can easily include design flow customizations into the coreAssembler environment.coreBuilder + coreAssemblercoreBuilder combines with coreAssembler to provide designers with an open and customizable environment for the creation of IP-based subsystems as well as product design platforms. IP that has been packaged with coreBuilder can easily be included with controlled configuration options targeted at specific market applications into design platforms assembled with coreAssembler.In addition to the ability to include packaged IP, new design specific IP can be easily integrated into the design platform.Figure 2 shows how coreAssembler integrates IP into a design platform.coreConsultantcoreConsultant guides an IP integrator through the configu-ration, verification, and implementation of a single core packaged with coreBuilder into a coreKit and generates theIP-XACT XML. coreConsultant includes the graphic and command line options for use along with built-in interfaces to the Discovery and Galaxy platforms speeding the implemen-tation and verification of an IP core.coreAssembler2Synopsys, Inc.700 East Middlefield Road Mountain View, CA ©2008 Synopsys, the Synopsys logo, Design Compiler, Physical Compiler, Power Compiler, PrimeTime, TetraMAX, Formality and VCS areregistered trademarks and coreBuilder, coreAssembler, coreConsultant, DC FPGA, Discovery and Galaxy are trademarks of Synopsys, Inc. All otherproducts or service names mentioned herein are trademarks of their respective holders and should be treated as such. Printed in the U.S.A. 06/08.PS.WO.08-16501IP-XACT SupportThe Synopsys suite of IP reuse tools have been and continue to be used in the development and testing of the IP-XACT specifi-cation. IP packaged with coreBuilder can be used in any IP-XACT compliant SoC design tool. Designs, platforms or subsystems implemented in coreAssembler can include components that are IP-XACT compliant into the subsystem Supported Platforms and Simulators Solaris, HP, and Linux Verilog Simulators Synopsys VCS Cadence NC-Verilog ® MTI ModelSim-VerilogVHDL Simulators Synopsys VCS MX Cadence NC-VHDL MTI ModelSim-VHDLFor a complete directory of Synopsys IP visit: /ipdirectoryFor more information on DesignWare IP, visit /designware-ipFigure 3. SPIRIT Schema and Generator Interface.Environment Address map Component Configuration。

Formality_Basic_Lab_Instruction

Overview of Formality Basic LabsPurpose: These labs are designed for you to become familiar with using Formality.Content: There are four labs using Synopsys training and public-domain RTL source. The netlists were generated using DesignCompiler 2006.06-SP5 software. Be aware that there are additional SVF enhancements created by later versions of DC. (Using newer SVF files with the Auto Setup Mode in Formality will reduce or eliminate the issues in these labs.)Procedure:∙Follow the instructions for each lab.∙There is a “.solution” sub-directory with the correct result.Please compare your result with the correct result as you finish each lab.Invoke Formality in this manner to bring up the GUI:"fm_shell -gui -f runme.fms |tee runme.log" or"formality -f runme.fms |tee runme.log"FM Lab1: Basic Formality FlowObjective: This lab will introduce you to the Formality GUI bymanually reading-in two designs for verification. Then, you will create a Tcl script to perform the same verification.Lab flow:All of the necessary reference and implemention files, and librariesare included in sub-directories.Use the Formality GUI to verify the golden Verilog RTL against thegate-level Verilog netlist produced by DC. Be sure to include the SVF file. Aft erward, modify the resulting “fm_shell_command.log” fileto become a Formality TCL script.a.)Bring up the Formality GUI by us ing the command “formality” or“fm_shell –gui”. Follow the flow buttons on the GUI to read-inSVF, reference designs, implementation design with library, andthen verify.b.)The DC produced SVF file "default.svf" is located under the sub-directory "netlist_w_svf". This file is necessary for correctsetup.c.)The Verilog RTL files are located under the directory "rtl". Thetop-level design name is "mR4000".d.)The Verilog gate-level netlist "mR4000.gates.v" is located underthe directory "netlist_w_svf". The top-level design name is"mR4000".e.)The library file "tc6a_cbacore.db" is located under "lib". Thisis needed for the netlist. There are no Verilog simulationlibraries, just the .db file for this lab.f.)Use the GUI flow buttons: Guidance, Reference, Implementation,Setup (not needed), Match, Verify, Debug (not needed).g.)After completing a successful verification using the GUI, editand transform the "fm_shell_command.log" file into a Formality"runme.fms" Tcl script.h.)Use the script to run verification: "fm_shell -f runme.fms |teerunme.log".i.)Experiment with Formality commands and variables. Try some ofthe following commands:help report*report_passing_pointsman set_topman verifyreport_statusj.)Exit Formality.FM Lab2: Recognizing Simulation/SynthesisMismatch ErrorsObjective: This lab will give you practice in writing a Formality Tcl script. This design is VHDL and contains several potential differences between simulation and synthesis in their code interpretation which Formality will flag. You will need to direct Formality to ignore the differences and continue verification.By default, Formality is conservative in its interpretation of RTL. It will stop processing if it finds a difference between simulation and synthesis. You can direct it to continue by turning these error messages into warning messages. Use the following variable toaccomplish this:set hdlin_warn_on_mismatch_message “FMR_VHDL-1002 …”Use this variable before reading in the RTL into a container.(Note: If you have these types of mismatch issues using your designat work, you need to make sure that these conditions are investigated before taping-out your design.)This lab requires the use of “hdlin_dwroot”. Please edit the runme.fms u nder the …fm_basic/labs/lab2/scripts directory to correctly set the variable “hdlin_dwroot” to the top-level location of the DC software.Lab flow:1.)Use the script ./scripts/runme.fms as a starting point to createyour Formality Tcl script. Copy it to the lab2 workingdirectory.2.)You will need to complete the following:a.Read and link the reference VHDL files from the directorysrc.b.Read and link the Verilog gate-netlist.3.)Run an initial verification. Look at the error message ID.4.)Include the error message ID in the Formality script using thevariable hdlin_warn_on_mismatch_message to turn it into a warning message instead.5.)Continue this until you get a successful verification.6.)There are two other ways to accomplish this conversion ofsim/synth messages to warnings. See the ./.solution/runme.fmsscript.FM Lab3: Missing Part of the Design Objective: This lab shows an example of what happens in verificationif a piece of the reference design is missing while the implementation design remains complete. The point to this lab is to review transcript messages. These messages can provide hints to correct problems. You must change the "runme.fms" FM TCL script to get a successful verification.Lab flow:1.) Run the verification using the existing "runme.fms" script.2.)Find clues to indicate the potential problem.2a) Transcript messages:Formality debugging involves collecting information that may point to the reason why the design fails verification. Always look at the transcript messages first.Note the following warning message in the transcript:Warning: Cannot link cell '/WORK/fifo/memory' to its reference design'DW_ram_r_w_s_lat'. (FE-LINK-2)Status: Implementing inferred operators...Status: Creating black-box designs...Created technology library 'FM_BBOX' in container 'r' for black-box designsCreated black-box design 'DW_ram_r_w_s_lat' in library 'FM_BBOX'Warning: 1 blackbox designs were created for missing references. (FM-064) Formality is creating a black-box to represent a missing piece of the design. The missing piece is the DW part "DW_ram_r_w_s_lat".This is only a warning instead of an error because the customerincluded this variable setting in the FM TCL script:set hdlin_unresolved_modules black_boxOtherwise, Formality would have stopped processing the design.The problem is resolved by setting a variable to point to the top-level of the DesignCompiler tree. Formality can then find the correct DW information to generate the missing part.The Formality variable is hdlin_____________________.The DC location (for Synopsys internal training) is/global/apps/syn_2007.12-SP2.*** It is important to note that if you are paying attention to the transcript, you would stop here and correct the problem with themissing piece of the design. However, since the script continued tofinish the verification, there are some additional clues to see if you skipped the warning message.2b) Messages from matching:If you proceeded through matching, you will see several unmatched,black-box input pins. Since there are no unmatched implementationblack-boxes, this means that the reference design has a black-box that the implementation does not have.Additionally, the implementation seems to have latches that the reference design does not have. You can draw the conclusion that a big design piece is missing in the reference design.Here is a picture of the GUI unmatched points tab:2c) Graphical debugging:After running the verification and getting failing compare points, we normally would run "Diagnose". However, we already know that a large piece of the design is missing.It would be interesting to quickly view the pattern window to see how the missing design piece affected the logic cone of a failing compare point.Notice that several logic cone inputs seem to be missing in the pattern window:3.) Include the missing variable for specifying the DC tree in the FM TCL script and re-run verification. If you do not get a successfulverification, view the .solution directory.FM Lab4: Beginning DebugObjective: This lab will give you practice in using the Diagnose command and in viewing failing logic cones. This is a gate-netlist vs gate-netlist ECO verification. The ECO was done manually, and you are checking the resulting netlist against the original netlist.Lab flow:a.Run Formality script fm.tcl.formality –f fm.tcl |tee fm.logb.Start the GUI.c.Right mouse click on the first failing compare point and selectShow Patterns.d.This brings up the Pattern Viewer. The Pattern Viewer is verifyuseful in quickly identifying obvious differences in inputs to logic cones. We recommend using the Pattern Viewer first whendoing graphical debugging.e.In this case there is nothing obvious that is different betweenthe ref/impl logic cone inputs other than the same patternproduces different results at the compare point. Therefore, there is some difference in the combinational logic in the two cones.f.Close the Pattern Viewer.g.Click Diagnose button. This runs the diagnosis algorithm on allfailing compare points. You should get 1 error detected and 2 error candidates.h.The GUI automatically changes to Error Candidate window. Rightclick on failing cell U4072.i.Select Show Logic Cones.j.Select first failing compare point and click OK. The schematic will highlight the error candidate (implementation) and thematching region (reference).k.Notice that U4072 is a 3-input AND in the reference and a 3-input OR in the implementation. This is the ECO problem. Also noticehighlighted in orange.l.Click on the Error Candidate Pruning button (or F8). The implemenation will be pruned.m.Click on the reference window and click again on the Error Candidate Pruning button (or F8). Now the reference is pruned.The resultant logic cones are easier to deal with. (No action needed in this lab to correct the design.)n.Close the schematic window. Click on the failing points tab. o.Select the first two failing points (bd_au_count_reg_0_ and bd_au_count_reg_1_) and click Diagnose Selected Points button. p.Note that there is still 1 error detected but now there are 6 error candidates.q.Right click on failing cell U4072.r.Select Show Logic Cones. Note that the Select Failing Compare Point window shows the 7 failing points but only 2 have been diagnosed.s.Select first failing compare point and click OK.t.Prune (F8) the reference and implementation schematic windows.Note that there are more possible failures candidates. This is due to selecting a subset of the failing points.。