时钟缓冲器基础知识---文本资料
时钟的知识点归纳总结
时钟的知识点归纳总结时钟是人类生活中不可或缺的工具之一，我们在日常生活中常常需要依靠时钟来获取准确的时间信息。
以下是关于时钟的一些知识点的归纳总结。
一、时钟的基本原理：1.基于机械原理的时钟：机械钟通过摆锤的摆动来驱动时针、分针和秒针的运动，从而显示时间。
2.基于电子原理的时钟：电子时钟通过晶体振荡器产生稳定的频率信号，然后通过锁相环电路将该信号转化为秒脉冲，从而驱动时、分、秒指针的运动。
二、时钟的种类：1.机械钟：机械钟是最早发展起来的一种钟表，其内部由一系列齿轮和摆锤组成，通过齿轮的传动来驱动时、分、秒指针运动。
2.石英钟：石英钟是一种利用石英晶体的压电效应来产生电压信号的钟表，具有精确的时间显示和较长的使用寿命。
3.原子钟：原子钟是以原子核或原子的共振频率作为时间基准的钟表，具有非常高的精确度和稳定性。
三、时钟的工作原理：1.机械钟的工作原理：机械钟内部装有一个重物，称为摆锤，通过摆锤的摆动来驱动齿轮系统，从而驱动时、分、秒指针的运动。
2.石英钟的工作原理：石英钟内部有一个石英晶体，应用于其上的电压会使晶体发生压电效应，进而产生稳定的频率信号，该信号经过计数和分频后用于驱动指针运动。
3.原子钟的工作原理：原子钟使用原子核或原子的共振频率作为时间基准，通常使用铯或铯原子，通过测量铯原子的共振频率来计算出准确的时间。
四、时钟的精准度：1.机械钟的精准度：机械钟的精准度一般较低，通常为每天准确率在数秒左右。
2.石英钟的精准度：石英钟的精准度要比机械钟高得多，通常为每天准确率在数十毫秒左右。
3.原子钟的精准度：原子钟的精准度非常高，通常为每天准确率在纳秒或皮秒级别。
五、时钟的应用：1.家用时钟：家用时钟主要用于在家庭生活中显示时间，通常由石英钟或机械钟组成。
2.办公室时钟：办公室时钟用于在办公环境中显示时间，通常会安装在墙上，以便员工方便查看时间。
3.公共场所时钟：公共场所时钟用于在公共场所如火车站、机场、购物中心等显示时间，以便公众准确掌握时间信息。
日常时钟相关知识点归纳
日常时钟相关知识点归纳日常时钟相关知识点主要包括时钟的基本构造、时钟的工作原理、不同类型的时钟、时钟的使用和维护等内容。
一、时钟的基本构造时钟由时钟机芯和表盘组成。
时钟机芯包括发条、主轴、齿轮、指针和摆轮等部件，用于传递时间信息。
表盘通常由数字或标志性刻度表示时间。
二、时钟的工作原理时钟机芯根据不同的设计原理，可以分为机械时钟、电子时钟和原子钟等类型。
机械时钟依靠发条的弹力和传动装置来驱动指针的运动；电子时钟通过电路和晶振来产生稳定的振荡信号，驱动数字或指针的显示；原子钟则利用原子的振荡频率作为计时基准，具有极高的精度和稳定度。
三、不同类型的时钟1.机械时钟：常见的挂钟、座钟等属于机械时钟，其工作原理是通过发条的弹力和齿轮传动来驱动指针的运动。
机械时钟需要定期上发条来提供动力。
2.电子时钟：电子时钟利用电路和晶振来产生稳定的振荡信号，驱动数字或指针的显示。
电子时钟通常使用电池或外部电源供电，具有较高的精度和稳定性。
3.原子钟：原子钟利用原子的振荡频率作为计时基准，具有极高的精度和稳定性。
原子钟通常用于科学研究和精密测量领域。
四、时钟的使用和维护1.校准时间：时钟的准确性和精度需要定期校准。
可以通过与标准时间源（如电波时钟、互联网时间服务器等）同步来校准时钟。
2.更换电池：电子时钟使用电池供电，需要定期更换电池以确保正常工作。
3.清洁维护：时钟表盘和机芯的清洁和维护可以延长时钟的使用寿命和保持良好的工作状态。
可以使用柔软的布擦拭，避免使用化学清洁剂。
4.防止冲击：时钟机芯内部的齿轮和零件非常精密，避免将时钟暴露在剧烈振动或冲击下，以免损坏时钟。
以上是日常时钟相关的基本知识点。
时钟作为一种时间工具，准确显示时间对我们的生活和工作非常重要，定期的维护和保养可以保证时钟的正常运行和使用寿命。
微光半导体 2012年 时钟缓冲器设计指南说明书
11.0 IntroductionThe goal of a clock buffer is to reproduce the input clock signal with minimal additive jitter. This requires both a well-designed buffer device and a carefully designed circuit board that minimizes the external sources of jitter on the output. One of these sources is the interfering tone produced by power supply switching. The tone can be a significant source of jitter at the buffer’s output. The jitter contributed by the tone can be mitigated by external filtering and on-chip regulators. This document will show how to measure Power Supply Noise Rejection (PSNR) and allows a designer to estimate the effect of jitter on the buffer output based on the expected power supply characteristics.2.0 Power Supply RejectionMeasurement SetupNoise sources on a power supply rail can be either random or periodic. Both can be detrimental to jitter performance of a buffer, but it is usually the periodic noise related to the power supply switching frequency (or indeed other digital noise that couples into the power supply) that dominates the jitter response.From an analysis perspective, it useful to characterize noise and the buffer’s response in terms of the frequency domain. A simple test circuit can be used to inject a tone at a particular frequency on the supply rail,and then measure the response on the buffer.December 2012ZLAN-403Power Supply Noise Rejection in Microsemi Clock BuffersApplication NoteFigure 1 shows the schematic for the PSNR measurement. The PCB power supply filter shown is the circuit recommended in the clock buffer datasheet. The DC source is a clean linear supply used to provide the 3.3V to the DUT. The function generator is used to inject a tone into the supply rail. The large inductor prevents AC current from the function generator propagating back into the DC source. The large capacitor prevents current from the DC supply flowing into the function generator. The PCB Power Supply Filter and the buffer are placed together on the same circuit board. The tone voltage at the input to the DUT is measured at point Vmon.Figure 1 - PSNR Measurement Setup3.0 PSNR Measurement ResultsUsing this test setup, a tone at a particular frequency is generated, and the effect on the output signal is captured by the Agilent E5052B Signal Source Analyzer. The signal source analyzer is configured with its "Spurious" option set to display spur power in dBc (decibels relative to the carrier). The magnitude of the tone or spur is shown on the phase noise plot. The PSNR is defined as the ratio of the output tone power to the carrier power. Figure 2 shows an example of 100 kHz power supply tone on a 125MHz input signal. The power of the tone at cursor 1 is shown in the first line of the text displayed in the plot: -77.4356 dBc. This is the PSNR of the buffer for this tone frequency.Figure 2 - Effect of Power Supply Tone on Buffer Output -- Phase NoiseTable 1 presents the additive jitter associated with a power supply tone at various frequencies for a 1:4 LVPECLclock buffer at room temperature. The carrier frequency in this case is 125 MHz, and the amplitude of the ripple isfixed at 25 mVpp at the DUT. The additive jitter is calculated from Equation 1. The buffer shows very goodrejection of power supply noise. Note that the additive jitter varies in a non-linear fashion with tone frequency.Where:PSNR is the magnitude of the tone power relative to the carrier in dBc.Fc is the frequency of the carrier in Hz.Jtone rms is the additive rms jitter due to the tone.It is difficult to fix the ripple amplitude at greater than 25 mVpp at higher frequencies, as the board power filter and decoupling capacitors tend to shunt the ripple to ground (which is their intended function). Practically, this limits the upper frequency to about 500 kHz.Measurements show that the additive jitter due to the tone at the output of the buffer is proportional to the amplitude of the tone at the input of the buffer. However, the constant of proportion is different for different tone frequencies.A plot of additive jitter vs input voltage for a 100 kHz tone is shown in Figure 3. From the graph, the amount of additive jitter can be determined based on the amplitude of the 100 kHz ripple.Table 1 - Power Supply Rejection at various frequency offsets with a carrier Frequency of 125 MHzFrequency Offset(kHz)Amplitude of Tone at Power Supply Input(mV pp)Power of Tone at Buffer Output relative to Carrier (PSNR in dBc)Additive Jitter due to Power Supply Tone(fs rms)10025-77.923120025-74.135530025-73.637440025-76.128150025-72.6423Jtone rms 10PSNR 20---------------2π×Fc×----------------------------=Equation 14.0 Additive Jitter and PSNRIt is useful to understand the impact of a particular power supply tone on the buffer’s output in terms of its contribution to additive jitter. Total jitter at the buffer’s output is given by Equation 2, with the assumption that the noise contributed by the tone is significantly above the random noise floor.Where:Jin rms is the random jitter on the input signal, with any contribution from spurs on the input removed,Jadd rms is the random additive noise that the buffer contributes,Jtone rms is the additive jitter contributed by the tone.Also, in the case where there is no power supply tone, the equation reduces to:Figure 3 - Additive Jitter vs Input Ripple Amplitude (mVpp)Jtotal rms Jin rms 2Jadd rms 2Jtone rms2++=Equation 2Jtone rms can be calculated from Equation 1 as stated earlier.As an example, consider a 125 MHz signal source with a random jitter of 200 fs rms between 12 kHz and 20 MHz.This signal is fed to the input of a clock distribution buffer which has an additive jitter of 110 fs rms at 125 MHz in the same band. In the absence of any power supply tones, the total random jitter output from the buffer will be given byEquation 3, , or 228 fs rms.Now assume a power supply tone is applied, and that its contribution can be seen on a phase noise plot of the buffer’s output as a spur with -85 dBc magnitude. This is the PSNR. The contribution from the tone in terms of jitter is given by Equation 1, and results in about 101 fs rms. Therefore, the total rms random jitter, found from Equation2, is , or 250 fs rms.Using the above equations, it is possible to plot a graph of the total jitter vs additive jitter contributed by a tone. For example consider a case in which the input jitter is 100 fs, the additive jitter from the buffer is 110 fs. Figure 4shows a plot of the total jitter vs increasing additive jitter due to power supply tone. The input jitter and additive jitter dominate the total jitter up to about 200 fs, then the rising jitter contributed by the tone begins to dominate.Jtotal rms Jin rms 2Jadd rms2+=Equation 320021102+200211021012++Figure 4 - Total Jitter vs Tone Contribution5.0 Designing for Power Supply RejectionThe PCB power supply filtering also contributes to overall Power Supply Rejection. Figure 5 shows the ideal transfer function of the filter components outlined in Figure 1. The 3dB frequency is given by , which is about 100kHz.The total Power Supply Noise Rejection is a combination of the attenuation due to the filter and the attenuation due to the buffer’s intrinsic PSNR.To appropriately manage power supply tones, the following jitter budgeting procedure can be used: •The total jitter allowed at the output must be defined.•The additive jitter of the buffer (J add ) and the expected jitter of the input signal (J in ) should be established.•The maximum jitter allowed to be contributed from a tone is then given from a derivative of Equation 2:•The maximum jitter is translated into a maximum tone voltage at the input of the buffer using a plot of additive jitter vs. input power supply ripple, as in Figure 3.•The maximum voltage at the buffer’s input is translated to the maximum ripple voltage on the power supply using Figure 5.For example, consider a system with a Jin of 300 fs rms and a Jadd of 110 fs rms (at 125 MHz). The maximum tolerable jitter at the output is 500 fs rms. From Equation 2, we have Jtone = 384 fs rms (maximum). Assume the concerning tone is generated by the power supply’s switching frequency, which is 100 kHz. From Figure 3, it can be seen that the maximum voltage on the input ripple must be less than ~40 mVpp. From Figure 3, at 100 kHz, the PCB filtering circuit attenuation factor is about 0.7. Therefore the ripple on the power supply must be less than 40mVpp/0.7 = 57 mVpp to achieve the 500 fs rms budget at the output. This is relatively easily achieved as most power supplies limit ripple below 30 mV pp.12πRC ()⁄Figure 5 - Transfer Function of Power Supply FilterJtone rms Jtotal rms 2Jin rms 2–Jadd rms 2–=6.0 ConclusionPower supply selection is an important consideration in low-jitter clock buffer design. To achieve the desired jitter targets, the board designer needs to consider the periodic voltage components on the supply rail, the PCB power supply filter design, and the clock buffer’s intrinsic power supply rejection. Microsemi clock buffers provide robust intrinsic power supply rejection. When they are used with the recommended power supply filter, significant attenuation of power supply ripple can be achieved. This allows board designers a wide degree of flexibility in power supply selection, while still maintaining the output jitter targets.Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. 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微晟半导体 ZL40200 低噪声高频精密 LVPECL 双输出时钟缓冲器数据表说明书
1FeaturesInputs/Outputs •Accepts differential or single-ended input •LVPECL, LVDS, CML, HCSL, LVCMOS •Two precision LVPECL outputs •Operating frequency up to 750 MHzPower •Options for 2.5 V or 3.3 V power supply •Core current consumption of 49 mA•On-chip Low Drop Out (LDO) Regulator for superior power supply rejectionPerformance •Ultra low additive jitter of 39 fs RMSApplications•General purpose clock distribution •Low jitter clock trees •Logic translation•Clock and data signal restoration•Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC•PCI Express generation 1/2/3 clock distribution •Wireless communications•High performance microprocessor clock distributionApril 2014Figure 1 - Functional Block DiagramZL40200Precision 1:2 LVPECL Fanout BufferData SheetOrdering InformationZL40200LDG1 16 Pin QFN TraysZL40200LDF116 Pin QFN Tape and ReelMatte TinPackage size: 3 x 3 mm-40o C to +85o CTable of ContentsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.3 Device Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.1 Sensitivity to power supply noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.2 Power supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.4.3 PCB layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217.0 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24List of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3 - LVPECL Input DC Coupled Thevenin Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4 - LVPECL Input DC Coupled Parallel Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5 - LVPECL Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 6 - LVDS Input DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7 - LVDS Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8 - CML Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9 - HCSL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 10 - CMOS Input DC Coupled Referenced to VDD/2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 11 - CMOS Input DC Coupled Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 12 - Simplified Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 13 - LVPECL Basic Output Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 14 - LVPECL Parallel Output Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15 - LVPECL Parallel Thevenin-Equivalent Output Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 16 - LVPECL AC Output Termination for Externally Terminated LVPECL Inputs . . . . . . . . . . . . . . . . . . . . 13 Figure 17 - LVPECL AC Output Termination for Internally Terminated LVPECL Inputs. . . . . . . . . . . . . . . . . . . . . 13 Figure 18 - LVPECL AC-Coupled Output Termination for CML Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 19 - Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 20 - Decoupling Connections for Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 21 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 22 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Change SummaryPage ItemChange1Applications Added PCI Express clock distribution.5Pin Description Added exposed pad to Pin Description.Removed 22 O hm series resistors from Figure 3 and 4.These resistor s are not required; however there is no impact to performance if the resistors are included.6, 7Figure 3 and Figure 413Figure 16Corrected LVPECL interface circuit.18Figure 21Below are the changes from the February 2013 ti the April 2014 issue:Page Item Change7Figure 4Changed text to indicate the circuit is not recommended for VDD_driver=2.5V.7Figure 5Changed pull-up and pull-down resistors from 2kOhm to 100 Ohm.Below are the changes from the November 2012 issue to the February 2013 issue:Clarification of V ID and V OD.The device is packaged in a 16 pin QFN1416642NCvddNCN Cc l k _pvddgndNCo u t 1_no u t 1_po u t 0_n81210o u t 0_pc l k _nN CNCgndFigure 2 - Pin Connections2.0 Pin DescriptionPin Description Pin # Name Description1, 4clk_p, clk_n,Differential Input (Analog Input). Differential input signals.12, 11, 10, 9out0_p, out0_n out1_p, out1_n Differential Output (Analog Output). Differential outputs.8, 13vdd Positive Supply Voltage. 2.5V DC or 3.3 V DC nominal.5, 16gnd Ground. 0 V.2, 3, 6, 7, 14, 15NCNo Connection. Leave unconnected.Exposed Pad Device GND .The ZL40200 is an LVPECL clock fanout buffer with two identical output clock drivers capable of operating at frequencies up to 750MHz.Inputs to the ZL40200 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40200 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is also available.The ZL40200 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.The device block diagram is shown in Figure 1; its operation is described in the following sections.3.1 Clock InputsThe device can accept LVPECL, LVDS, CML, HCSL and single-ended inputs.Figure 3 - LVPECL Input DC Coupled Thevenin EquivalentFigure 4 - LVPECL Input DC Coupled Parallel TerminationFigure 5 - LVPECL Input AC Coupled TerminationFigure 6 - LVDS Input DC CoupledFigure 7 - LVDS Input AC CoupledFigure 8 - CML Input AC CoupledFigure 9 - HCSL Input AC CoupledFigure 10 - CMOS Input DC Coupled Referenced to VDD/2Figure 11 - CMOS Input DC Coupled Referenced to GroundVDD_driver R1 (kΩ)R2 (kΩ)R3 (kΩ)RA (kΩ) C (pF) 1.5 1.25 3.075open10101.81 3.8open10102.50.33 4.2open10103.30.75open4.21010Table 1 - Component Values for Single Ended Input Reference to Ground * For frequencies below 100 MHz, increase C to avoid signal integrity issues.3.2 Clock OutputsLVPECL has a very low output impedance and a differential signal swing between 1V and 1.6 V. A simplified diagram for the output stage is shown in Figure 12.The LVPECL to LVDS output termination is not shown since there is a separate device that has the same input and LVDS outputs.out_pout_nFigure 12 - Simplified Output DriverThe methods to terminate the ZL40200 LVPECL drivers are shown in the following figures.Figure 15 - LVPECL Parallel Thevenin-Equivalent Output TerminationFigure 16 - LVPECL AC Output Termination for Externally Terminated LVPECL InputsFigure 17 - LVPECL AC Output Termination for Internally Terminated LVPECL InputsFigure 18 - LVPECL AC-Coupled Output Termination for CML Inputs3.3 Device Additive JitterThe ZL40200 clock fan out buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40200 is random and as such it is not correlated to the jitter of the input clock signal.The square of the resultant random RMS jitter at the output of the ZL40200 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources that are not shown in Figure 19.Figure 19 - Additive Jitter3.4 Power SupplyThis device operates with either a 2.5V supply or 3.3V supply.3.4.1 Sensitivity to power supply noisePower supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40200 is equipped with a low drop out (LDO) power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The LDO regulator on the ZL40200 allows this device to have superior performance even in the presence of external noise sources. The on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from power supply noise.The performance of these clock buffers in the presence of power supply noise is detailed in ZLAN-403, “Power Supply Rejection in Clock Buffers” which is available from Applications Engineering.3.4.2 Power supply filteringFor optimal jitter performance, the device should be isolated from the power planes connected to its power supply pins as shown in Figure 20.•10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating•0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating•Capacitors should be placed next to the connected device power pins• a 0.3 Ohm resistor is recommended for the filter shown in Figure 20Figure 20 - Decoupling Connections for Power Pins3.4.3 PCB layout considerationsThe power nets in Figure 20 can be implemented either as a plane island or routed power topology without changing the overall jitter performance of the device.Absolute Maximum Ratings*Parameter Sym.Min.Max.Units 1Supply voltage V DD_R-0.5 4.6V 2Voltage on any digital pin V PIN-0.5V DD V 3LVPECL output current I out30mA 4Soldering temperature T260 °C 5Storage temperature T ST-55125 °C 6Junction temperature T j125 °C 7Voltage on input pin V input V DD V 8Input capacitance each pin C p500fF 4.0 AC and DC Electrical Characteristics* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.* Voltages are with respect to ground (GND) unless otherwise statedRecommended Operating Conditions*Characteristics Sym.Min.Typ.Max.Units1Supply voltage 2.5 V mode V DD25 2.375 2.5 2.625V2Supply voltage 3.3 V mode V DD33 3.135 3.3 3.465V3Operating temperature T A-402585°C* Voltages are with respect to ground (GND) unless otherwise statedDC Electrical Characteristics - Current ConsumptionCharacteristics Sym.Min.Typ.Max.Units Notes 1Supply current LVPECL drivers -unloadedI dd_unload49mA Unloaded2Supply current LVPECL drivers - loaded (all outputs are active)I dd_load88mA Including powerto R L = 50DC Electrical Characteristics - Inputs and Outputs - for 3.3 V SupplyCharacteristics Sym.Min.Typ.Max.Units Notes 1Differential input common modevoltageV CM 1.1 2.0V2Differential input voltage difference V ID0.251V3LVPECL output high voltage V OH V DD-1.40V Measured at 10MHz4LVPECL output low voltage V OL V DD-1.62V Measured at 10MHz*The VOD parameter was measured from 125 MHz to 750 MHz.*The VOD parameter was measured from 125 MHz to 750 MHz.Figure 21 - Differential Voltage Parameter*Supply voltage and operating temperature are as per Recommended Operating Conditions5LVPECL output differential voltageV OD0.50.9VDC Electrical Characteristics - Inputs and Outputs - for 2.5 V SupplyCharacteristicsSym.Min.Typ.Max.Units Notes1Differential input common mode voltageV CM 1.1 1.6V 2Differential input voltage difference V ID 0.251V 3LVPECL output high voltage V OH V DD -1.40V 4LVPECL output low voltage V OL V DD -1.62V 5LVPECL output differential voltage*V OD0.40.9VAC Electrical Characteristics* - Inputs and Outputs (see Figure 22) - for 3.3 V supply.CharacteristicsSym.Min.Typ.Max.Units Notes1Maximum Operating Frequency 1/t p 750MHz 2input to output clock propagation delay t pd 012ns 3output to output skew t out2out 50100ps 4part to part output skewt part2part 80300ps 5Output clock Duty Cycle degradation t PWH / t PWL-2%0%2%Duty Cycle 6LVPECL Output Slew Rater sk0.75 1.2V/nsDC Electrical Characteristics - Inputs and Outputs - for 3.3 V SupplyCharacteristicsSym.Min.Typ.Max.Units NotesAC Electrical Characteristics* - Inputs and Outputs (see Figure 22) - for 2.5 V supply.Characteristics Sym.Min.Typ.Max.Units Notes 1Maximum Operating Frequency1/t p750MHz2input to output clock propagation delay t pd012ns3output to output skew t out2out50100ps4part to part output skew t part2part80300ps5Output clock Duty Cycle degradation t PWH/ t PWL-202Percent6LVPECL Output Slew Rate r sk0.75 1.2ps* Supply voltage and operating temperature are as per Recommended Operating ConditionsInputt Pt PWL t pdt PWHOutputFigure 22 - Input To Output TimingAdditive Jitter at 2.5 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 1122212.512 kHz - 20 MHz 803311.0412 kHz - 20 MHz 70442512 kHz - 20 MHz 65550012 kHz - 20 MHz 566622.0812 kHz - 20 MHz 43775012 kHz - 20 MHz39Additive Jitter at 3.3 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 1122212.512 kHz - 20 MHz 823311.0412 kHz - 20 MHz 72442512 kHz - 20 MHz 63550012 kHz - 20 MHz 526622.0812 kHz - 20 MHz 43775012 kHz - 20 MHz395.0 Performance Characterization*The values in this table were taken with an approximate slew rate of 0.8 V/ns.*The values in this table were taken with an approximate slew rate of 0.8 V/ns.* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for V DD = 3.3 V. The magnitude of the interfering tone is measured at the DUT.Additive Jitter from a Power Supply Tone*CarrierFrequency (MHz)ParameterTypicalUnitsNotes125MHz 25 mV at 100 kHz 159fs RMS 750MHz25 mV at 100 kHz82fs RMS6.0 Typical BehaviorTypical Phase Noise at 622.08 MHzTypical Waveform at 155.52 MHzInput Slew Rate versus Additive Jitter Propagation Delay versus TemperatureNote:This is for a single device. For more details see thecharacterization section.V ODversus FrequencyPower Supply Tone Magnitude versus PSRR (at 100 kHz) at 125 MHz Power Supply Tone Magnitude versus Additive Jitter (at 100 kHz) at 125 MHzPower Supply Tone Frequency (at 25 mV) versus PSRR at 125 MHz Power Supply Tone Frequency (at 25 mV) versus Additive Jitter at 125 MHz7.0 Package Thermal Characteristics*Proper thermal management must be practiced to ensure that T jmax is not exceeded.Thermal DataParameterSymbolTest ConditionValue UnitJunction to Ambient Thermal ResistanceΘJAStill Air 1 m/s 2 m/s 67.961.658.1oC/WJunction to Case Thermal Resistance ΘJC Still Air 44.1o C/W Junction to Board Thermal Resistance ΘJB Still Air23.2oC/WMaximum Junction Temperature*T jmax 125o C Maximum Ambient TemperatureT A85oC© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 3,400 employees globally. Learn more at .Microsemi Corporate Headquarters One One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail: ***************************Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. 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带有可选展频时钟 (SSC) 的时钟缓冲器 时钟倍乘器
OUTV SSC_SEL SSC_SEL INSSC_SEL 0SSC_SEL 1GNDVDD OE OUT FSCDCS503-Q1ZHCS946B –MARCH 2012–REVISED JUNE 2012带有可选展频时钟(SSC)的时钟缓冲器/时钟倍乘器查询样品:CDCS503-Q1特性•符合汽车应用要求•单一3.3V 器件电源•具有下列结果的AEC-Q100测试指南：•宽温度范围-40°C 至105°C–器件温度2级•节省空间的8引脚薄型小外形尺寸(TSSOP)封装–-40°C 至105°C 环境温度范围应用范围–器件人体模型(HBM)静电放电(ESD)分类等级•要求通过SSC 和/或者时钟倍乘来减少电磁干扰H2(EMI)的车载应用–器件充电器件模型(CDM)ESD 分类等级C3B •带有可选展频时钟(SSC)的易于使用的时钟生成器产品的一部分•带有可选输出频率和可选SSC 的时钟倍乘器•通过两个外部引脚可控制SSC–±0%，±0.5%，±1%，±2%中心展频•可使用一个外部控制引脚来选择x1或者x4的频率倍乘•通过控制引脚进行输出禁用图1.方框图Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.CDCS503-Q1ZHCS946B–MARCH2012–REVISED 说明CDCS503-Q1是一款带有可选频率倍乘的可展频、LVCMOS输入时钟缓冲器。
时钟弹簧资料
时钟弹簧
方向盘 Steering Wh
柱轴 Column Shaft
1-2.时钟弹簧旳 种类
开关类型
卡扣类型
滚珠型
把时钟弹簧跟组合开关（ Multi Function Body）
组装后， 安装在汽车旳种类
把时钟弹簧跟柱轴（Column Shaft）直接组装旳种类
北京当代 时钟弹簧培训目录
1.时钟弹簧产品使用用途
1)时钟弹簧简介 2)时钟弹簧关联 主要事项 3)时钟弹簧缺陷 判断顺序 4)时钟弹簧整备 资料
2. 售后件原因分析阐明 3. 我司生产时钟弹簧旳品质确保
1-1.时钟弹簧产品 使用用途
▶时钟弹簧是什么?
方向连接器总成 旳 简称 （Steering Rolling Connector Assembly）
2-5. 路试时 注意事项
-.车辆出厂前路试时,必须经过S型路线 ⇒因中立位置不对反转旳会断线，噪音发生旳原因.
-.经过S型路线上,将方向盘向右打死,检验SRC中立位置 ⇒假如中立位置不对,方向盘向右打死时SRC内部断线, 气囊灯常亮.
-.经过S型路线上,将方向盘向左打死,检验SRC中立位置. ⇒假如中立位置不对,方向盘向左打死时SRC内部断线, 气囊灯常亮.
- 车辆出厂前,必须要经过S型道路路试后,才干出厂.
2-6. 拆装车时 注意事项
=>进行拆装车前，先将电池正负极断开后进行SRC拆装，以预防造成气囊误爆。
拆装车前确保先将电池正负极断开后， 拔插气囊模块
2-6. 拆装车时 注意事项
=>假如电池正负极不进行断开直接SRC重装，除造成气囊误爆，还会在系统检测时显示 气囊阻值过大。
-.时钟弹簧拆卸安装工作时, 时钟弹簧中立调整后, 安装在车辆上. (往右侧旋转至不动完毕后，再往左侧旋转 标签显示圈回转后, 定中立) ⇒因中立针脱落反转旳会造成断线、噪音发生旳原因.
时钟基础知识
时钟基础知识时钟是我们日常生活中不可或缺的一部分，它在我们的工作、学习和生活中起着至关重要的作用。
本文将介绍一些关于时钟的基础知识，包括时钟的种类、工作原理以及常见故障的排除方法。
一、时钟的种类1. 机械时钟机械时钟是一种使用机械装置来测量时间的时钟。
它采用机械齿轮以及摆线来驱动指针的运动。
机械时钟通常需要通过手动上弦或者摇摆器来维持正常运行。
2. 石英时钟石英时钟是一种通过石英晶体振荡来测量时间的时钟。
石英晶体具有稳定的振荡频率，因此石英时钟比机械时钟更加准确。
石英时钟通常由电池供电。
3. 原子钟原子钟是一种通过原子或分子的高稳定振荡频率来测量时间的时钟。
原子钟的准确度极高，常用于科学实验和导航系统中。
原子钟通常使用铯或铷等元素进行振荡。
二、时钟的工作原理无论是机械时钟、石英时钟还是原子钟，它们的工作原理都是基于稳定的振荡频率来测量时间。
以下是一个简单的时钟工作原理的示意图：[示意图]时钟通过一个稳定的振荡器来产生固定的脉冲信号，这些脉冲信号被转换成可见的时间单位，比如小时、分钟和秒。
机械时钟通过齿轮传动和摆线来驱动指针的运动；石英时钟通过石英晶体的振动来产生电信号，并通过电子电路将其转化为时间单位；原子钟则通过原子或分子的共振频率来产生极为稳定的时间信号。
三、常见故障排除方法1. 时钟走慢或快如果时钟走得慢或快，首先需要检查电池是否正常工作。
若电池耗尽或电池接触不良，可以更换电池或调整电池接触。
另外，石英时钟的振荡器可能会受到温度变化的影响，可以尝试将时钟放置在稳定的温度环境中。
2. 指针不动或越位如果时钟的指针停止运动或者越位，可能是由于机械部件的故障导致。
这时可以尝试打开时钟的后盖，检查机械部件是否正常，如有需要可以进行清洁和维修。
如果是电子时钟，可能是电子电路出现了故障，可以尝试更换电子元件或者直接送修。
3. 时钟噪音大时钟发出噪音通常是由于机械部件磨损或石英晶体振动不均匀所导致。
对于机械时钟，可以尝试加入适量的润滑剂来减少噪音。
主板时钟电路工作原理
主板时钟电路工作原理一、引言主板时钟电路是计算机系统中的重要组成部分，它负责提供系统时钟信号，为计算机的各个部件提供统一的时序参考。
本文将详细介绍主板时钟电路的工作原理及其相关知识。
二、主板时钟电路的作用主板时钟电路的主要作用是为计算机内部的各个部件提供统一的时序参考信号。
它通过产生稳定的时钟信号，确保计算机内部各个部件的协调工作。
时钟信号的频率和稳定性对计算机系统的性能和稳定性有着重要影响。
三、主板时钟电路的组成主板时钟电路一般由以下几个部分组成：1. 振荡器：振荡器是主板时钟电路的核心部件，它负责产生稳定的时钟信号。
常见的振荡器有晶体振荡器和压控振荡器等。
晶体振荡器具有高稳定性和精确的频率特性，被广泛应用于主板时钟电路。
2. 预分频器：预分频器用于将振荡器输出的高频时钟信号分频为较低的频率，以适应不同部件的工作频率要求。
预分频器一般采用可编程分频器，可以根据需要进行设置。
3. 时钟分配器：时钟分配器将预分频器输出的时钟信号分配给不同的部件，以满足各个部件的时钟需求。
时钟分配器一般采用时钟树结构，可以实现多路时钟选择和分频功能。
4. 时钟缓冲器：时钟缓冲器用于放大和驱动时钟信号，确保时钟信号的质量和稳定性。
时钟缓冲器一般采用高速缓冲器，具有较低的时钟延迟和较高的驱动能力。
四、主板时钟电路的工作原理主板时钟电路的工作原理如下：1. 振荡器产生稳定的时钟信号，通常为晶体振荡器，其频率由晶体的特性决定。
2. 振荡器输出的时钟信号经过预分频器进行分频，得到适合不同部件工作频率要求的时钟信号。
3. 预分频器输出的时钟信号经过时钟分配器进行选择和分配，分配给不同的部件。
4. 时钟信号经过时钟缓冲器进行放大和驱动，确保时钟信号的质量和稳定性。
5. 各个部件根据接收到的时钟信号进行相应的操作和计算。
五、主板时钟电路的注意事项在设计和使用主板时钟电路时，需要注意以下几个方面：1. 振荡器的选取：选择适合的振荡器对主板时钟电路的性能和稳定性至关重要。
高速设计知识点
高速设计知识点高速设计是现代电子技术领域中的一个重要分支，它涉及到各种高速电路和系统的设计和优化。
在高速设计过程中，需要考虑信号传输速度、信号完整性、时钟分配、布线规则等多个方面的知识点。
本文将介绍几个与高速设计相关的关键知识点。
一、时钟分配与优化时钟在高速电路中起到了非常重要的作用，它为各个模块提供了同步的时序信号。
时钟分配和优化是高速设计中的一个关键环节，它直接影响到高速电路的性能和稳定性。
1. 时钟树设计：时钟树是指将一个时钟信号从时钟源传输到目标模块的网络结构。
在设计时钟树网络时，需要考虑各个时钟路径的延迟、抖动和功耗等因素，并且要避免时钟偏斜和冗余。
2. 时钟缓冲：时钟缓冲是指将时钟信号放大与同步的过程，它通常使用锁相环（PLL）或延迟锁定环（DLL）来实现。
时钟缓冲的选择和配置要根据具体的设计需求来确定，包括频率要求、时钟分配方式和功耗等因素。
二、电磁兼容性（EMC）电磁兼容性是指电子设备在电磁环境下正常工作并与其他设备共存的能力。
在高速设计中，电磁兼容性问题尤为重要，因为高速信号的传输会产生较强的电磁辐射和抗干扰需求。
1. 地线设计：地线是高速电路中的重要信号回路，它不仅需要提供良好的信号回路路径，还需要提供较低的电阻和电感，以减少信号的反射和互耦。
2. 屏蔽与防护：高速电路往往使用屏蔽罩或屏蔽层来减少电磁泄漏和抗干扰。
在设计中，需要合理规划屏蔽的位置、形状和材料，以提高系统的电磁兼容性。
三、信号完整性在高速电路中，信号的完整性对系统的性能和可靠性具有重要影响。
以下是几个与信号完整性相关的知识点。
1. 端口匹配：端口匹配是指将信号源和接收器的输入/输出阻抗匹配。
通过端口匹配，可以减少信号的反射和功率损耗，提高信号传输质量。
2. 布线规则：布线规则是指在高速电路布线中需要遵循的一系列设计规范。
这些规范包括最小距离要求、分区规划、信号层规划等，旨在减少信号串扰和电磁干扰。
四、功耗优化功耗优化是高速设计中的一个重要方面，尤其是在移动设备和便携式电子产品中更加突出。
Skyworks Solutions PCIe 时钟缓冲器文档说明书
Si53156-A13APCI-E XPRESS G EN 1, G EN 2, G EN 3, AND G EN 4 F ANOUT B UFFERFeaturesApplicationsDescriptionThe Si53156-A13A is a spread spectrum tolerant PCIe clock buffer that can source six PCIe clocks simultaneously. The device has six hardware output enable control inputs for enabling the respective differential outputs on the fly. The device also features output enable control through I 2C communication. I 2C pro-grammability is also available to dynamically control skew, edge rate and ampli-tude on the true, compliment, or both differential signals on the clock outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is quick and easy with the Skyworks Solutions PCIe Clock Jitter Tool. Download it for free at https:///en/application-pages/pci-express-learning-center .Functional Block Diagram⏹PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant ⏹Supports Serial ATA (SATA) at 100MHz ⏹100–210MHz operation ⏹Low power, push pull, differential output buffers ⏹Internal termination for maximum integration⏹Dedicated output enable pin for eachoutput⏹Six PCI-Express buffered clock outputs⏹Clock input spread tolerable ⏹Supports LVDS outputs ⏹I 2C support with readback capabilities⏹Extended temperature: –40 to 85o C⏹3.3V power supply ⏹32-pin QFN package⏹Network attached storage ⏹Multi-function printers⏹Wireless access point ⏹RoutersDIFFIN DIFFINSCLK SDATA OE [5:0]DIFF0DIFF1DIFF2DIFF3DIFF4DIFF5Patents pendingOrdering Information:See page 17.Si53156-A13A2SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Si53156-A13A T ABLE OF C ONTENTSSection Page1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105. Pin Descriptions: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•3Si53156-A13A4SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•1. Electrical SpecificationsTable 1. DC Electrical SpecificationsParameterSymbol Test ConditionMin Typ Max Unit 3.3V Operating Voltage VDD core 3.3 ± 5% 3.135— 3.465V 3.3V Input High Voltage V IH Control input pins 2.0—V DD + 0.3V 3.3V Input Low Voltage V IL Control input pins V SS – 0.3—0.8V Input High Voltage V IHI2C SDATA, SCLK 2.2——V Input Low VoltageV ILI2C SDATA, SCLK —— 1.0V Input High Leakage Current I IH Except internal pull-down resistors, 0 < V IN < V DD ——5μA Input Low Leakage Current I IL Except internal pull-up resistors, 0 < V IN < V DD–5——μA 3.3V Output High Voltage (Single-Ended Outputs)V OH I OH = –1 mA 2.4——V 3.3V Output Low Voltage (Single-Ended Outputs)V OL I OL = 1 mA——0.4V High-impedance Output CurrentI OZ –10—10μA Input Pin Capacitance C IN 1.5—5pF Output Pin Capacitance C OUT ——6pF Pin Inductance L IN ——7nH Power Down Current I DD _PD ——1mA Dynamic Supply Current in Fanout ModeI DD_3.3VDifferential clocks with 5” traces and 2pF load, fre-quency at 100MHz——45mASi53156-A13ASkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 5Table 2. AC Electrical SpecificationsParameterSymbolConditionMinTypMaxUnitDIFFIN at 0.7V Input Frequency Rangef in 100—210MHzRising and Falling Slew Rates for Each Clock Output Signal in a Given Differential Pair T R /T FSingle ended measurement: V OL = 0.175 to V OH = 0.525V(Averaged)0.6—4 V/nsDifferential Input High Voltage V IH 150——mV Differential Input Low Voltage V IL ——–150mV Crossing Point Voltage at 0.7V SwingV OX Single-ended measurement 250—550mV Vcross Variation over all edges V OX Single-ended measurement——140mV Differential Ringback Voltage V RB –100—100mV Time before ringback allowed T STABLE 500——ps Absolute maximum input voltage V MAX —— 1.15V Absolute minimum input voltage V MIN –0.3——V Duty Cycle for Each Clock Output Signal in a Given Differential Pair T DCMeasured at crossing point V OX 45—55%Rise/Fall Matching T RFMDetermined as a fraction of 2x (T R – T F )/(T R + T F )——20%DIFF at 0.7V Duty Cycle T DC Measured at 0V differential 45—55%Clock Skew T SKEW Measured at 0V differential——50ps Additive Peak JitterPk-Pk 0—10ps Additive PCIe Gen 2 Phase JitterRMS GEN210kHz < F < 1.5 MHz 0—0.5ps 1.5MHz< F < Nyquist Rate0—0.5ps Additive PCIe Gen 3 Phase Jitter RMS GEN3Includes PLL BW 2–4MHz(CDR = 10MHz)0—0.10ps Additive PCIe Gen 4 Phase Jitter RMS GEN4PCIe Gen 4——0.10ps Additive Cycle to Cycle Jitter T CCJ Measured at 0V differential ——50ps Long-term Accuracy L ACC Measured at 0V differential ——100ppm Rising/Falling Slew rate T R / T F Measured differentially from±150mV 2.5—8V/ns Crossing Point Voltage at 0.7V SwingV OX300—550mVNotes:1.Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.2. Download the Skyworks Solutions PCIe Clock Jitter Tool at https:///en/application-pages/pci-express-learning-center .Si53156-A13A6SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Enable/Disable and Setup Clock Stabilization from Power-UpT STABLEMeasured from the point when both V DD and clock input arevalid–—5msStopclock Set-up TimeT SS10.0——nsTable 3. Absolute Maximum ConditionsParameterSymbol Condition Min Typ Max Unit Main Supply Voltage V DD_3.3VFunctional —— 4.6V Input Voltage V IN Relative to V SS –0.5— 4.6V DC Temperature, StorageT S Non-functional –65—150°C Industrial Temperature, Operating AmbientT A Functional –40—85°C Commercial Temperature, Operating AmbientT A Functional 0—85°C Temperature, Junction T J Functional ——150°C Dissipation, Junction to Case ØJC JEDEC (JESD 51)——17°C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51)——35°C/W ESD Protection (Human Body Model)ESD HBM JEDEC (JESD 22 - A114)2000——VFlammability RatingUL-94UL (Class)V–0Note:Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supplysequencing is not required.Table 2. AC Electrical Specifications (Continued)ParameterSymbolConditionMinTypMaxUnitNotes:1.Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.2. Download the Skyworks Solutions PCIe Clock Jitter Tool at https:///en/application-pages/pci-express-learning-center .Si53156-A13A 2. Functional Description2.1. OE Pin DefinitionThe OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE pin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disable the output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins are required to be driven at all times even though they have an internal 100k resistor.2.2. OE AssertionThe OE signals are active high inputs used for synchronous stopping and starting the DIFF output clocks respectively while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high causes stopped respective DIFF outputs to resume normal operation. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output clock cycles.2.3. OE DeassertionWhen the OE pin is deasserted by making it logic low, the corresponding DIFF output is stopped, and the final output state is driven low.SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•7Si53156-A13A8SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•3. Test and Measurement SetupThis diagram shows the test load configuration for differential clock signals.Figure 1.0.7V Differential Load ConfigurationFigure 2.Differential Measurement for Differential Output Signals(for AC Parameters Measurement)Si53156-A13AFigure3.Single-Ended Measurement for Differential Output Signals(for AC Parameters Measurement)SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•9Si53156-A13A4. Control Registers4.1. I2C InterfaceTo enhance the flexibility and function of the clock buffer, an I2C interface is provided. Through the I2C Interface, various device functions are available, such as individual clock output enable. The registers associated with the I2C Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. Power management functions can only be programed in program mode and not in normal operation modes.4.2. Data ProtocolThe I2C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes.The block write and block read protocol is outlined in Table4 on page10 while Table5 on page11 outlines byte write and byte read protocol. The slave receiver address is 11010110 (D6h).Table 4. Block Read and Block Write ProtocolBlock Write Protocol Block Read Protocol Bit Description Bit Description1Start1Start8:2Slave address—7 bits8:2Slave address—7 bits9Write 9Write 10Acknowledge from slave10Acknowledge from slave18:11Command Code—8 bits18:11Command Code–8 bits19Acknowledge from slave19Acknowledge from slave27:20Byte Count—8 bits20Repeat start28Acknowledge from slave27:21Slave address—7 bits36:29Data byte 1–8 bits28Read = 137Acknowledge from slave29Acknowledge from slave45:38Data byte 2–8 bits37:30Byte Count from slave—8 bits46Acknowledge from slave38Acknowledge....Data Byte/Slave Acknowledges46:39Data byte 1 from slave—8 bits....Data Byte N–8 bits47Acknowledge....Acknowledge from slave55:48Data byte 2 from slave—8 bits....Stop56Acknowledge....Data bytes from slave/Acknowledge....Data Byte N from slave—8 bits....NOT Acknowledge....Stop10SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Table 5. Byte Read and Byte Write ProtocolByte Write Protocol Byte Read ProtocolBit Description Bit Description1Start1Start8:2Slave address–7 bits8:2Slave address–7 bits9Write 9Write 10Acknowledge from slave10Acknowledge from slave18:11Command Code–8 bits 18:11Command Code–8 bits19Acknowledge from slave19Acknowledge from slave27:20Data byte–8 bits20Repeated start28Acknowledge from slave27:21Slave address–7 bits29Stop28Read29Acknowledge from slave37:30Data from slave–8 bits38NOT Acknowledge39StopControl Register 0.Byte 0Bit D7D6D5D4D3D2D1D0 NameType R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 00000000Bit Name Function7:0ReservedControl Register 1.Byte 1Bit D7D6D5D4D3D2D1D0 Name DIFF0_OE DIFF1_OE DIFF2_OE Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 00010101Bit Name Function7:5Reserved4DIFF0_OE Output Enable for DIFF0.0: Output disabled.1: Output Enabled.3Reserved2DIFF1_OE Output Enable for DIFF1.0: Output disabled.1: Output enabled.1Reserved0DIFF2_OE Output Enable for DIFF2.0: Output disabled.1: Output enabled.Control Register 2.Byte 2Bit D7D6D5D4D3D2D1D0 Name DIFF3_OE DIFF4_OE DIFF5_OEType R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 11100000Bit Name Function7DIFF3_OE Output Enable for DIFF3.0: Output disabled.1: Output enabled.6DIFF4_OE Output Enable for DIFF4.0: Output disabled.1: Output enabled.5DIFF5_OE Output Enable for DIFF5.0: Output disabled.1: Output enabled.4:0ReservedControl Register 3.Byte 3Bit D7D6D5D4D3D2D1D0 Name Rev Code[3:0]Vendor ID[3:0]Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 00001000Bit Name Function7:4Rev Code[3:0]Program Revision Code.3:0Vendor ID[3:0]Vendor Identification Code.Reset settings = 00000110Reset settings = 11011000Control Register 4.Byte 4Bit D7D6D5D4D3D2D1D0Name BC[7:0]TypeR/WR/WR/WR/WR/WR/WR/WR/WBit Name Function7:0BC[7:0]Byte Count Register.Control Register 5.Byte 5BitD7D6D5D4D3D2D1D0Name DIFF_Amp_Sel DIFF_Amp_Cntl[2]DIFF_Amp_Cntl[1]DIFF_Amp_Cntl[0]TypeR/WR/WR/WR/WR/WR/WR/WR/WBit Name Function7DIFF_Amp_SelAmplitude Control for DIFF Differential Outputs.0: Differential outputs with Default amplitude.1: Differential outputs amplitude is set by Byte 5[6:4].6DIFF_Amp_Cntl[2]DIFF Differential Outputs Amplitude Adjustment.000: 300mV 001: 400mV 010: 500mV 011: 600mV 100: 700mV 101: 800mV 110: 900mV 111: 1000mV5DIFF_Amp_Cntl[1]4DIFF_Amp_Cntl[0]3:0Reserved5. Pin Descriptions: 32-Pin QFNFigure 4.32-Pin QFNTable 6. Si53156-A13A 32-Pin QFN DescriptionsPin #Name TypeDescription1VDD PWR 3.3V power supply.2OE2I,PUActive high input pin enables DIFF2 (internal 100k Ω pull-up).Refer to Table 1 on page 4 for OE specifications.3VDD PWR 3.3V Power Supply 4OE3I,PU Active high input pin enables DIFF3 (internal 100k Ω pull-up).Refer to Table 1 on page 4 for OE specifications.5OE4I,PU Active high input pin enables DIFF4 (internal 100k Ω pull-up).Refer to Table 1 on page 4 for OE specifications.6OE5I,PU Active high input pin enables DIFF5 (internal 100k Ω pull-up).Refer to Table 1 on page 4 for OE specifications.7NC NCNo connect.8VDD PWR 3.3V power supply.9DIFF0O, DIF 0.7V, 100MHz differential clock.10DIFF0O, DIF 0.7V, 100MHz differential clock.11DIFF1O, DIF 0.7V, 100MHz differential clock.VDD OE2*VDD OE3*OE5*D I F F 0D I F F 0D I F F 1D I F F 1V D DD I F F 2G D _P D B *VDDD I F F 2V D D*Note: Internal 100 kohm pull-up.12DIFF1O, DIF 0.7V, 100MHz differential clock.13VDD PWR 3.3V power supply.14DIFF2O, DIF 0.7V, 100MHz differential clock.15DIFF2O, DIF 0.7V, 100MHz differential clock.16VDD PWR 3.3V power supply.17DIFF3O, DIF 0.7V, 100MHz differential clock.18DIFF3O, DIF 0.7V, 100MHz differential clock.19DIFF4O, DIF 0.7V, 100MHz differential clock.20DIFF4O, DIF 0.7V, 100MHz differential clock.21VDD PWR 3.3V power supply.22DIFF5O, DIF 0.7V, 100MHz differential clock.23DIFF5O, DIF 0.7V, 100MHz differential clock.24VDD PWR 3.3V power supply.25SCLK I SMBus compatible SCLOCK.26SDATA I/O SMBus compatible SDATA.27CKPWRGD_PDBI, PU3.3V LVTTL input. This pin is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. A real-time active low input for asserting power down (PDB) and disabling all outputs (internal 100k Ω pull-up).28VDD PWR 3.3V power supply.29DIFFIN I 0.7V Differential True Input, typically 100MHz. Input frequency range 100 to 210MHz.30DIFFIN O 0.7V Differential Complement Input, typically 100MHz. Input frequency range 100 to 210MHz.31OE0I,PU Active high input pin enables DIFF0 (internal 100k Ω pull-up).Refer to Table 1 on page 4 for OE specifications.32OE1I,PU Active high input pin enables DIFF1 (internal 100k Ω pull-up).Refer to Table 1 on page 4 for OE specifications.33GNDGNDGround for bottom pad of the IC.Table 6. Si53156-A13A 32-Pin QFN DescriptionsPin #Name TypeDescription6. Ordering GuidePart Number Package Type Temperature Lead-freeSi53156-A13AGM32-pin QFN Extended, –40 to 85︒C Si53156-A13AGMR32-pin QFN—Tape and Reel Extended, –40 to 85︒C7. Package OutlineFigure5 illustrates the package details for the Si53156-A13A. Table7 lists the values for the dimensions shown in the illustration.Figure5.32-Pin Quad Flat No Lead (QFN) PackageTable 7. Package Diagram DimensionsDimension Min Nom MaxA0.700.750.80A10.000.020.05b0.180.250.30D 5.00 BSCD2 3.15 3.20 3.25e0.50 BSCE 5.00 BSCE2 3.15 3.20 3.25L0.300.400.50aaa0.10bbb0.10ccc0.08ddd0.10Notes:1.All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small BodyComponents.4. Coplanarity less than 0.08mm.5. Terminal #1 identifier and terminal numbering convention conform to JESD 95-1 SPP-012.8. Land PatternFigure6 illustrates the recommended land pattern details for the Si53156-A13A in a 32-pin QFN package. Table8 lists the values for the dimensions shown in the illustration.nd PatternTable 8. PCB Land Pattern DimensionsDimension mmS1 4.01S 4.01L1 3.20W1 3.20e0.50W0.26L0.86Notes:General1.All dimensions shown are in millimeters (mm).2. This Land Pattern Design is based on the IPC-7351 guidelines.Solder Mask Design1.All metal pads are to be non-solder mask defined (NSMD). Clearance between thesolder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal wallsshould be used to assure good solder paste release.2. The stencil thickness should be 0.125mm (5 mils).3. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.4. A 3x3 array of 0.85mm square openings on a 1.00mm pitch can be used for thecenter ground pad..Card Assembly1. A No-Clean, Type-3 solder paste is recommended.2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020specification for Small Body Components.Si53156-A13A21SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•D OCUMENT R EVISION H ISTORYRevision 1.0Initial “A13A” Revision derived from Si53156-A01Adata sheet.Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. 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时钟缓冲器基础EN
Clock Buffer BasicsClocks are the basic building blocks for all electronics today. For every data transition in a synchronous digital system, there is a clock that controls a register. Most systems use Crystals, Frequency Timing Generators (FTGs), or inexpensive ceramic resonators to generate precision clocks for their synchronous systems. Additionally, clock buffers are used to create multiple copies, multiply and divide clock frequencies, and even move clock edges forwards or backward in time. Many clock-buffering solutions have been created over the past few years to address the many challenges required by today’s high-speed logic systems. Some of these challenges include: High operating and output frequencies, propagation delays from input to output, output to output skew between pins, cycle-tocycle and long-term jitter, spread spectrum, output drive strength, I/O voltage standards, and redundancy. Because clocks are the fastest signals in a system and are usually under the heaviest loads, special consideration must be given when creating clocking trees. In this chapter, we outline the basic functions of non-PLL and PLL-based buffers and show how these devices can be used to address the high-speed logic design challenges.In today’s typical synchronous de signs, multiple clock signals are often needed to drive a variety of components. To create the required number of copies, a clock tree is constructed. The tree begins with a clock source such as an oscillator or an external signal and drives one or more buffers. The number of buffers is typically dependent on the number and placement of the target devices.In years past, generic logic components were used as clock buffers. These were adequate at the time, but they did little to maintain the signal integrity of the clock. In fact, they actually were a detriment to the circuit. As clock trees increased in speed and timing margins reduced, propagation delay and output skew became increasingly important. In the next several sections, we discuss the older devices and why they are inadequate to meet the needs of today’s designs. The definitions of the common terms associated with modern buffers follow. Finally, we address the attributes of the modern clock buffer with and without a PLL. The FTG that is often used as a clock source is a special type of PLL clock buffer.◆Early BuffersA clock buffer is a device in which the output waveform follows the input waveform. The input signal propagates through the device and is re-driven by the output buffers. Hence, such devices have a propagation delay associated with them. Inaddition, due to differences between the propagation delay through the device on each input-output path, skew will exist between the outputs. An example of a non-PLL based clock buffer is the 74F244 that is available from several manufacturers. These devices have been available for many years and were suitable for designs where frequencies were below 20 MHz. Designers would bring in a clock and fan it out to multiple synchronous devices on a circuit card. With these slow frequencies and associated rise times, designers had suitable margins with which to meet setup and hold times for their synchronous interfaces. However, these buffers are not optimal for today’s high-speed clocking requirements. The 74F244 suffers from a long propagation delay (3 to 5 ns) and long output-to-output skew delays. Non-PLL based clock buffers have improved in recent years and use more advanced I/O design techniques to improve the output-to-output skew. As the clock period gets shorter, the uncertainty or skew in the clock distribution system becomes more of a factor. Since clocks are used to drive the processors and to synchronize the transfer of data between system components, the clock distribution system is an essential part of the system design. A clock distribution system design that does not take skew into consideration may result in a system with degraded performance and reliability.◆Clock SkewSkew is the variation in the arrival time of two signals specified to occur at the same time. Skew is composed of the output skew of the driving device and variation in the board delays caused by the layout variation of the board traces. Since the clock signal drives many components of the system, and since all of these components should receive their clock signal at precisely the same time in order to be synchronized, any variation in the arrival of the clock signal at its destination will directly impact system performance. Skew directly affects system margins by altering the arrival of a clock edge. Because elements in a synchronized system require clock signals to arrive at the same time, clock skew reduces the cycle time within which information can be passed from one device to the next.As system speeds increase, clock skew becomes an increasingly large portion of the total cycle time. When cycle times were 50 ns, clock skew was rarely a design priority. Even if skew was 20% of the cycle time, it presented no problem. As cycle times dropped to 15ns and less, clock skew requires an ever-increasing amount of design resource. Now typically, these high-speed systems can have only 10% of their timing budget dedicated to clock skew, so obviously, it must be reduced.There are two types of clock skew that affect system performance. The clock driver causes intrinsic skew and the printed circuit board (PCB) layout and design is referred to as extrinsic skew. Extrinsic skew and layout procedures for clock trees will be discussed later in this book. The variation of time due to skew is defined by the following equation:tSKEW_INTRINSIC = Device Induced SkewtSKEW_EXTRINSIC = PCB + Layout + Operating Environment Induced Skew tSKEW = tSKEW_INTRINSIC + tSKEW_EXTRINSICIntrinsic clock skew is the amount of skew caused by the clock driver or buffer by itself. Board layout or any other design issues, except for the specification stated on the clock driver data sheet do not cause intrinsic skew.◆Output SkewOutput skew (tSK)is also referred to as pin-to-pin skew. Output skew is the difference between delays of any two outputs on the same device at identical transitions. Joint Electronic Device Engineering Council (JEDEC) defines output skew as the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Figures 2.2 and 2.3 show a clock buffer with common input Cin driving outputs Co1_1 through Co1_n. The absolute maximum difference between the rising edges of the outputs will be specified as output skew. Typical output skew in today’s high performance clock buffers is around 200 picoseconds (ps).◆Part-to-Part SkewPart-to-part skew (tDSK)is also known as package skew and device-to-device skew. Part-topart skew is similar to output skew except that it applies to two or more identical devices.Part-to-part skew is defined as the magnitude of the difference in propagation delays between any specified outputs of two separate devices operating at identical conditions. The devices must have the same input signal, supply voltage, ambient temperature, package, load, environment, etc. Figure 2.4 illustrates tDSK from the preceding example.Typical part-to-part skew for today’s high performance buffers is around 500 ps. Propagation DelayPropagation delay (tPD) is the time between specified reference points on theinput and output voltage waveforms with the output changing from one defined level (low) to the other (low). Propagation delay is illustrated in Figure 2.3. Non-PLL based devices in today’s high performance devices range from 3 to 7 ns. PLL-based buffers are able to zero out this propagation delay with the aid of Phase Detectors, Loop Filters and Voltage Controlled Oscillators (VCOs).◆Uneven LoadingWhen using a high-speed clock buffer or PLL, care must be taken to equally load the outputs of the device to ensure that tight skew tolerances are maintained. Inherent in each output of the clock driver is an output impedance that is mostly resistive in nature (along with some inductance and capacitance). When each of these resistive outputs is equally loaded, the tight skew specification of the clock driver is preserved. If the loads become unbalanced, the (RC) time constants of the various outputs would be different, and the skew would be directly proportional to the variation in the loading.◆Input Threshold VariationAfter the low skew clock signals have been distributed, the clock receivers must accept the clock input with minimal variations. If the input threshold levels of the receivers are not uniform, the clock receivers will respond to the clock signals at different times creating clock skew. If one load device has a threshold of 1.2 volts and another load device has a threshold of 1.7 volts and the rising edge rate is 1V/ns, there will be 500 ps of skew caused by the point at which the load device switches based on the input signal. Most manufacturers center the input threshold level of their devices near 1.5 volts nominal for (TTL) input devices. This input threshold will vary slightly from manufacturer to manufacturer especially as conditions (such as voltage and temperature) change. The TTL specification for the input threshold level is guaranteed to be a logic high when the input voltage is above 2.0 volts and a logic low when the input voltage level is below 0.8 volts.This leaves a 1.2-volt window over voltage and temperature. Components with Complementary Metal Oxide Semiconductor (CMOS) rail swing inputs have a typical input threshold of VCC/2 or about 2.5 volts, which is much higher than the TTL level. If the threshold levels are not uniform, clock skew will develop between components because of these variations. There are many I/O standards which have emerged and all must be taken into consideration when providing clocks to different subsystems. Table 2.1 listed below which lists the more prevalent standards along with the inputthreshold voltages.◆Non-PLL Based Clock DriversThere are two main types of modern clock driver architectures: a buffer-type device (non-PLL) and a feedback-type device (PLL).In a buffer-style (non-PLL) clock driver, the input wave propagates through the device and is “re-d riven” by the output buffers. This output signal directly follows the input signal and has a propagation delay (tPD) that ranges from 5 ns to over 15 ns. These devices differ from the buffers in the past such as the 74F244 in that they are designed specifically for clock signals. On a 74F244, there are eight inputs and eight outputs. To create a one to eight buffer, all eight inputs are tied together. This causes excess loading at the inputs on the driving signal. A one to eight clock buffer has only one input and hence only one load. The output rise and fall times are also equally matched and therefore do not contribute to duty cycle error. With their improved I/O structure, the pin-to-pin skew is kept to a minimum.The output skew of this device, if it is not listed on the data sheet, can be calculated by subtracting the minimum propagation delay from the maximum propagation delay.The 10 ns tPD clock driver delay shown in Figure 2.5 does not take into account the affects of the board layout and design. These types of devices are excellent for buffering source signals such as oscillators where the output phase does not need to match the input. A variety of the non-PLL based buffers are available on the market today and typically range from as few as 4 outputs to as many as 30. Some devices also include configurable I/O and internal registers to divide the output frequencies.Among the highest performance non-PLL based Low Voltage CMOS (LVCMOS) clock buffers available today is the B9940L. The B9940L is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V- or 3.3V-compatible and can drive two series terminated 50-Ohm transmission lines. With this capability, the B9940L has an effective fan out of 1:36. Low output-to-output skews of 150 ps, a device to device skew of 750 ps, and a high-end operating frequency of 200 MHz, makes the B9940L an ideal clock distribution buffer for nested clock trees in synchronous systems.These devices still face the problems of device propagation delay. The propagation delay through these devices is about 5 ns. This delay will cause skew in systems where both the reference clock to the buffer and the outputs of the buffer need to be aligned. These devices also have the drawback that the output waveform is directly based on the input waveform. If the input waveform is a non-50% duty-cycle clock, the output waveform will also have a less-than-ideal duty cycle. Expensive crystal oscillators with tight tolerances are needed when using this type of buffer in systems requiring near 50/50 outputs.These devices also lack the ability to phase adjust or frequency multiply their outputs. Phase adjustment allows the clock driver to compensate for trace propagation delay mismatches and setup and hold time differences, and frequency multiplication allows the distribution of high and low frequency clocks from the same common reference. Expensive components and time-consuming board routing techniques must be used to compensate for the functional shortcomings of these buffer-style clock driver devices. PLL-based devices have been incorporated to address all of these shortcomings.◆PLL-Based Clock DriversThe second type of clock distribution device uses a feedback input that is a function of one of its outputs. The feedback input can be connected internally or externally to the part. If it’s an external feedback, a trace is used to connect an output pin to the feedback pin. This type of device is usually based upon one or more PLLs that are used to align the phase and frequency of the feedback input and the reference input. Since the feedback input is a reflecion of an output pin, the propagation delay is effectively eliminated. In addition to very low device propagation delay, this type of architecture enables output signals to be phase shifted to compensate for board-level trace-length mismatches. Outputs can be selectively divided, multiplied, or inverted while still maintaining very low output skew.PLLs have a number of desirable properties that include the ability to multiply clock frequencies, correct clock duty cycles and cancel out clock distribution delays. Many PLL based clock buffers have been brought to market in recent years to aid clock tree designs that require zero propagation delay from the input signal to the output. A completely integrated PLL allows alignment in both the phase and the frequency of the reference with an output. We will look at some of the more prevalent PLL-based clock buffers and their features in the following sections.◆What is a PLL?The basic PLL is a feedback system that receives an incoming oscillating signal and generates an output waveform that oscillates at the same frequency as the input signal. It is comprised of a phase/frequency detector (PD), a low-pass filter, and a voltage-controlled oscillator as shown in Figure 2.6. In order for the PLL to align the reference (REF) input with an output, the output must be fed back to the input of the PLL. This feedback (FB) input is used as the alignment signal on which all other outputs are based.The Phase Frequency Detector (PD) evaluates the rising edge of the REF input with respect to the FB input. If the REF input occurs before the FB input indicating that the VCO is running too slowly, the PD produces a Pump Up signal that lasts until the rising edge of the FB input. If the FB input occurs before the REF input, the PD produces a Pump Down signal that is triggered on the rising edge of the FB input and lasts until the rising edge of REF. This Pump Down pulse forces the VCO to run slower. In this way, the PD forces the VCO to run faster or slower based on the relationship of the REF and FB inputs. The output of the VCO is the internally generated oscillator waveform. The input voltage that controls the frequency of the VCO is a measure of the input frequency — as the input frequency changes so does this voltage. The PLL is designed to operate within a limited band of frequencies. If the input frequency is outside this band, the circuit will not lock-on to the input signal and FREF and FOUT will be different. As long as FREF remains within the tracking range of the circuit, FOUT = FREF. However, if FREF moves out of range, the circuit goes out of lock, and once again the input and internal frequencies will be different. In the absence of a REF input, the condition of the output is device-specific. For instance, with the loss of a reference input, the Cypress CY2308 ZDB will tri-state all outputs.However, the outputs of the CY7B991V operate at the device’s slowest speed while the outputs of the CY7B994Vwill run at their highest frequency. Therefore, the specifics of the device need to be known if the design will be placed in this condition. (There are now buffers that support dual clock inputs if the loss of an input clock is expected.) The filter converts these Pump Up and Pump Down signals into a single control voltage (FCONT) and its magnitude is dependent on the number of previous Pump Up and Pump Down pulses that have occurred. The range of the voltage produced by the filter is guaranteed to force the VCO into any frequency within the selected frequency range.◆Zero Delay BufferA zero delay buffer (ZDB) is a device that can fanout one clock signal into multiple clock signals with zero delay and very low skew between the outputs. This device is well suited for a variety of clock distribution applications requiring tight input-output and out skews. A simplified diagram of a ZDB is shown in Figure 2.7. A ZDB is built with a PLL that uses a reference input and a feedback input. The feedback input is driven by one of the outputs. The phase detector adjusts the output frequency of the VCO so that its two inputs have no phase or frequency difference. Since the PLL control loop includes one of the outputs and its load, it will dynamically compensate for the load placed on that output.This means that it will have zero delay from the input to the output that drives feedback independent of the loading on that output. Note that this is only the case for the output being monitored by the Feedback input and all other outputs have an input to output delay that is affected by the differences in the output loads. Please see the section “Lead or Lag Adjustment” for a discussion of this topic.The Cypress Semiconductor CY2308 is a dual bank, general purpose ZDB providing eight copies of a single input clock with zero delay from input to output and low skew between outputs. This popular buffer is designed for use in a variety of clock distribution applications and will be used throughout this book as the typical Zero Delay, PLL-based buffer. The capability to externally connect the feedback path on the device provides skew-control and opens up opportunities for some interesting applications.◆Using External FeedbackMany ZDBs have an open external feedback path that is simply closed by driving any output into the FB pin for ZDB operation. However, the feedback path can be used for other interesting applications. Using a discrete delay element in the feedback path will generate outputs that lead the input signal. Sometimes designs require some copies of a clock that are early compared to the remaining copies of the input clock. Figure 2.9 shows a circuit implementation to generate such early clocks using a ZDB.Another simple approach to lead or lag output clocks is to insert trace delay into the feedback path. The outputs of the buffer will lead the input by the amount of trace delay added in the feedback path. This approach provides a precise method for delay adjustment. Some designers will embed a very long trace into the board from anoutput pin to the feedback pin. At the ends of each trace segment, the designer places pads for zero ohm resistors. This allows for incremental additional delay into the feedback path to align the outputs to the precise phase. Figure 2.10 shows an example where the feedback path is 5 inches shorter than the other output traces. This initially allows the remaining outputs to be later in time than the input. By placing a capacitor on the feedback line, the outputs can be moved forward in time.。
Si53360 61 62 65 低噪声 LVCMOS 分输出时钟缓冲器说明书
Si53360/61/62/65 Data Sheet Low-Jitter, LVCMOS Fanout Clock Buffers with up to 12 outputsand Frequency Range from dc to 200 MHzThe Si53360/61/62/65 family of LVCMOS fanout buffers is ideal for clock/data distri-bution and redundant clocking applications. The family utilizes Skyworks advanced CMOS technology to fanout clocks from dc to 200 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. Built-in LDOs deliver high PSRR performance and eliminates the need for external components simplifying low jitter clock distribution in noisy environments.The CMOS buffers are available in multiple configurations with 8 outputs(Si53360/61/65), or dual banks of 6 outputs each (Si53362). These buffers can be paired with the Si534x clock generators and Si5xx oscillators to deliver end-to-end clock tree performance.KEY FEATURES•Low additive jitter: 120 fs rms•Built-in LDOs for high PSRR performance •Up to 12 LVCMOS Outputs from LVCMOS inputs•Frequency range: dc to 200 MHz •Multiple configuration options•Dual Bank option•2:1 Input MUX option•RoHS compliant, Pb-free •Temperature range: –40 to +85 °CCLK0CLK1CLK_SEL CLKTable of Contents1. Ordering Guide (3)2. Functional Description (4)2.1 LVCMOS Input Termination (4)2.2 Input Mux (4)2.3 Output Clock Termination Options (5)2.4 AC Timing Waveforms (6)2.5 Power Supply Noise Rejection (6)2.6 Typical Phase Noise Performance: Single-Ended Input Clock (7)2.7 Input Mux Noise Isolation (8)3. Electrical Specifications (9)4. Detailed Block Diagrams (12)5. Si5336x Pin Descriptions (15)5.1 Si53360 Pin Descriptions (15)5.2 Si53361 Pin Descriptions (17)5.3 Si53362 Pin Descriptions (19)5.4 Si53365 Pin Descriptions (21)6. Package Outline (22)6.1 16-Pin TSSOP Package (22)6.2 16-Pin QFN Package (24)6.3 24-Pin QFN Package (25)7. PCB Land Pattern (26)7.1 16-Pin TSSOP Land Pattern (26)7.2 16-Pin QFN Land Pattern (27)7.3 24-Pin QFN Land Pattern (29)8. Top Markings (31)8.1 Si53360/65 Top Markings (31)8.2 Si53361 Top Marking (32)8.3 Si53362 Top Marking (33)9. Revision History (34)Si53360/61/62/65 Data Sheet • Ordering Guide1. Ordering GuideTable 1.1. Si5336x Ordering Guide2. Functional DescriptionThe Si53360/61/62/65 are a family of low-jitter, low skew, fixed format (LVMCOS) buffers. These devices are available in multiple configurations customized for the end application (refer to 1. Ordering Guide for more details on configurations).2.1 LVCMOS Input TerminationThe table below summarizes the various ac- and dc-coupling options supported by the LVCMOS device, and the figure shows the recommended input clock termination.Table 2.1. LVCMOS Input Clock OptionsV DDCMOSDriverNote: Value for Rs should be chosen so that the total source impedance matches the characteristic impedance of the PCB trace.Figure 2.1. Recommended Input Clock Termination2.2 Input MuxThe Si53360-61/62 provide two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The following table summarizes the input and output clock based on the input mux settings.Table 2.2. Input Mux Logic2.3 Output Clock Termination OptionsThe recommended output clock termination options are shown below. Unused outputs should be left unconnected.CMOSNote:Rs = 33 ohm for 3.3 V and 2.5 V operation.Rs = 0 ohm for 1.8 V operation.Figure 2.2. LVCMOS Output Termination2.4 AC Timing WaveformsQ N Q MT SKT SKT PLHT RT FQQCLK QT PHLOutput-Output SkewPropagation DelayRise/Fall TimeVPP/2VPP/280% VPP 20% VPPFigure 2.3. AC Timing Waveforms2.5 Power Supply Noise RejectionThe device supports on-chip supply voltage regulation to reject power supply noise and simplify low-jitter operation in real-world envi-ronments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements.See “AN491: Power Supply Rejection for Low-Jitter Clocks ” for more information.2.6 Typical Phase Noise Performance: Single-Ended Input ClockEach of the phase noise plots superimposes Source Jitter and Total Jitter on the same diagram.•Source Jitter - Reference clock phase noise (measured Single-ended to PNA).•Total Jitter - Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. For more information, see 3. Electrical Specifications.Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS).measured hereFigure 2.4. Single-ended Measurement Method The following figure shows three phase noise plots superimposed on the same diagram.Figure 2.5. Total Jitter Single-Ended Input (156.25 MHz)2.7 Input Mux Noise IsolationThe input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when clocks are present at both the CLK0 and CLK1 inputs. The following figure shows a measurement of the input mux’s noise isolation.Figure 2.6. Input Mux Noise Isolation (Single-ended Input Clock, 16QFN Package)3. Electrical SpecificationsTable 3.1. Recommended Operating ConditionsTable 3.2. Input Clock SpecificationsV DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, T A = –40 to 85 °CTable 3.3. DC Common Characteristics (CLK_SEL, OEx) V DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, T A = –40 to 85 °CTable 3.4. Output Characteristics (LVCMOS) V DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, T A = –40 to 85 °CTable 3.5. AC CharacteristicsV DD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, T A = –40 to 85 °CTable 3.6. Additive JitterTable 3.7. Thermal ConditionsTable 3.8. Absolute Maximum Ratings4. Detailed Block DiagramsCLK0CLK1 CLK_SELQ0Q1Q2Q3Q4Q5Q6Q7Si53361 - 16-QFN 3x3 mmVDDO (Si53361 only)Figure 4.1. Si53360 and Si53361 Block DiagramQ7Q6Q8OEBVDDOBQ10Q9Q11Q1Q0Q2OEA VDDOA Q4Q3Q5CLK0CLK1CLK_SELFigure 4.2. Si53362 Block DiagramCLKFigure 4.3. Si53365 Block Diagram5. Si5336x Pin Descriptions5.1 Si53360 Pin DescriptionsCLK0CLK1Q2Q1GND Q6Q5Q3VDD Q0VDD Q7GND OE Q4CLK_SELFigure 5.1. Si53360 Pin Descriptions Table 5.1. Si53360 16-TSSOP Pin Descriptions5.2 Si53361 Pin DescriptionsO EC L K 1Q0Q1Q 2Q 3Q 4Q 5Q6C L K _S E LQ7VDDGND VDDO C L K 0GNDFigure 5.2. Si53361 Pin Descriptions Table 5.2. Si53361 16-QFN Pin Descriptions5.3 Si53362 Pin DescriptionsVDDN CN CN C CLK_SELQ2Q3V D D O A Q 4Q 5Q 6Q 7V D D O BQ11Q8N CQ9Q1OEA C L K 1OEB Q0C L K 0Q10Figure 5.3. Si53362 Pin Descriptions Table 5.3. Si53362 24-QFN Pin Descriptions5.4 Si53365 Pin DescriptionsQ6Q7VDD GND VDD Q2GND Q4OE Q0Q3VDD GND CLK Q5Q1Figure 5.4. Si53365 Pin Descriptions Table 5.4. Si53365 16-TSSOP Pin DescriptionsSi53360/61/62/65 Data Sheet • Si5336x Pin Descriptions6. Package Outline6.1 16-Pin TSSOP PackageFigure 6.1. 16-Pin TSSOP PackageTable 6.1. 16-Pin TSSOP Package DimensionsTable 6.2. 16-QFN Package DimensionsTable 6.3. 24-QFN Package Dimensions7. PCB Land Pattern7.1 16-Pin TSSOP Land PatternFigure 7.1. 16-Pin TSSOP Land PatternTable 7.1. 16-Pin TSSOP Land Pattern Dimensions7.2 16-Pin QFN Land PatternFigure 7.2. 16-Pin QFN Land PatternTable 7.2. 16-QFN Land Pattern Dimensions7.3 24-Pin QFN Land PatternFigure 7.3. 24-Pin QFN Land PatternTable 7.3. 24-QFN Land Pattern Dimensions8. Top Markings8.1 Si53360/65 Top MarkingsFigure 8.1. Si53360 Top Marking Figure 8.2. Si53365 Top MarkingTable 8.1. Si53360/65 Top Marking ExplanationMark Method:LaserFont Size: 2.0 Point (0.71 mm)Right-JustifiedLine 1 Marking:Device Part Number53360 for Si53360, 53365 for Si53365Line 2 Marking:TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. Line 3 Marking YY = Year, WW = WorkCorresponds to the year and work week of the mold date.WeekFigure 8.3. Si53361 Top MarkingTable 8.2. Si53361 Top Marking ExplanationMark Method:LaserFont Size: 2.0 Point (0.71 mm) Cen-ter-alignedLine 1 Marking:Device Part Number3361 for Si53361Line 2 Marking:TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form.Line 3 Marking YY = Year, WW = WorkWeek Corresponds to the year and work week of the mold date.Figure 8.4. Si53362 Top MarkingTable 8.3. Si53362 Top Marking ExplanationMark Method:LaserFont Size: 2.0 Point (0.71 mm)Right-justifiedLine 1 Marking:Device Part Number53362 for Si53362Line 2 Marking:TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form.Line 3 Marking YY = Year, WW = WorkWeek Corresponds to the year and work week of the mold date.9. Revision HistoryRevision 1.3December, 2018•Changed CLK_SEL from pull-down resistor to pull-up resistor.•Updated output state to low when OE pin is asserted low on Si53365.Revision 1.2December, 2016•Introduced Si53361 and Si53362 new products.•Merged Si53360/65 datasheets with the new products to create a single LVCMOS buffer datasheet.•Added Core supply current spec at multiple supply voltages.•Added “Internal pull-down resistor” typical spec.Copyright © 2021 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. 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Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.Skyworks, the Skyworks symbol, Sky5®, SkyOne ®, SkyBlue™, Skyworks Green™, Clockbuilder ®, DSPLL ®, ISOmodem ®, ProSLIC ®, and SiPHY ® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at , are incorporated by reference.Portfolio/ia/timing SW/HW /CBPro Quality /quality Support & Resources /support ClockBuilder ProCustomize Skyworks clock generators,jitter attenuators and networksynchronizers with a single tool. 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Si53258-EVB 自动汽车级 PCIe 时钟缓冲器评估板用户指南说明书
UG400: Si53258-EVB User's Guide (Using Si53258-D02-AM-QFN40-EVB)The Si53258-EVB is used for evaluating the two input, eight output Si53258A-D02AM Automotive grade PCIe Reference Clock Buffer. The Si53258A-D02AMdevice selects one of two differential input clocks to buffer 8 copies of a 100 MHzHCSL format output clock compliant to PCIe Gen 1/2/3/4/5 common clock andseparate reference clock specifications.EVB FEATURES •Powered from either USB port or external +5Vpower supply.•Two differential input clocks to select from forbuffering.•Eight buffered HCSL format differential outputclocks.•Programmable device core VDD supply foroperation at 3.3 V, 2.5 V, or 1.8 V.•Programmable VDDO (output driver) suppliesallow each of the clock output banks to have itsown power supply voltage selectable from 3.3V, 2.5 V, or 1.8 V.•SMA connectors for all output clocks.•Internal output termination switch selectable for100 Ω or 85 Ω operation.•Output enable (OE) control switch per output.•All output trace lengths matched to 10 inches.•Loss of Signal (LOS) indication LED.Table of Contents1. Functional Block Diagram (3)2. Si53258-EVB Operation (4)2.1 EVB Configuration: Switches & Jumpers (4)3. LEDs (6)4. Output Clocks (7)5. Input Clocks (8)6. Si53258-EVB Rev 1.0 Schematics (9)Location of DIP Switches:Figure 2.1. DIP Switches LocationUG400: Si53258-EVB User's Guide (Using Si53258-D02-AM-QFN40-EVB) • Si53258-EVB OperationUG400: Si53258-EVB User's Guide (Using Si53258-D02-AM-QFN40-EVB) • LEDs3. LEDsThe Si53258-EVB has 2 LEDs defined below.D2: Blue LED indicating +5V presence.D3: Red LED indicating Loss of Signal (LOS). When lit, this LED indicates selected input clock is not present.The Si53258-EVB supports all 8 differential pair output clocks, each terminated as shown in the figure below. The EVB has locations to install 2 pf parallel termination capacitors if desired, which are tagged with “NI” in schematic to indicate they are not installed by default. The outputs are otherwise direct DC coupled to the SMA connectors. Convenient connection pads are also provided for measuring the output with a differential probe, in which case removal of the 0 Ω resistors to isolate the SMA “stub” from the transmission line is suggested.Figure 4.1. Si53258-EVB Output Clock Differential Pair Termination CircuitThe Si53258-EVB supports 2 input clocks (selectable) with input termination as shown below. Each input pair is AC coupled through a 0.1uF capacitor with on-board 50 Ω AC termination from each leg to GND.Figure 5.1. Si53258-EVB Input Clock Differential Pair Termination Circuit。
时钟缓冲器基础知识
时钟缓冲器基础知识时钟是所有电子产品的基本构建块今天。
用于在同步数字系统中的每个数据过渡，有一个时钟，用于控制的寄存器中。
大多数系统使用晶体，频率时序发生器（FTGS ），或廉价的陶瓷谐振器来产生精确的时钟同步的系统。
此外，时钟缓冲器被用来创建多个副本，乘，除时钟频率，甚至移动时钟边沿向前或向后的时间。
许多时钟缓冲解决方案已经创造了超过过去几年，以解决当今高速逻辑系统所需的许多挑战。
其中一些挑战包括：高工作频率和输出频率，传播延迟从输入到输出，输出到输出歪斜引脚之间，周期tocy cle和长期抖动，扩频，输出驱动强度，I / O电压标准和冗余。
因为钟表是最快的信号系统，通常最重的负载下，特别考虑必须在创建时钟树时发出。
在这一章中，我们列出了非P LL和基于PLL的缓冲区的基本功能，并显示这些设备如何被用来解决高速逻辑设计挑战。
在当今的典型的同步设计中，通常需要多个时钟信号，以驱动各种组件。
创建副本的所需数目的时钟树的构建。
树开始于一个时钟源，例如振荡器或外部信号并驱动一个或多个缓冲器。
缓冲器的数量通常是依赖于目标设备的数目和位置。
在过去几年里，通用逻辑组件被用来作为时钟缓冲器。
这些是足够的时间，但他们做一点维持时钟的信号完整性。
事实上，它们实际上是一个不利的电路。
随着时钟树中的速度和时序容限降低增加，传播延迟和输出歪斜变得越来越重要。
在接下来的几节中，我们讨论了旧设备，为什么他们却不足以应付当今的设计需求。
与现代缓冲区相关的常见术语的定义如下。
最后，我们解决了现代时钟缓冲器的属性具有和不具有P LL。
经常被用作时钟源的FTG是一种特殊类型的P L L时钟缓冲器。
◆早期的缓冲器一种时钟缓冲器是一种装置，其输出波形随输入波形。
时钟缓冲器 重要参数
时钟缓冲器重要参数时钟缓冲器是现代电子设备中非常重要的组成部分，它起到了信号传输和数据处理的关键作用。
时钟缓冲器的性能参数直接影响着整个系统的稳定性和可靠性。
本文将重点介绍时钟缓冲器的几个重要参数，并对其进行详细解析。
一、时钟缓冲器的输入电平电压范围时钟缓冲器的输入电平电压范围是指能够被时钟缓冲器正确识别和处理的输入信号的电压范围。
当输入信号的电压超出这个范围时，时钟缓冲器可能无法正常工作，导致系统故障。
因此，合理选择时钟缓冲器的输入电平电压范围非常重要。
二、时钟缓冲器的输入频率范围时钟缓冲器的输入频率范围是指能够被时钟缓冲器正确接收和处理的输入信号的频率范围。
输入信号的频率超出这个范围时，时钟缓冲器可能无法正确识别输入信号，导致系统时序出错。
因此，合理选择时钟缓冲器的输入频率范围对于系统的正常工作至关重要。
三、时钟缓冲器的输出电平电压范围时钟缓冲器的输出电平电压范围是指时钟缓冲器输出信号的电压范围。
输出电平电压范围过大或过小都可能导致系统工作异常或损坏。
因此，合理选择时钟缓冲器的输出电平电压范围对于保证系统的稳定性和可靠性非常重要。
四、时钟缓冲器的输出频率范围时钟缓冲器的输出频率范围是指时钟缓冲器能够提供的输出信号的频率范围。
输出频率范围不仅与时钟缓冲器本身的性能有关，还与外部电路的需求密切相关。
合理选择时钟缓冲器的输出频率范围可以确保系统工作的稳定性和可靠性。
五、时钟缓冲器的功耗时钟缓冲器的功耗是指时钟缓冲器在工作过程中消耗的电能。
功耗的大小直接影响着系统的能耗和发热量，对于一些功耗敏感的应用场景尤为重要。
因此，在选择时钟缓冲器时需要综合考虑功耗指标，以满足系统对能量消耗的要求。
六、时钟缓冲器的延迟时钟缓冲器的延迟是指时钟信号从输入到输出所经过的时间。
延迟的大小直接影响着系统的时序性能和数据传输的准确性。
合理选择时钟缓冲器的延迟指标，可以确保系统的时序要求得到满足。
七、时钟缓冲器的抖动时钟缓冲器的抖动是指时钟信号的频率或相位发生变化的波动现象。
时钟弹簧
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时
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转
动
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工作原理
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减速信号
时钟弹簧 点
引爆雷管
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So，时钟弹簧的功能是及时把点火信号传输给引爆器。
气囊充气
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时钟弹簧工作原理 CLOCK SPRING
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目录 •作用简介 •DAB系统组成 •结构 •工作原理
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DAB系统组成
DAB组成
碰撞&防护 传感器
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时钟弹簧
-Leabharlann 气囊组件结构时钟弹簧主要由柔性扁平电缆（FFC），壳体和线心等组成，壳体固定在转向轴或 组合开关上，线心的上部插入转向盘中，FFC的输入端固定在壳体上，输出端固定在 线心上。在转向盘左右转动时，线心也随着一起转动，带动FFC的输出端一起转动。 当线心受顺时针转动力矩时，FFC被卷紧，卷紧后的FFC各圈紧缠在线心上，松卷时， FFC完全松开，紧贴壳体。
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时钟缓冲器基础知识时钟是所有电子产品的基本构建块今天。
用于在同步数字系统中的每个数据过渡，有一个时钟，用于控制的寄存器中。
大多数系统使用晶体，频率时序发生器（FTGS ），或廉价的陶瓷谐振器来产生精确的时钟同步的系统。
此外，时钟缓冲器被用来创建多个副本，乘，除时钟频率，甚至移动时钟边沿向前或向后的时间。
许多时钟缓冲解决方案已经创造了超过过去几年，以解决当今高速逻辑系统所需的许多挑战。
其中一些挑战包括：高工作频率和输出频率，传播延迟从输入到输出，输出到输出歪斜引脚之间，周期tocycle和长期抖动，扩频，输出驱动强度，I / O电压标准和冗余。
因为钟表是最快的信号系统，通常最重的负载下，特别考虑必须在创建时钟树时发出。
在这一章中，我们列出了非PLL和基于PLL的缓冲区的基本功能，并显示这些设备如何被用来解决高速逻辑设计挑战。
在当今的典型的同步设计中，通常需要多个时钟信号，以驱动各种组件。
创建副本的所需数目的时钟树的构建。
树开始于一个时钟源，例如振荡器或外部信号并驱动一个或多个缓冲器。
缓冲器的数量通常是依赖于目标设备的数目和位置。
在过去几年里，通用逻辑组件被用来作为时钟缓冲器。
这些是足够的时间，但他们做一点维持时钟的信号完整性。
事实上，它们实际上是一个不利的电路。
随着时钟树中的速度和时序容限降低增加，传播延迟和输出歪斜变得越来越重要。
在接下来的几节中，我们讨论了旧设备，为什么他们却不足以应付当今的设计需求。
与现代缓冲区相关的常见术语的定义如下。
最后，我们解决了现代时钟缓冲器的属性具有和不具有PLL。
经常被用作时钟源的FTG是一种特殊类型的PLL时钟缓冲器。
◆早期的缓冲器一种时钟缓冲器是一种装置，其输出波形随输入波形。
输入信号传播通过该设备并重新驱动输出缓冲器。
因此，这种装置具有与它们相关联的传播延迟。
此外，由于通过每个输入输出路径上的设备的传播延迟之间的差异，将歪斜的输出之间存在。
一类非PLL时钟缓冲器的一个例子是74F244 ，可从几个制造商。
这些设备已经面世多年，是适用于设计中的频率分别为20MHz以下。
设计师时钟和风扇出来，只会令到在电路卡上的多个同步设备。
有了这些缓慢的频率和相关的上升时间，设计师们适当的利润，用以满足建立和保持时间的同步接口。
然而，这些缓冲区是不是最佳的为今天的高速时钟要求。
该74F244患有长传播延迟（3 〜5 ns）和长输出到输出偏斜延迟。
基于非PLL时钟缓冲器在最近几年有所改善，并使用更先进的I / O设计技术来提高输出至输出偏斜。
随着时钟周期越短，在时钟分配系统的不确定性或歪斜变得更加的一个因素。
由于时钟用于驱动处理器和同步系统部件之间的数据传输，时钟分配系统是系统设计的一个重要组成部分。
时钟分配系统的设计，不采取歪斜考虑可能会导致系统性能下降和可靠性。
◆时钟偏差歪斜是在指定发生在同一时间的两个信号的到达时间的变化。
歪斜是由驱动装置和变异引起的电路板走线布局变化的电路板延时器的输出歪斜。
由于时钟信号驱动系统的许多部件，并且因为所有这些组件应该正好在同一时间，以进行同步接收的时钟信号，在时钟信号的其目的地的到达的任何变化将直接影响系统的性能。
歪斜通过改变时钟边沿的到来将直接影响系统的利润。
因为在同步系统中的元素所需要的时钟信号，以在同一时间到达时，时钟偏差减小其内的信息，可以通过从一个装置到下一个循环时间。
随着系统速度的提高，时钟偏差的总周期时间的比例越来越大。
当循环次数分别为50纳秒，时钟歪斜很少是设计重点。
即使是歪斜的周期时间20 ％，它不会引起任何问题。
作为循环次数下降到15ns少，时钟偏差，需要不断增加的设计资源的量。
现在，通常情况下，这些高速系统中只能有10 ％专门用于时钟偏移的时序预算的，所以很明显，它必须减少。
有两种类型的时钟偏差的影响系统性能。
时钟驱动器会导致固有偏差和所述印刷电路板（PCB）的布局和设计被称为外源性歪斜。
外在歪斜和布局程序时钟树将在本书后面讨论。
的时间，由于歪斜的变化被定义为以下等式：tSKEW_INTRINSIC =设备引起的偏移tSKEW_EXTRINSIC = PCB +布局+工作环境诱导斜t偏斜= tSKEW_INTRINSIC + tSKEW_EXTRINSIC固有的时钟偏差是造成其本身的时钟驱动器或缓冲器偏移的量。
电路板布局或任何其他设计问题，除了表示对时钟驱动器数据表中的规格不引起内在的歪斜。
◆输出偏斜输出偏斜（TSK ）也称为引脚到引脚歪斜。
输出偏移是在相同的转换相同的设备上的任何两个输出端的延迟之间的差异。
联合电子设备工程委员会（JEDEC ）的输出歪斜定义为与连接在一起的所有驾驶输入和输出的开关在同一方向驾驶时相同的指定负载一台设备的指定输出之间的偏差。
图2.2和2.3显示一个时钟缓冲器与普通输入，通过Co1_n CIN驾驶输出Co1_1 。
输出的上升沿之间的最大绝对差值将被指定为输出歪斜。
在今天的高性能时钟缓冲器典型的输出歪斜大约是200皮秒（ps）的。
◆输入阈值的变化之后，低偏移时钟信号已分发，时钟接收器必须接受时钟输入以最小的变化。
如果接收机的输入端阈值电平是不均匀的，该时钟接收器将响应于时钟信号在不同的时间产生的时钟偏差。
如果一个负载装置有一个1.2伏的阈值和另一个负载装置具有1.7伏的阈值和上升沿速率为1V/ns的，将会有500 ps的歪斜所引起的在该基础上，负载装置的开关点输入信号。
大多数制造商为中心的设备的输入阈值电平接近1.5伏的标称（TTL ）输入设备。
该输入阈值会略有不同，从生产厂家尤其是条件（如电压和温度）的变化。
将TTL规格的输入阈值电平是保证逻辑高时，输入电压高于2.0伏和逻辑低时，输入电压电平低于0.8伏。
这使得一个1.2伏的窗口过电压和温度。
用互补金属氧化物半导体（CMOS）元件轨道摆动的输入有VCC / 2或大约2.5伏，这是比TTL电平高得多的一个典型的输入阈值。
如果阈值电平是不均匀的，时钟偏移会因为这些变化的部件之间发展。
还有很多已经出现，并提供时钟，以不同的子系统时，都必须考虑I / O标准。
表2.1列出下面列出的更普遍的标准随着输入阈值电压。
◆非PLL的时钟驱动器有现代时钟驱动器架构的两种主要类型：缓冲型器件（非PLL）和一个反馈型器件（PLL）。
在缓冲式（非PLL）时钟驱动时，输入波传播通过该装置，并“重新驱动”通过输出缓冲器。
此输出信号直接地跟随输入信号，并具有传播延迟（TPD），取值范围是5纳秒到15纳秒。
这些设备从缓冲器以往不同，如在它们是专为时钟信号而设计的74F244 。
在74F244 ，有八个输入和8路输出。
要创建一个到八个缓冲区，所有八个输入连接在一起。
这会导致过量的负荷在对驱动信号的输入。
一到八个时钟缓冲器只有一个输入，因此只有一个负载。
输出上升和下降时间也难分伯仲，因此不利于占空比误差。
他们改进的I / O结构，引脚到引脚歪斜保持在最低限度。
该设备的输出歪斜，如果它不是数据表上列出的，可以通过减去从最大传播延迟最小传播延迟来计算。
在图2.5所示的10纳秒的tPD时钟驱动器的延迟不考虑影响的电路板布局和设计。
这些类型的设备是极好的缓冲源信号，例如振荡器，其输出相位并不需要匹配输入。
各种各样的基于非PLL缓冲器可在当今市场上，通常范围从少到4路输出，多则30 。
有些设备还包括可配置的I / O和内部寄存器来划分的输出频率。
中最高性能的非今天的PLL基于低电压CMOS （LVCMOS ）时钟缓冲器可为B9940L 。
该B9940L是有能力的低电压时钟分配缓冲区选择的差动LVPECL或LVCMOS / LVTTL的兼容的输入时钟。
这两个时钟源可以用于提供一个测试时钟以及初级系统时钟。
所有其他控制输入的LVCMOS / LVTTL的兼容。
十八输出2.5V - 3.3V或兼容，可驱动两个串联端接50欧姆传输线。
有了这个功能，B9940L有一个有效的扇出1:36 。
150 ps的，一个设备的750 PS装置倾斜，以及200MHz的高端工作频率低输出至输出歪曲，使B9940L嵌套时钟树中同步系统的理想时钟分配缓冲区。
这些设备仍然面临设备传播延迟的问题。
通过这些设备的传播延迟是大约5纳秒。
这个延迟会引起歪斜的系统中两个参考时钟的缓冲液和缓冲液的输出需要被对齐。
这些器件还具有输出波形是直接根据输入波形的缺点。
如果输入波形是一个非50 ％占空比的时钟，输出波形也将有一个低于理想的占空比。
都在使用这种类型的缓冲区中，需要近50/50输出系统所需的昂贵的晶体振荡器具有严格的公差。
这些器件还缺少逐步调整或频率乘以它们的输出能力。
相位调整允许时钟驱动器，以补偿跟踪传播延迟失配和建立和保持时间的差异，和倍频允许的高频和低频时钟从相同的共同的参考分布。
昂贵的组件和费时的电路板布线技术必须被用来补偿这些缓冲式时钟驱动器设备的功能性缺点。
基于PLL的器件已被纳入到解决所有的这些缺点。
◆零延迟缓冲器零延迟缓冲器（ZDB ）是可以扇出的一个时钟信号为多个时钟信号与输出之间的零延迟和非常低歪斜的装置。
该器件非常适合各种要求严格的输入输出时钟分配的应用程序和出倾斜。
一个ZDB的简化框图如图2.7所示。
一个ZDB是建立与使用参考输入和反馈输入一个PLL 。
反馈输入由输出中的一个驱动。
鉴相器调整VCO的输出频率，使得它的两个输入都没有相位或频率的差异。
由于PLL控制回路包括输出和负载中的一个，它会动态地补偿负载放置在该输出。
这意味着，它必须从输入零延迟，驱动该输出负载的反馈独立的输出。
注意，这仅是为了通过反馈输入和所有其它输出被监视的输出有一个输入到输出的延迟是受输出负载的差异的情况。
请参见“超前或滞后调节”这一主题的讨论。
赛普拉斯半导体公司CY2308是一款双银行，通用ZDB提供8个拷贝的单一输入时钟的零延迟从输入到输出和低偏移输出之间。
这种流行的缓冲区是专为在各种时钟分配应用中使用，在本书中，是典型的零延迟，基于PLL的缓冲区将被使用。
外部连接装置上的反馈路径中的能力提供了偏斜控制和开辟了一些有趣的应用程序的机会。
◆使用外部反馈许多ZDBS有一个是简单地通过驱动任何输出到FB引脚为ZDB操作关闭一个开放的外部反馈路径。
然而，在反馈路径可以用于其它有趣的应用。
使用在反馈路径中的离散的延迟元件会产生导致的输入信号的输出。
有时，设计需要一个时钟，是比较早期的输入时钟的剩余份数的一些副本。
图2.9显示了一个电路实现，生成使用ZDB这种早期的时钟。