第9章数字系统设计verilog HDL(第6版)王金明

第9章 Verilog设计进阶9.1 加法器设计（1）级连加法器8位级连加法器module add_jl(sum,cout,a,b,cin);input[7:0] a,b;input cin;output[7:0] sum;output cout;full_add1 f0(a[0],b[0],cin,sum[0],cin1); full_add1 f1(a[1],b[1],cin1,sum[1],cin2); full_add1 f2(a[2],b[2],cin2,sum[2],cin3); full_add1 f3(a[3],b[3],cin3,sum[3],cin4); full_add1 f4(a[4],b[4],cin4,sum[4],cin5); full_add1 f5(a[5],b[5],cin5,sum[5],cin6); full_add1 f6(a[6],b[6],cin6,sum[6],cin7); full_add1 f7(a[7],b[7],cin7,sum[7],cout); endmodule（2）数据流描述的加法器module add_bx(cout,sum,a,b,cin); parameter WIDTH=8; input cin; output cout; input[WIDTH-1:0] a,b; output[WIDTH-1:0] sum; assign {cout,sum}=a+b+cin;endmodule（3） 8位超前进位加法器moduleadd_ahead(sum,cout,a,b,cin); input[7:0] a,b;input cin;output[7:0] sum;output cout;wire[7:0] G,P;wire[7:0] C,sum;assign G[0]=a[0]&b[0]; assign P[0]=a[0]|b[0]; assign C[0]=cin;assign sum[0]=G[0]^P[0]^C[0]; assign G[1]=a[1]&b[1]; assign P[1]=a[1]|b[1]; assign C[1]=G[0]|(P[0]&cin); assign sum[1]=G[1]^P[1]^C[1]; assign G[2]=a[2]&b[2]; assign P[2]=a[2]|b[2]; assign C[2]=G[1]|(P[1]&C[1]); assign sum[2]=G[2]^P[2]^C[2]; assign G[3]=a[3]&b[3]; assign P[3]=a[3]|b[3]; assign C[3]=G[2]|(P[2]&C[2]); assign sum[3]=G[3]^P[3]^C[3];assign G[4]=a[4]&b[4]; assign P[4]=a[4]|b[4]; assign C[4]=G[3]|(P[3]&C[3]); assign sum[4]=G[2]^P[2]^C[2]; assign G[5]=a[5]&b[5]; assign P[5]=a[5]|b[5]; assign C[5]=G[4]|(P[4]&C[4]); assign sum[5]=G[5]^P[5]^C[5]; assign G[6]=a[6]&b[6]; assign P[6]=a[6]|b[6]; assign C[6]=G[5]|(P[5]&C[5]); assign sum[6]=G[6]^P[6]^C[6]; assign G[7]=a[7]&b[7]; assign P[7]=a[7]|b[7]; assign C[7]=G[6]|(P[6]&C[6]); assign sum[7]=G[7]^P[7]^C[7]; assign cout=G[7]|(P[7]&C[7]); endmodule（4）流水线加法器module adder8(cout,sum,a,b,cin,enable); input[7:0] a,b; input cin,enable; output[7:0] sum; reg[7:0] sum;output cout;reg cout;reg[3:0] tempa,tempb,firsts; reg firstc; always @(posedge enable)begin{firstc,firsts}=a[3:0]+b[3:0]+cin; tempa=a[7:4]; tempb=b[7:4];endalways @(posedge enable)begin{cout,sum[7:4]}=tempa+tempb+firstc; sum[3:0]=firsts;endendmodule9.2 乘法器）并行乘法器（1module mult(outcome,a,b); parameter size=8;input[size:1] a,b;output[2*size:1] outcome; assign outcome=a*b;endmodule8×8并行乘法器的门级综合原理图（2）移位相加乘法器4×4移位相加乘法操作示意图8位移位相加乘法器顶层设计8位移位相加乘法器时序仿真波形（3）布斯乘法器（4）查找表乘法器9.3 奇数分频与小数分频（1）奇数分频module count7(reset,clk,cout);input clk,reset; output wire cout;reg[2:0] m,n; reg cout1,cout2;assign cout=cout1|cout2;//两个计数器的输出相或always @(posedge clk)beginif(!reset) begin cout1<=0; m<=0; endelse begin if(m==6) m<=0; else m<=m+1;if(m<3) cout1<=1;else cout1<=0; end endalways @(negedge clk)beginif(!reset) begin cout2<=0; n<=0; endelse begin if(n==6) n<=0; else n<=n+1;if(n<3) cout2<=1; else cout2<=0; end endendmodule模7奇数分频器功能仿真波形图（Quartus Ⅱ）module count_num(reset,clk,cout);parameter NUM=13;input clk,reset; output wire cout;reg[4:0] m,n; reg cout1,cout2;assign cout=cout1|cout2;always @(posedge clk)begin if(!reset) begin cout1<=0; m<=0; endelsebegin if(m==NUM-1) m<=0; else m<=m+1;if(m<(NUM-1)/2) cout1<=1; else cout1<=0;endendalways @(negedge clk)begin if(!reset) begin cout2<=0; n<=0; endelse beginif(n==NUM-1) n<=0; else n<=n+1;if(n<(NUM-1)/2) cout2<=1; else cout2<=0; end endendmodule模13奇数分频器功能仿真波形图（Quartus Ⅱ）module fdiv5_5(clkin,clr,clkout);input clkin,clr; output reg clkout;reg clk1; wire clk2; integer count;xor xor1(clk2,clkin,clk1); //异或门always@(posedge clkout or negedge clr) //2分频器begin if(~clr) begin clk1<=1'b0; endelse clk1<=~clk1;endalways@(posedge clk2 or negedge clr) //模5分频器begin if(~clr)begin count<=0; clkout<=1'b0; endelse if(count==5) //要改变分频器的模，只需改变count的值begin count<=0; clkout<=1'b1; endelse begin count<=count+1; clkout<=1'b0; end endendmodule功能仿真波形5.5倍半整数分频器功能仿真波形图（Quartus Ⅱ）小数分频module fdiv8_1(clk_in,rst,clk_out);input clk_in,rst; output reg clk_out;reg[3:0] cnt1,cnt2;//cnt1计分频的次数always@(posedge clk_in or posedge rst)begin if(rst) begin cnt1<=0; cnt2<=0; clk_out<=0; endelse if(cnt1<9)//9次8分频begin if(cnt2<7) begin cnt2<=cnt2+1; clk_out<=0; end else begin cnt2<=0; cnt1<=cnt1+1; clk_out<=1; end end else begin //1次9分频if(cnt2<8) begin cnt2<=cnt2+1; clk_out<=0; end else begin cnt2<=0; cnt1<=0; clk_out<=1; endend endendmodule8.1小数分频功能仿真波形（Quartus Ⅱ）9.4 VGA图像显示控制器设计VGA 行扫描时序VGA 场扫描时序标准VGA显示模式行、场扫描的时序行扫描时序要求（单位：像素，输出一个Pixel的时间间隔）行同步头行图像行周期对应位置H_Tf H_Ta H_Tb H_Tc H_Td H_Te H_Tg时间/Pixels8964086408800场扫描时序要求（单位：行，输出一行Line的时间间隔）场同步头场图像场周期对应位置V_Tf V_Ta V_Tb V_Tc V_Td V_Te V_Tg时间/Lines222584808525VGA图像显示控制器设计VGA图像显示控制器结构框图R，G，B三基色信号分别采用5 bit，6 bit，5 bit表示的LENA图像9.5 点阵式液晶显示控制GDM12864的结构及指令“写数据”时序图液晶控制9.6 乐曲演奏电路乐曲演奏的原理乐曲演奏电路原理框图习题 9习题 9习题 9实验与设计。