基于FPGA的SDRAM实验Verilog源代码

// megafunction wizard: %ALTPLL%

// GENERATION: STANDARD

// VERSION: WM1.0

// MODULE: altpll

// ============================================================ // File Name: clk_ctrl.v

// Megafunction Name(s):

// altpll

//

// Simulation Library Files(s):

// altera_mf

// ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 11.0 Build 208 07/03/2011 SP 1 SJ Full Version

// ************************************************************

//Copyright (C) 1991-2011 Altera Corporation

//Your use of Altera Corporation's design tools, logic functions

//and other software and tools, and its AMPP partner logic

//functions, and any output files from any of the foregoing

//(including device programming or simulation files), and any

//associated documentation or information are expressly subject

//to the terms and conditions of the Altera Program License

//Subscription Agreement, Altera MegaCore Function License

//Agreement, or other applicable license agreement, including,

//without limitation, that your use is for the sole purpose of

//programming logic devices manufactured by Altera and sold by

//Altera or its authorized distributors. Please refer to the

//applicable agreement for further details.

// synopsystranslate_off

`timescale 1 ps / 1 ps

// synopsystranslate_on

moduleclk_ctrl (

areset,

inclk0,

c0,

c1,

c2,

locked);

input areset;

input inclk0;

output c0;

output c1;

output c2;

output locked;

`ifndef ALTERA_RESERVED_QIS

// synopsystranslate_off

`endif

tri0 areset;

`ifndef ALTERA_RESERVED_QIS

// synopsystranslate_on

`endif

wire [5:0] sub_wire0;

wire sub_wire2;

wire [0:0] sub_wire7 = 1'h0;

wire [2:2] sub_wire4 = sub_wire0[2:2];

wire [0:0] sub_wire3 = sub_wire0[0:0];

wire [1:1] sub_wire1 = sub_wire0[1:1];

wire c1 = sub_wire1;

wire locked = sub_wire2;

wire c0 = sub_wire3;

wire c2 = sub_wire4;

wire sub_wire5 = inclk0;

wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};

altpll altpll_component (

.areset (areset),

.inclk (sub_wire6),

.clk (sub_wire0),

.locked (sub_wire2),

.activeclock (),

.clkbad (),

.clkena ({6{1'b1}}),

.clkloss (),

.clkswitch (1'b0),

.configupdate (1'b0),

.enable0 (),

.enable1 (),

.extclk (),

.extclkena ({4{1'b1}}),