(数字电路的噪声和布局)

南京师范大学电气与电子工程学院教学授课计划60

Chp. 8DIGITAL CIRCUIT NOISE AND LAYOUT

（数字电路的噪声和布局）

本章学习要求：了解如下主要概念、方法和内容。

1．时域与频域关系，模拟与数字电路关系等

2．数字逻辑器件的噪声（内部噪声源分析）

3．数字电路接地系统噪声（接地线电感的影响；减小电感的方法，实际数字电路接地系统考虑等）

4．电源分配（电源解偶解偶电容类型与数值，电解解偶电容，解偶电容的配置）

5．噪声电压控制目标与测量

§8.1 Introduction

1. A digital system is also a radio-frequency (RF) system with noise and

interference potential

2.Small IC digital logic gates ( 数字逻辑门电路 ) , which draw only a few

mA current, can also be a serious noise source for

(1)high switching speed

(2)combined with inductance of the conductor

The noise source when current change through an inductor

di

V L

dt

Example: “on”state, I = 5mA,

“off”state, I = 1 mA

So i 4mA , however t 2ns!!

Also if a power supply wiring has an inductance of 500mH, L = 500 mH

南京师范大学电气与电子工程学院教学授课计划61 The noise voltage across the power supply wiring when gate change state

di

V N L

dt

500mH =1V!4mA 2ns

Realizing the power supply voltage of this system is only 5 V,therefore

V N%1V%20%

V5V

3.Chp.8 and Chp.9 will discuss techniques to minimize

(1)internal noise generation (2) radiated emission

§8.2 Frequency Versus Time Domain频(域与时域关系 )

1.Though digital circuit works in time domain, because legal requirement

on the emission are specified in frequency-domain, so “f”versus “t”

should be known

2.Bandwidth of a digital system

Definition: logic pulse bandwidth should be the point , where the energy content in the harmonic (consist a square wave) is negligible when

beyond this point. Or the break point where the Fourier coefficient start to decay at 40dB/decade

BW 1 t r

t r : pulse rise time e.g. t r = 2 ns, BW = 159 MHz

Typical rise/fall time and related bandwidth for logic device

§8.3 Analog Versus Digital Circuit

1.In an analog circuit, small noise coupled into circuit may cause

interference, which often occurs in low signal level (mV , mA) or in high-

gain amplifier ; In contrast, digital circuit have no amplifier and

南京师范大学电气与电子工程学院教学授课计划62 operate at large signal level

2. For noise margin LSTTL, V =400mV~600mV, CMOS, V

N =1.5V( Vcc

N

= 5 V) , So digital circuit have an inherent immunity to low-level noise

§8.4 Digital Logic Noise

1.In analog circuit, external noise is usually the primary concern, however,

in digital circuit, internal noise source is the major concern

2.Reason for internal noise

(1)ground bus noise

(2)power bus noise

(3)transmission line reflection

(4)cross talk

3.Noise measurement requirement

A)ground voltage difference between various points in the system

B)Vcc-to-ground voltage on the power supply pins of all IC’s

§8.5 Internal Noise Source

1.Fig. 8-1 Noise generation when output of gate “1”switches from high

to low ( P277)

2.Since gate “1”resistance R is very small in discharge path (R,L,C in series), high-Q

resonant may cause output to negative

Q

1 L

R C

Fig.8-2 output voltage waveform( p278)

(A)ringing due to stray capacitance and inductance (B) ringing damped by adding

output resistor

So R Q