Sitime MEMS硅晶振介绍
SiTime MEMS硅晶振航空航天解决方案
DIFFERENTIAL LOW-JITTER OSCILLATORS | Better reliability | 0.2 ps/mV power supply noise rejection (PSNR)
SiT9346/47
1 MHz to 725 MHz ±10, ±20, ±25, ±50 2.5 to 3.3
• n/a •
Acceleration survivability
•••
Frequency warm up
• n/a n/a
Best-in-Class Aging
Lower Acceleration (g) Sensitivity
Frequency Stability (ppm)
1 year 5 years 10 years 15 years 20 years
SiT8944 SiT8945
1 MHz to 110 MHz 115 MHz to 137 MHz
±20, ±25, ±50
1.8, 2.5 to 3.3
3.5 to 4.5 mA 4.9 to 6 mA
2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2,
7.0 x 5.0
Custom value-added services include:
100% burn-in to screen for infant mortality 100% test at extreme temperatures Q uality conformance inspection (QCI), sample testing for high reliability Customer-generated drawings Custom test flows
SiT8008数据手册-SiTime低功耗1-110MHz任意频率单端有源晶振
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and nominal supply voltage.
+50 ppm Operating Temperature Range +70 °C
Hale Waihona Puke – +85 °C Industrial Supply Voltage and Current Consumption 1.8 2.5 2.8 3.0 3.3 – 3.8 3.7 3.5 – – 2.1 1.1 1.98 2.75 3.08 3.3 3.63 3.63 4.5 4.2 4.1 4.2 4.0 4.3 2.5 V V V V V V mA mA mA mA mA A A Contact SiTime for 1.5V support
Table 2. Pin Description
Pin Symbol Output Enable 1 OE/ST/NC Standby No Connect 2 3 4 GND OUT VDD Power Output Power Functionality H[1]: specified frequency output L: output is high impedance. Only output driver is disabled. H[1]: specified frequency output L: output is low (weak pull down). Device goes to sleep mode. Supply current reduces to I_std. Any voltage between 0 and Vdd or Open[1]: Specified frequency output. Pin 1 has no function. Electrical ground Oscillator output Power supply voltage[2] OE/ST/NC
SiTime 全硅MEMS可编程振荡器产品推荐
深圳市福浪電子有限公司
FRONTER ELECTRONICS CO.，LTD 地址 ADD：深圳市福田区深南大道 6021 号喜年中心 1112-1117 室 RM.1112-1117, XINIAN CENTER, NO.6021, SHENNAN Blvd . SHENZHEN,CHINA 电话 TEL：86-755-83458728/13823529576 陈军 Johnson Chen 传真 FAX： 86-755-83459818 网址 WEB ADD： 邮件 E-MAIL：chj@
未温度补偿前之纯硅谐振器
50
温度特性 25 PPM SiTime振荡器 较好的系统设计余量
40
30
20
10 Frequency ppm error
± 25ppm
0
-10
-20
-30
25 PPM 石英产品
-40
高低温设计余量较差
-50 -40 -30 -20 -10 0 10 20 30 Tem perature (C) 40 50 60 70 80 90
深圳市福浪電子有限公司
FRONTER ELECTRONICS CO.，LTD 地址 ADD：深圳市福田区深南大道 6021 号喜年中心 1112-1117 室 RM.1112-1117, XINIAN CENTER, NO.6021, SHENNAN Blvd . SHENZHEN,CHINA 电话 TEL：86-755-83458728/13823529576 陈军 Johnson Chen 传真 FAX： 86-755-83459818 网址 WEB ADD： 邮件 E-MAIL：chj@
有今日在所有电子产品设计内所使用的 IC 一般； 具备优良的稳定性及品质； 杜绝在生产过程中出现的 人为失误。产品的品质一致性是透过设计阶段完成，与石英产品在量产阶段控制品质之制造控管方式 不同，系统厂商无须担心来料与量产样品认证的不一致性。 3、SITIME 全硅 MEMS 可编程振荡器；支持频率、精度、电压可编程；可满足客户不同规则组合振 荡器需求。 4、SITIME 支持所有业界标准封装（7050，5032，3225，2520） ，所有规格产品交货期仅需 2-4 周。 5、SITIME 全矽 MSMS 振荡器内部起振锁相环晶片，具备温补功能；频率精度相对于温度的变化为 线性关系，规格所标示的频率精度涵盖震动频偏、温度频偏、老化频偏等，在-40~+85℃的工作温度范 围内温度频差可以控制到±10ppm。 6、 SITIME 全硅 MSMS 振荡器封装无密封问题， 防振性达石英产品的 25 倍。 出货不良率低于 1dppm。 7、SITIME 目前产品线涵盖范围已达石英振荡器应用的 70%市场；包括工控、监控、Computing、视 频应用、网络产品、消费类产品、低功耗产品、高速数据传输等。
SiTime MEMS硅晶振：时钟抖动定义与测量方法
时钟抖动定义与测量方法1引言抖动是时钟信号边沿事件的时间点集合相对于其理想值的离散时序变量。
时钟信号中的抖动通常是由系统中的噪声或其他干扰导致的。
具体因素包括热噪声、电源变化、负载条件、器件噪声以及相邻电路耦合的干扰等。
2抖动类型时钟信号抖动定义有多种主要是：∙周期抖动 (Period Jitter）∙相邻周期抖动(Cycle to Cycle Period Jitter)∙长期抖动(Long Term Jitter)∙相位抖动(Phase Jitter)∙时间间隔误差(Time Interval Error or TIE)2.1周期抖动周期抖动是时钟信号的周期时间相对于一定数量、随机选定的理想时钟信号周期的偏差。
如果我们能对一定数量的时钟周期进行测量，就可以计算出这一段时间测量窗口内的平均时钟周期以及其标准偏差与峰峰值。
我们通常将标准偏差和峰峰值分别称作 RMS 值和 Pk-Pk 周期抖动。
许多已发表的文献中往往将周期抖动定义为测得的时钟周期与理想周期之间的差异，但在实际应用中，想要量化理想周期往往有困难。
如果用示波器观察设定频率为 100 MHz 的振荡器的输出，测得的平均周期可能是 9.998 ns，而非理想周期的 10 ns。
因此，在实际测量中可将测量时间窗口内的平均周期视为理想周期。
周期抖动应用2.1.1周期抖动在数字系统中的时序冗余度计算方面非常实用。
例如，在一个基于微处理器的系统中，处理器在时钟上升之前需要 1 ns 的数据建立时间。
如果时钟的周期抖动为 -1.5 ns ，则时钟的上升沿可能发生在数据有效前，因而微处理器可能得到不正确的数据。
该实例如图 1 所示。
图 1：因时钟抖动造成的数据建立时间冲突同样，如果另一个微处理器的数据保持时间要求为 2 ns ，但时钟抖动为 +1.5 ns ，则数据保持时间缩短至 0.5 ns 。
微处理器也会得到不正确的数据。
这种情况如图 2 所示。
SiTime MEMS硅晶振FirstTM 工艺
SiTime MEMS First TM工艺目录1引言 (1)1.1封装 (1)1.2稳定性 (2)1.3耐久性 (2)1.4尺寸 (2)1.5可制造性 (2)1.6质量 (2)2 MEMS FirstTM 工艺流程详解 (3)2.1 谐振器定义 (3)2.2 氧化物填充 (3)2.3 通气孔的形成 (4)2.4 谐振器结构释放 (4)2.5 谐振器密封 (5)2.6 电气通孔的形成 (5)2.7 金属导线层 (6)3MEMS First TM工艺的特性与优势 (6)4结论 (6)1引言MEMS FirstTM 是SiTime 用于制造硅谐振器晶片的工艺。
它可生产完全封装在硅材料中的、极其稳定且高持久性的超小型谐振器。
由于该工艺采用标准 CMOS 晶圆代工厂工具及材料，因而其产品不仅很容易制造，而且还具有优异的质量和可靠性。
此外，以大型晶圆形式生产，还可实现大批量快速量产。
以下章节将更加详细地介绍 MEMS FirstTM 工艺的各个重要方面。
1.1封装在开发出MEMS First TM工艺之前，封装是阻碍MEMS 谐振器实现商业化的最大问题。
MEMS First TM工艺能生产出在单独超净真空腔中密封的谐振器的成品晶圆，从而消除这一制约。
这些晶圆不仅看上去很像标准CMOS 晶圆，而且还可采用塑封铸模(plastic molding)、倒装芯片（Flip Chip）以及芯片堆叠等业界标准 IC 封装工艺进行封装。
1.2稳定性MEMS First TM工艺的气密封装特性称为 Epi-Seal TM，该特性是在清洁真空环境中以极高温度实现的。
这有利于谐振器的高稳定性。
使用陶瓷封装或晶圆键合(wafer bonding) 的常规低温封装会在封装中残留挥发性有机物和水，导致谐振器的质量负载和频率漂移。
支持Epi-Seal TM的MEMS First TM是唯一经过验证的制造工艺，能生产出稳定性达到甚至超过石英晶振的谐振器。
sitime硅晶振结构
sitime硅晶振结构
SiTime的MEMS硅晶振的结构包括两个部分：一个是全硅MEMS谐振器，另一个是具备温补功能的启动电路及锁相环CMOS晶片。
两者利用标准的
半导体晶片MCM封装方式完成。
这种结构采用标准的全自动半导体工艺，使得量产产品具有出色的产品一致性表现。
此外，SiTime的Elite Platform™振荡器和Super-TCXO™系列基于一种新颖的架构，由DualMEMS™芯片和混合信号CMOS IC组成，具有专有的温度补偿方案和低噪声频率合成器。
这种架构可实现出色的动态性能、超低抖动、宽频率范围和可编程性。
独特的DualMEMS芯片结构和TurboCompensation™温度补偿可在温度范围内实现卓越的频率稳定性和
对动态热干扰的稳健性。
以上内容仅供参考，建议咨询专业人士获取更具体准确的信息。
SiTime MEMS 振荡器产品数据手册说明书
SiTime introduced two families of ultra-robust AEC-Q100-qualified MEMS oscillators. The SiT2024/25 and SiT8924/25 oscillators deliver the highest performance and best robustness and are designed for ASIL (Automotive Safety Integrity Level) compliant automotive applications such as advanced driver assistance systems (ADAS), in-vehicle Ethernet, powertrain and electronic control units (ECUs).“The automotive industry is going through a massive transformation, with new features such as advanced safety and driver assistance systems, electrification, automation and real-time big data analytics. The usage of electronic components in automobiles is increasing rapidly and requires stringent levels of quality, reliability and performance,” said Piyush Sevalia, executive vice president of marketing at SiTime. “MEMS technologies are playing a significant role in this transformation. SiTime is leveraging our revolutionary silicon MEMS, advanced analog technology and standard semiconductor packaging to provide unique timing solutions that deliver the highest reliability and dynamic performance under extreme temperatures, shock and vibration.”SiTime’s new automotive product families offer a unique combination of the widest frequency range, tightest stability at ±20 ppm and the best reliability. The SiT2024/25 oscillators are optimized for under-the-hood systems such as engine control, transmission control, active suspension control, electronic steering and other ECUs. These oscillators are available in a SOT23-5 leaded package to enable visual inspection and the best solder joint reliability, especially in hot and cold environments. The SiT8924/25 oscillators, available in industry-standard QFN footprints as small as 2.0 x 1.6 mm, are ideal for camera modules and other small form factor systems.than quartz oscillators and deliver the following features and benefits.The SiT2024, SiT2025, SiT8924 and SiT8925 oscillators are in production now. Pricing information and Production Part Approval Process (PPAP) documentation, compliant with the AIAG manual, is available upon request.• AEC-Q100 qualified, Grade 1 (-40°C to +125°C), Grade 2 (-40°C to +105°C) and extended temperature range (-55°C to +125°C)3-wire version with a short-circuit protected open-drain output• SiT2024/2025: SOT23-5 leaded package for best board-level solder-joint reliability and ease-of-use in manufacturing and testLow current consumption of typ. 1.6 mA• SiT8924/8925: Five package options in industry-standard oscillator footprint• Excellent frequency stability at ±20 ppm for best timing margin• Highest reliability at over 1 billion hours MTBF (< 1 FIT)• Best shock resistance at 50,000 g• Best vibration resistance at 70 g• Lowest vibration sensitivity (g-sensitivity) at 0.1 ppb/g • Widest frequency range of 1 to 137 MHz with 6 decimal places of accuracy• Unique, programmable output drive strength for EMI reduction• Supply voltage options of 1.8 V, 2.5 to 3.3 VFEATURESHeadlightsEMI reductionSiT8924/5 & SiT2024/5AEC-Q100 MEMS Oscillator Applications & BenefitsPerformance in Presence of Vibration2016 2520 3225 5032 7050SOT23 SOIC-81. Contact SiTime for ≤±10 ppm stability options.2. Contact SiTime for AEC-Q100 compliance status.3. Contact SiTime for 95°C & 105°C products.。
三分钟你可以把SITIME说清楚 - TC
1.品質不一致2.頻率溫度穩定度差3.交貨期長4.不同規格產品不齊全5.抗震性差6.同業調貨（致所有銷售 SITIME 產品的業務）只要您瞭解石英震盪器（有源晶振）使用傳統製造方式上的缺點；您即可以是 SiTime 全矽 MEMS 震盪器系列產品的最佳代言人石英震盪器一般製造的方式及其缺點：(紅色字體為石英產品缺點) 1.一般而言；石英廠商所做的工作為石英切割、與日系廠商購買基座、起振晶片；將石英以及晶片以特殊黏膠結合後至於基座上，並進行填充氮氣密封。
數十道繁複工序；且需要大量人工參與量產製造、品質管理。
絕大部分石英廠商常見或偶見廠內生產控管不良造成之產品污染、密封不良造成漏氣（使頻率偏離規格）等不良現像。
2.不同頻率震盪器；廠商需對石英做不同方式的切割、不同頻率起振的方式也需搭配不同的晶片，支持的電壓不同、或者需要的抖動（jitter）、精度規格不同，震盪器內部搭配的起振晶片均不同所有石英廠商建廠後，除非增加生產線，否則生產產能固定；供貨有限。
所有石英廠無法針對所有規格的震盪器準備生產線或具備生產規模；因此一般而言；個別廠商僅針對某些規格產品生產，造成系統廠商客戶不可能採用”One Stop Shopping”的採購目標。
即使系統廠商目標是縮減同類型產品的供應商，但由於石英產品的特殊性，以及其生產工藝上的限制，廠商的目標如果停留在僅對現有石英供應商之間採購，絕無法達成；而SITIME 的全硅可編程震盪器，從設計、生產上的根本性變革，具備提供廠商 “One Stop Shopping”的條件。
由於不可能為客戶廠商不同需求震盪器備料齊全，石英廠商間普遍存在同業調貨狀況，即不同石英生產廠商透過同一品牌交貨給系統廠商，調貨交貨也意味著品質控管的空窗。
因此一些系統廠商嚴明規定合作石英廠商不得有調貨供貨狀況；以避免此無法控制之品質風險。
SiTime硅晶振样品中心 w SiTime中国区技术支持3.石英產品的頻率精度與溫度關係非線性關係（或稱溫飄；一般為向下拋物線）一般石英產品規格書上標示的頻率穩定度（或精度）；一般為在25℃室溫；除此之外，還有所謂”溫飄”。
SiTime MEMS振荡器代替晶体谐振器的8大理由
SiTime MEMS振荡器代替晶体谐振器的8大理由每个电子系统都需要一个计时装置。
晶体(XTAL) 谐振器通常是首选解决方案。
然而，与XTAL 相比，将谐振器与振荡器IC 配对成一个完整的集成计时器件的振荡器具有多项优势。
MEMS 计时技术进一步扩展了这些优势。
系统设计人员不再需要解决XTAL 的局限性，也不再需要接受使用晶体进行设计的麻烦和风险。
SiTime 即将在一个有源器件中包含一个MEMS 器件和配套IC，如图所示结构可实现、实现、灵活的一个产品，这些产品设计到系统中。
1.即插即用振荡器简化系统设计从表面上看，使用石英晶体的振荡器设计似乎很简单，尤其是考虑到这项技术的成熟度。
但是，在将晶体与振荡器电路匹配时，需要考虑无数的设计参数。
这些参数包括晶体运动阻抗、谐振模式、驱动电平和振荡器负电阻，它是振荡器增益的量度。
此外，必须考虑并联谐振模式晶体的负载电容，它应该考虑PCB 寄生电容和振荡器电路中可能包含的片上集成电容。
必须仔细考虑所有这些参数，以确保电路的可靠启动和运行。
由于振荡器电路需要谐振器与振荡器电路紧密匹配，因此晶体供应商无法保证晶体的启动。
相比之下，振荡器是一个完全集成的解决方案。
振荡器制造商将石英谐振器与振荡器电路相匹配，从而减轻了电路板设计者的负担。
由于消除了匹配错误，SiTime 保证了振荡器的启动。
简而言之，振荡器是一种即插即用的解决方案，可以极大地简化系统设计。
MEMS 振荡器消除了设计问题晶体运动阻抗和振荡器负电阻振荡器电路必须有足够的增益和相移才能满足振荡的巴克豪森准则。
特别重要的是晶体的运动阻抗(ESR) 和振荡器的负电阻（相当于增益）。
如果振荡器的增益不足以克服石英谐振器的运动阻抗，则电路可能无法启动。
使用振荡器可以消除这些问题。
晶体谐振模式、频率调谐电容和片上振荡器电容石英晶体可以在串联或并联谐振模式下谐振，但通常只针对这两种模式中的一种进行校准。
如果针对并联谐振进行校准，则它们需要通常指定的特定负载电容。
SiTime公司介绍
●●●●●●●●●●●●MEMSFirstTM，TempFlat MEMSTM，EpiSealTM，MEMS 技术数字 P LL，TurboCompensationTM，FlexEdgeTM 基于模拟的技术ChornosTMMEMS 设计自动化软件ALL 内部设计的 M EMS 和混合信号 I C 数十年的 M EMS 和模拟专业知识160 名员工--50％的工程师，75％的工程师拥有高级学位荣誉2008-2018 的 M EMS 时序中的＃1（cs＆A 和 Y ole Developpement）2015-2016 电子产品年度产品ECN 影响力决赛入围者 2015-2017ACE 奖入围者 2015-20172015-2016 年度微波和射频产品EDN 热门产品 2014,2016产品和优点●MEMS 振荡器和谐振器-最广泛的产品组合●可编程架构-65种产品种类可生成 200K 零件-更多功能，最短的交货时间●独特的基于 M EMS 的计时产品-最小尺寸（1.5×0.8mm-kHZ 和 M Hz）-最低功率（900 nA typ.-32kHz）-最高性能（±0.1ppm 稳定性，3e-11 ADEV）-最佳可靠性（12 亿平方英尺 M TBF）-最佳的坚固性（50,000 g shock 和 70 g 振动）-最佳质量（2DPPM），终身保修市场大约 60 亿美元的元件市场始终产品为每个电子产品提供心跳2012 年至 2017 年，MEMS 振荡器增长的年复合增长率将超过 65％技术和专业知识SiTime 公司SiTime Corporation为MEMS与模拟半导体公司，专业致力于为全球提供最先进的MEMS全硅振荡器，取代传统石英产品。
SiTime的可配置解决方案协助客户创造产品的市场差异性，让产品具备更高的效能、最小的尺寸、最低功耗及最佳稳定性。
SiTime 产品丰富的功能组合和灵活性可使客户精简其供应链，降低成本。
mems真空硅晶振工作原理
mems真空硅晶振工作原理
MEMS硅晶振工作原理：
1.MEMS硅晶振是采用MEMS技术制造的一种硅晶振，它具有优于石英晶
振的优异固有材料性能。
2.SiTime的MEMS硅晶振采用先进的绝缘硅为底衬工艺进行真空密封，有
效阻止了外界颗粒的进入，可靠性强，使用寿命长。
3.硅晶振包含一个MEMS谐振器和一个升级的可编程模拟振荡电路，真空
密封后采用低成本的塑料封装。
4.在MEMS振荡器领域，SiTime是一个领先的技术公司，它的MEMS谐振
器均采用先进的绝缘硅为底衬工艺进行真空密封，有效阻止了外界颗粒的进入，可靠性强，使用寿命长。
5.MEMS硅晶振以更高的频率稳定性提高了计时精度，从而在扩展的温度
范围内实现V2X和5G通信的更好同步。
总之，MEMS硅晶振工作原理是基于MEMS技术和硅材料的优异性能，通过制造和封装工艺的创新，实现了高频率稳定性、高可靠性和长寿命的特点，适用于各种需要高精度计时和通信的应用场景。
SiT5356数据手册-晶圆电子SiTime硅晶振一级代理商
SiT53561 – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXODescriptionThe SiT5356 is a ±100 ppb precision MEMS Super-TCXO that is fully compliant to Telcordia GR-1244-CORE Stratum 3 oscillator specifications. Engineered for best dynamic performance, the SiT5356 is ideal for high reliability telecom, wireless and networking, industrial, precision GNSS and audio/video applications.L everaging SiTime’s unique DualMEMS™ temperature sensi ng and TurboCompensation™ technolog ies, the SiT5356 delivers the best dynamic performance for timing stability in the presence of environmental stressors due to air flow, temperature perturbation, vibration, shock, and electromagnetic interference. This device also integrates multiple on-chip regulators to filter power supply noise, eliminating the need for a dedicated external LDO.The SiT5356 offers three device configurations that can be ordered using Ordering Codes for:1)TCXO with non-pullable output frequency,2)VCTCXO allowing voltage control of outputfrequency, and3)DCTCXO, enabling digital control of output frequencyusing an I2C interface, pullable to 5 ppt (parts pertrillion) resolution.The SiT5356 can be factory programmed for any combination of frequency, stability, voltage, and pull range. Programmability enables designers to optimize clock configurations while eliminating long lead times and customization costs associated with quartz devices where each frequency is custom built.Refer to Manufacturing Guideline for proper reflow profile and PCB cleaning recommendations to ensure best performance. Features⏹Any frequency from 1 MHz to 60 MHz in 1 Hz steps ⏹Factory programmable options for low lead time⏹Best dynamic stability under airflow, thermal shock▪±100 ppb stability across temperature▪±1 ppb/ C typical frequency slope (ΔF/ΔT)▪3e-11 ADEV at 10 second averaging time⏹-40°C to +105°C operating temperature⏹No activity dips or micro jumps⏹Resistant to shock, vibration and board bending⏹On-chip regulators eliminate the need for external LDOs ⏹Digital frequency pulling (DCTCXO) via I2C▪Digital control of output frequency and pull range ▪Up to ±3200 ppm pull range▪Frequency pull resolution down to 5 ppt⏹ 2.5V, 2.8V, 3.0V and 3.3V supply voltage⏹LVCMOS or clipped sinewave output⏹RoHS and REACH compliant⏹Pb-free, Halogen-free, Antimony-free Applications⏹4G/5G radio, Small cell⏹IEEE1588 boundary and grandmaster clocks⏹Carrier-grade routers and switches⏹Synchronous Ethernet⏹Optical transport – SONET/SDH, OTN, Stratum 3⏹DOCSIS 3.x remote PHY⏹GPS disciplined oscillators⏹Precision GNSS systems⏹Test and measurementBlock DiagramFigure 1. SiT5356 Block Diagram 5.0 x 3.2 mm2 Package PinoutOE / VC / NC12345678910SCL / NCNCGNDNCNCVDDCLKA0 / NCSDA / NCFigure 2. Pin Assignments (Top view) (Refer to Table 13for Pin Descriptions)Ordering InformationThe following part number guide is for reference only. To customize and build an exact part number, use theSiTime Part Number Generator. To validate the part number, use the SiTime Part Number Decoder.Notes:1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time optionsfor best EMI.2. Bulk is available for sampling onlyTABLE OF CONTENTSDescription (1)Features (1)Applications (1)Block Diagram (1)5.0 x 3.2 mm2 Package Pinout (1)Ordering Information (2)Electrical Characteristics (4)Device Configurations and Pin-outs (10)Pin-out Top Views (10)Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs (11)Waveforms (13)Timing Diagrams (14)Typical Performance Plots (15)Architecture Overview (19)Frequency Stability (19)Output Frequency and Format (19)Output Frequency Tuning (19)Pin 1 Configuration (OE, VC, or NC) (20)Device Configurations (20)TCXO Configuration (20)VCTCXO Configuration (21)DCTCXO Configuration (22)VCTCXO-Specific Design Considerations (23)Linearity (23)Control Voltage Bandwidth (23)FV Characteristic Slope K V (23)Pull Range, Absolute Pull Range (24)DCTCXO-Specific Design Considerations (25)Pull Range and Absolute Pull Range (25)Output Frequency (26)I2C Control Registers (28)Register Descriptions (28)Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) (28)Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) (29)Register Address: 0x02. DIGITAL PULL RANGE CONTROL[14] (30)Serial Interface Configuration Description (31)Serial Signal Format (31)Parallel Signal Format (32)Parallel Data Format (32)I2C Timing Specification (34)I2C Device Address Modes (35)Schematic Example (36)Dimensions and Patterns (37)Layout Guidelines (38)Manufacturing Guidelines (38)Electrical CharacteristicsAll Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and 3.3V Vdd.Table 1. Output CharacteristicsTable 1. Output Characteristics (continued)Table 2. DC CharacteristicsTable 3. Input CharacteristicsNote:3. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 17 for APR with respect to other pull range options.Table 5. Jitter & Phase Noise – Clipped Sinewave, -40 to 85 °CTable 7. Jitter & Phase Noise – Clipped Sinewave, -40 to 105 °CTable 8. Absolute Maximum LimitsAttempted operation outside the absolute maximum ratings may cause permanent damage to the part.Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.Note:4. Exceeding this temperature for an extended period of time may damage the device.Table 9. Thermal Considerations[5]Note:5. Measured in still air.Table 10. Maximum Operating Junction Temperature[6]Note:6. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.Table 11. Environmental ComplianceDevice Configurations and Pin-outsTable 12. Device ConfigurationsPin-out Top ViewsOE/NC12345678910NC NC GNDNC NC VDD CLKNCNCFigure 3. TCXOVC 12345678910NC NC GNDNC NC VDD CLKNCNCFigure 4. VCTCXOOE / NC 12345678910 SCL NC GNDNC NC VDD CLKA0 / NCSDAFigure 5. DCTCXOTable 13. Pin DescriptionNotes:7. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.8. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between Vdd and GND. The 0.1 μF capacitor is recommended to place close to the device, and place the 10 μF capacitor less than 2 inches away.9. All NC pins can be left floating and do not need to be soldered down.Test Circuit Diagrams for LVCMOS and Clipped Sinewave OutputsFigure 6. LVCMOS Test Circuit (OE Function)Figure 7. Clipped Sinewave Test Circuit (OE Function)for AC and DC MeasurementsVC FunctionFigure 8. LVCMOS Test Circuit (VC Function)VC FunctionFigure 9. Clipped Sinewave Test Circuit (VC Function)for AC and DC MeasurementsNC FunctionFigure 10. LVCMOS Test Circuit (NC Function)NC FunctionFigure 11. Clipped Sinewave Test Circuit (NC Function)for AC and DC MeasurementsTest Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs (continued)FunctionFigure 12. LVCMOS Test Circuit (I2C Control), DCTCXO modeFunction2C Control), DCTCXO mode for AC and DC MeasurementsFigure 13. Clipped Sinewave Test Circuit (IFigure 14. Clipped Sinewave Test Circuit for Phase Noise Measurements, Applies to All Configurations(NC Function shown for example only)Note:10.SDA is open-drain and may require pull-up resistor if not present in I2C test setup.Waveforms90 % Vdd 50 % Vdd10 % VddFigure 15. LVCMOS Waveform Diagram[11]Figure 16. Clipped Sinewave Waveform Diagram[11]Note:11.Duty Cycle is computed as Duty Cycle = TH/Period.Timing DiagramsVdd Pin CLK OutputT_start: Time to start from power-offFigure 17. Startup Timing T_oe: Time to re-enable the clock outputFigure 18. OE Enable Timing (OE Mode Only)Typical Performance PlotsFigure 19. ADEV (±0.1 ppm)Figure 20. TDEV (0.1 Hz loop bandwidth, ±0.1 ppm)Figure 21. MTIE (0.1 Hz loop bandwidth, ±0.1 ppm)Figure 22. Frequency vs Temperature (±0.1 ppm), 105°CFigure 23. Freq. vs. Temp. Slope (ΔF/ΔT), ±0.1 ppm deviceFigure 24. VCTCXO frequency pull characteristicFigure 25. 1-day aging rate (to 62 days), ±0.1 ppm deviceFigure 26. Drift over 30 days relative to the first readingTypical Performance Plots (continued)Figure 27. Load sensitivity (±0.1 ppm )Figure 28. VDD sensitivity (±0.1 ppm)Figure 31. IDD TCXO (LVCMOS)Figure 32. IDD VCTCXO (LVCMOS)Figure 33. T_phj, RMS Random, (DC)TCXO (LVCMOS)Figure 34. Period Jitter, RMS (LVCMOS)Figure 35. IDD DCTCXO (LVCMOS)Figure 36. T_phj, RMS Random, VCTCXO (LVCMOS)Figure 37. DCTCXO frequency pull characteristicFigure 38. Rise Time (Clipped Sinewave)Figure 39. IDD TCXO (Clipped Sinewave)Figure 40. IDD VCTCXO (Clipped Sinewave)Figure 41. T_phj, RMS Random, (DC)TCXO (Clipped Sine)Figure 42. IDD DCTCXO (Clipped Sinewave)Figure 43. T_phj, RMS Random, VCTCXO (Clipped Sine)Figure 44. Duty Cycle (Clipped Sinewave)Architecture OverviewBased on SiTime’s innovative Elite Platform™, the SiT5356 delivers exceptional dynamic performance, i.e. resilience to environmental stressors such as shock, vibration, and fast temperature transients. Underpinning the Elite platform are SiTime’s unique DualMEMS™temperature sensing architecture and TurboCompensation™ technologies. DualMEMS is a noiseless temperature compensation scheme. It consists of two MEMS resonators fabricated on the same die substrate. The TempFlat™resonator is designed with a flat frequency characteristic over temperature whereas the temperature sensing resonator is by design sensitive to temperature changes. The ratio of frequencies between these two resonators provides an accurate reading of the resonator temperature with 20 µK resolution.By placing the two MEMS resonators on the same die, this temperature sensing scheme eliminates any thermal lag and gradients between resonator and temperature sensor, thereby overcoming an inherent weakness of legacy quartz TCXOs.The DualMEMS temperature sensor drives a state-of-the-art CMOS temperature compensation circuit. The TurboCompensation design, with >100 Hz compensation bandwidth, achieves a dynamic frequency stability that is far superior to any quartz TCXO. The digital temperature compensation enables additional optimization of frequency stability and frequency slope over temperature within any chosen temperature range for a given system design.Figure 45. Elite ArchitectureThe Elite platform also incorporates a high resolution, low noise frequency synthesizer along with the industry standard I2C bus. This unique combination enables system designers to digitally control the output frequency in steps as low as 5 ppt and over a wide range up to ±3200 ppm. For more information regarding the Elite platform and its benefits please visit:⏹SiTime's breakthroughs section⏹TechPaper:DualMEMS Temperature Sensing Technology ⏹TechPaper:DualMEMS Resonator TDC Functional OverviewThe SiT5356 is designed for maximum flexibility with an array of factory programmable options, enabling system designers to configure this precision device for optimal performance in a given application.Frequency StabilityThe SiT5356 comes in two factory-trimmed stability grades that are optimized for different applications. Both Stratum 3+ and Stratum 3 devices are compliant with Stratum 3 stability of ±4.6 ppm over 20 years.Table 14. Stability Grades vs. Ordering Codes⏹Stratum 3+ grade with ΔF/ΔT of ±3.5 ppb/︒C isengineered to provide significantly better performancethan legacy quartz TCXOs in time and phasesynchronization applications such as IEEE1588, smallcells, and 5G C-RAN (cloud RAN).⏹Stratum 3 grade is designed to replace classicStratum 3 TCXOs in applications such as SyncE withbetter dynamic performance and shorter lead time. Output Frequency and FormatThe SiT5356 can be factory programmed for an outputfrequency without sacrificing lead time or incurring an upfront customization cost typically associated with custom-frequency quartz TCXOs.The device supports both LVCMOS and clipped sinewave output. Ordering codes for the output format are shown below: Table 15. Output Formats vs. Ordering CodesOutput Frequency TuningIn addition to the non-pullable TCXO, the SiT5356 can also support output frequency tuning through either an analog control voltage (VCTCXO), or I2C interface (DCTCXO). The I2C interface enables 16 factory programmed pull-range options from ±6.25 ppm to ±3200 ppm. The pull range can also be reprogrammed via I2C to any supported pull-range value.Refer to Device Configuration section for details.Pin 1 Configuration (OE, VC, or NC)Pin 1 of the SiT5356 can be factory programmed to support three modes: Output Enable (OE), Voltage Control (VC), or No Connect (NC).Table 16. Pin Configuration OptionsWhen pin 1 is configured as OE pin, the device output is guaranteed to operate in one of the following two states:⏹Clock output with the frequency specified in the partnumber when Pin 1 is pulled to logic high⏹Hi-Z mode with weak pull down when pin 1 is pulled tologic low.When pin 1 is configured as NC, the device is guaranteed to output the frequency specified in the part number at all times, regardless of the logic level on pin 1.In the VCTCXO configuration, the user can fine-tune the output frequency from the nominal frequency specified in the part number by varying the pin 1 voltage. The guaranteed allowable variation of the output frequency is specified as pull range. A VCTCXO part number must contain a valid pull-range ordering code. Device ConfigurationsThe SiT5356 supports 3 device configurations –TCXO,VCTCXO, and DCTCXO. The TCXO and VCTCXO options are directly compatible with the quartz TCXO and VCTCXO. The DCTCXO configuration provides performance enhancement by eliminating VCTCXO’s sensitivity to control voltage noise with an I2C digital interface for frequency tuning.Figure 46. Block Diagram – TCXOTCXO ConfigurationThe TCXO configuration generates a fixed frequency output, as shown in Figure 46. The frequency is specified by the user in the frequency field of the device ordering code and then factory programmed. Other factory programmable options include supply voltage, output types (LVCMOS or clipped sinewave), and pin 1 functionality (OE or NC).Refer to the Ordering Information section at the end of the datasheet for a list of all ordering options.A VCTCXO, shown in Figure 47, is a frequency control device whose output frequency is an approximately linear function of control voltage applied to the voltage control pin. VCTCXOs have a number of use cases including the VCO portion of a jitter attenuation/jitter cleaner PLL Loop.The SiT5356 achieves a 10x better pull range linearity of <0.5% via a high-resolution fractional PLL compared with 5% to 10% typical of quartz VCTCXOs that rely on pulling a resonator. By contrast, quartz-based VCTCXOs change output frequency by varying the capacitive load of a crystal resonator using varactor diodes, which results in poor linearity.Figure 47. Block Diagram – VCTCXO Note that the output frequency of the VCTCXO is proportional to the analog control voltage applied to pin 1. Because this control signal is analog and directly controls the output frequency, care must be taken to minimize noise on this pin.The nominal output frequency is factory programmed per the customer’s request to 6 digits of precision and is defined as the output frequency when the control voltage equals Vdd/2. The maximum output frequency variation from this nominal value is set by the pull range, which is also factory programmed to the customer’s desired value and specified by the ordering code. The Ordering Information section shows all ordering options and associated ordering codes. Refer to VCTCXO-Specific Design Considerations for more information on critical VCTCXO parameters including pull range linearity, absolute pull range,control voltage bandwidth, and Kv.The SiT5356 offers digital control of the output frequency, as shown in Figure 48. The output frequency is controlled by writing frequency control words over the I2C interface. There are several advantages of DCTCXOs relative to VCTCXOs:1)Frequency control resolution as low as 5 ppt. Thishigh resolution minimizes accumulated time error insynchronization applications.2)Lower system cost – A VCTCXO may need a Digital toAnalog Converter (DAC) to drive the control voltageinput. In a DCTXCO, the frequency control is achieveddigitally by register writes to the control registers viaI2C, thereby eliminating the need for a DAC.3)Better noise immunity –The analog signal used todrive the voltage control pin of a VCTCXO can besensitive to noise, and the trace over which the signalis routed can be susceptible to noise coupling from thesystem. The DCTCXO does not suffer from analognoise coupling since the frequency control isperformed digitally through I2C.Figure 48. Block Diagram4)No frequency-pull non-linearity – The frequency pullingis achieved via fractional feedback divider of the PLL, eliminating any pull non-linearity concerns typical of quartz-based VCTCXOs. This improves dynamic performance in closed-loop applications.5)Programmable wide pull range –The DCTCXOpulling mechanism is via the fractional feedback divider and is therefore not constrained by resonator pullability as in quartz-based solutions. The SiT5356 offers 16 frequency pull-range options from ±6.25ppm to ±3200ppm, providing system designers great flexibility.Refer to DCTCXO-Specific Design Considerations for more information on critical DCTCXO parameters including pull range, absolute pull range, frequency output, and I2Ccontrol registers.VCTCXO-Specific Design ConsiderationsLinearityIn any VCTCXO, there will be some deviation of the frequency-voltage (FV) characteristic from an ideal straight line. Linearity is the ratio of this maximum deviation to the total pull range, expressed as a percentage. Figure 49 below shows the typical pull linearity of a SiTime VCTCXO. The linearity is excellent (1% maximum) relative to most quartz offerings because the frequency pulling is achieved with a PLL rather than varactor diodes.Figure 49. Typical SiTime VCTCXO LinearityControl Voltage BandwidthControl voltage b andwidth, sometimes called “modulation r ate” or “modulation b andwidth”, indicates how fast a VCO can respond to voltage changes at its input. The ratio of the output frequency variation to the input voltage variation, previously denoted by K V, has a low-pass characteristic in most VCTCXOs. The control voltage bandwidth equals the modulating frequency where the output frequency deviation equals 0.707 (e.g. -3 dB) of its DC value, for DC inputs swept in the same voltage range.For example, a part with a ±6.25 ppm pull range and a 0-3V control voltage can be regarded as having an average KV of 4.17 ppm/V (12.5 ppm/3V = 4.17 ppm/V). Applying an input of 1.5V DC ± 0.5V (1.0 V to 2.0V) causes an output frequency change of 4.17 ppm (±2.08 ppm). If the control voltage bandwidth is specified as 10 kHz, the peak-to-peak value of the output frequency change will be reduced to 4.33 ppm/√2 or 2.95 ppm, as the frequency of the control voltage change is increased to 10 kHz.FV Characteristic Slope K VThe slope of the FV characteristic is a critical design parameter in many low bandwidth PLL applications. The slope is the derivative of the FV characteristic –the deviation of frequency divided by the control voltage change needed to produce that frequency deviation, over a small voltage span, as shown below:inoutV VfK∆∆=It is typically expressed in kHz/Volt, MHz/Volt, ppm/Volt, or similar units. This s lope is usually called “K V” based on terminology used in PLL designs.The extreme linear characteristic of the SiTime SiT5356 VCTCXO family means that there is very little K V variation across the whole input voltage range (typically <1%), significantly reducing the design burden on the PLL designer. Figure50below illustrates the typical K V variation.Figure 50. Typical SiTime K V VariationPull Range, Absolute Pull RangePull range (PR) is the amount of frequency deviation that will result from changing the control voltage over its maximum range under nominal conditions.Absolute pull range (APR) is the guaranteed controllable frequency range over all environmental and aging conditions. Effectively, it is the amount of pull range remaining after taking into account frequency stability, tolerances over variables such as temperature, power supply voltage, and aging, i.e.:agingstability F F PR APR --=where stability F is the device frequency stability due to initial tolerance and variations on temperature, power supply, and load.Figure 51 shows a typical SiTime VCTCXO FV characteristic. The FV characteristic varies with conditions, so that the frequency output at a given input voltage can vary by as much as the specified frequency stability of the VCTCXO. For such VCTCXOs, the frequency stability and APR are independent of each other. This allows very wide range of pull options without compromising frequency stability.Figure 51. Typical SiTime VCTCXO FV Characteristic The upper and lower control voltages are the specified limits of the input voltage range as shown in Figure 51 above. Applying voltages beyond the upper and lower voltages do not result in noticeable changes of output frequency. In other words, the FV characteristic of the VCTCXO saturates beyond these voltages. Figures 1 and 2 show these voltages as Lower Control Voltage (VC_L) and Upper Control Voltage (VC_U).Table 17 below shows the pull range and corresponding APR values for each of the frequency vs. temperature ordering options.Table 17. VCTCXO Pull Range, APR Options [12] Typical unless specified otherwise. Pull range (PR) is ±6.25 ppm.Notes:12.APR includes initial tolerance, frequency stability vs. temperature, and the corresponding 20-year aging.DCTCXO-Specific Design ConsiderationsPull Range and Absolute Pull RangePull range and absolute pull range are described in theprevious section. Table 18 below shows the pull range andcorresponding APR values for each of the frequency vs.temperature ordering options.Table 18. APR Options[13]Notes:13.APR includes initial tolerance, frequency stability vs. temperature, and the corresponding 20-year aging.Output FrequencyThe device powers up at the nominal operating frequency and pull range specified by the ordering code. After power-up both pull range and output frequency can be controlled via I2C writes to the respective control registers. The maximum output frequency change is constrained by the pull range limits.The pull range is specified by the value loaded in the digital pull-range control register. The 16 pull range choices are specified in the control register and range from ±6.25ppm to ±3200ppm.Table 19 below shows the frequency resolution versus pull range programmed valueTable 19. Frequency Resolution versus Pull RangeThe ppm frequency offset is specified by the 26 bit DCXO frequency control register in two’s complement format as described in the I2C Register Descriptions. The power up default value is 00000000000000000000000000b which sets the output frequency at its nominal value (0 ppm). To change the output frequency, a frequency control word is written to 0x00[15:0] (Least Significant Word) and 0x01[9:0] (Most Significant Word). The LSW value should be written first followed by the MSW value; the frequency change is initiated after the MSW value is written.Figure 52. Pull Range and Frequency Control WordFigure 52shows how the two’s complement signed value of the frequency control word sets the output frequency within the ppm pull range set by 0x02:[3:0]. This example shows use of the ±200 ppm pull range. Therefore, to set the desired output frequency, one just needs to calculate the fraction of full scale value ppm, con vert to two’s complement binary, and then write these values to the frequency control registers.The following formula generates the control word value: Control word value = RND((225-1) × ppm shift from nominal/pull range), where RND is the rounding function which rounds the number to the nearest whole number. Two examples follow, assuming a ±200 ppm pull range: Example 1:⏹Default Output Frequency = 19.2 MHz⏹Desired Output Frequency = 19.201728 MHz (+90 ppm) 225-1 corresponds to +200 ppm, and the fractional value required for +90 ppm can be calculated as follows.⏹90 ppm / 200 ppm × (225-1) = 15,099,493.95.Rounding to the nearest whole number yields 15,099,494 and converting to two’s complement gives a binary value of 111001100110011001100110, or E66666 in hex.Example 2:⏹Default Output Frequency = 10 MHz⏹Desired Output Frequency = 9.998 MHz (-50 ppm) Following the formula shown above,⏹(-50 ppm / 200 ppm) × (225-1) = -8,388,607.75. Rounding this to the nearest whole number results in-8,388,608.Converting this to two’s complement binary results in 11100000000000000000000000, or 3800000 in hex. To summarize, the procedure for calculating the frequency control word associated with a given ppm offset is as follows:1)Calculate the fraction of the half-pull range needed.For example, if the total pull range is set for ±100 ppmand a +20 ppm shift from the nominal frequency isneeded, this fraction is 20 ppm/100 ppm = 0.22)Multiply this fraction by the full-half scale word value,225-1 = 33,554,431, round to the nearest wholenumber, and convert the result to two’s complementbinary. Following the +20ppm example, this value is0.2 × 33,554,431 = 6,710,886.2 and rounded to6,710,886.3)Write the two’s complement binary value starting withthe Least Significant Word (LSW) 0x00[16:0],followed by the Most Significant Word (MSW),0x01[9:0]. If the user desires that the output remainsenabled while changing the frequency, a 1 must alsobe written to the OE control bit 0x01[10] if the devicehas software OE Control Enabled.It is important to note that the maximum Digital Control update rate is 38 kHz regardless of I2C bus speed.I2C Control RegistersThe SiT5356 enables control of frequency pull range, frequency pull value, and Output Enable via I2C writes to the control registers. Table 20 below shows the register map summary, and detailed register descriptions follow.Table 20. Register Map SummaryRegister DescriptionsRegister Address: 0x00. Digital Frequency Control Least Significant Word (LSW)。
SiTime MEMS硅晶振和石英晶振的冲击和振动性能比较
SiTime MEMS硅晶振和石英晶振的冲击和振动性能比较1简介所有电子产品在其使用寿命期间都会受到冲击和振动。
力的范围可以从口袋或背包中携带的移动消费产品所经历的运动到工业设备或航空航天应用的高振动水平。
即使是建筑物中的固定产品也可能会受到附近风扇或其他设备的振动。
因此，重要的是要考虑电子元件在存在冲击和振动的情况下的性能。
表1 显示了各种环境中的典型加速度水平。
表1. 各种现场应用中的振动冲击和振动会对元件和外壳造成物理损坏，导致PCB 组件中的焊点失效，并降低电子元件的性能。
时钟振荡器容易受到多种不利影响：谐振器损坏、振动引起的相位噪声和抖动增加以及冲击引起的频率尖峰。
石英振荡器中的晶体谐振器是悬臂结构，对振动损坏特别敏感。
由于两个原因，SiTime MEMS 谐振器从根本上来说更加稳健。
首先，它们的质量比石英谐振器小得多，这减少了振动引起的加速度施加到谐振器上的力。
其次，SiTime MEMS 振荡器的专有设计包括以体模式在面内振动的非常坚硬的谐振器结构、固有抗振的几何结构以及最大限度地减少振动频率偏移的振荡器电路设计。
2测试条件由于外力的方向、持续时间和强度可能会有所不同，因此在各种测试条件下测量振荡器的电响应以充分了解其对冲击和振动的敏感性非常重要。
SiTime 评估了振荡器对三种不同振动或冲击模式的响应：(1) 正弦振动(2) 随机振动和(3) 脉冲冲击冲击测试的设备都是市售产品，包括来自SiTime 和竞争对手的基于MEMS 的振荡器，以及来自多家制造商的基于石英的振荡器。
我们包括了带有表面声波(SAW) 晶体谐振器的石英振荡器，众所周知，它在高工作频率下具有低抖动。
表2. 被测振荡器器件；单端部件（蓝色阴影）在26 MHz 下运行，差分部件（绿色阴影）在156.25 MHz 下运行2.1 正弦振动第一个测试测量了对15 Hz 至2 kHz 频率范围内的正弦振动的响应。
正弦振动的周期性特性会产生频率调制，这会在相位噪声频谱中以被振动频率偏移的频率引起杂散。
SiT3808数据手册-晶圆电子SiTime硅晶振一级代理商
Supply Voltage and Current Consumption
VCXO Characteristics ±25, ±50, ±100, ±150, ±200, ±400, ±800, ±1600 1.7 2.4 2.7 3.2 Lower Control Voltage Control Voltage Input Impedance Control Voltage Input Capacitance Linearity Frequency Change Polarity Control Voltage Bandwidth (-3dB) VC_L Z_in C_in Lin – V_BW – – 100 – – – – – – – – 5 0.1 Positive slope 8 – – – – 0.1 – – 1
1 MHz to 80 MHz High Performance MEMS VCXO
The Smart Timing Choice The Smart Timing Choice
SiT3808
Features
Applications
Any frequency between 1 MHz and 80 MHz with 6 decimal places of accuracy 100% pin-to-pin drop-in replacement to quartz-based VCXO Frequency stability as tight as ±10 ppm Widest pull range options from ±25 ppm to ±1600 ppm Industrial or extended commercial temperature range Superior pull range linearity of ≤1%, 10 times better than quartz LVCMOS/LVTTL compatible output Four industry-standard packages: 2.5 mm x 2.0 mm (4-pin), 3.2 mm x 2.5mm (4-pin), 5.0 mm x 3.2 mm (6-pin), 7.0 mm x 5.0 mm (6-pin) Instant samples with Time Machine II and field programmable oscillators RoHS and REACH compliant, Pb-free, Halogen-free and Antimony-free
sit8208,1-80MHZ 超高性能的振荡器
SiT8208是Sitime 基于其MEMS 时脉技术推出的一款可用于网通、通讯领域的硅晶振，支持1-80MHZ 任一频点输出；12K-20MHZ 测试条件下，抖动只有0.61PS ；兼容7050、5032、3225封装，可直接替代石英产品。
MEMS 硅晶振是美国SITIME 公司推出的、专业替代石英的革命性时钟产品，采用MEMS 技术与CMOS 技术相结合的半导体工艺，将传统的石英晶振全面硅化。
可完全替代传统的石英晶振，并从本质上消除了石英晶振的温漂、品质不一致、长期工作不稳定等缺陷；因采用全自动化半导体工艺，及自然界第二大元素----硅（仅次于氧）为原材料，率先将时钟组件产品的交货周期缩短到2-4周，且同比成本下降10%。
● 1-80MHZ 范围任一频点输出； ● 无温漂：-40℃～85℃全温保证； ● 低抖动：低至0.61PS （12K-20MHZ ）；● 工作精度可达±10PPM 、±20PPM 、±25PPM 、±50PPM ； ● 兼容LVCMOS/LVTTL 电平输出 ● 具有标准/使能两种工作模式● 同一频点多种封装：3.2×2.5，5.0×3.2，7.0×5.0mm ● 全硅半导体工艺，10倍于石英的稳定性 ● 2-4周交货周期应用：● 费电子、视频、图像采集、机顶盒、HDTV 、DVR 、扫描仪、打印机、复印机、网络摄像头 ●USB1.1、USB2.0、SATA 、SAS 、光端机、IEEE 1394、以太网、PCI 总线等等电气特性表：工作参数 标识 最小 典型 最大 单位 测试说明输出频率 f 1 - 80 MHZ频率稳定性F_stab-10 - +10 PPM 此处的精度指工作频偏、温度变化、电压变化、负载变化等条件下的综合考量。
-20 - +20 PPM -25 - +25 PPM -50- +50 PPM老化率 Ag -1.0 -+1.0ppM 25℃情况下每年的老化率 工作温度T_use-20 - +70 ℃商规 -40 - +85 ℃ 工规 工作电压 Vdd1.71 1.8 1.89 V2.25 2.5 2.75 V 2.52 2.83.08 V 2.973.33.63V■ 特色，优点和应用 ■ 技术参数■ 产品简介工作参数 标识 最小典型最大单位测试说明工作电流Idd- -- 32 mA 无负载，f=20MHZ 、Vdd=2.5V,2.8V or 3.3V - -- 31 mA 无负载，f=20MHZ 、Vdd=1.8V 静态电流 I_std- -- -- μA ST=GND, Vdd=3.3V, Output is Weakly Pulled Down占空因数 DC 45 50 55 % All Vdd上升/下降时间 Tr,Tf - 1.5 - ns 10%--90% ALL Vdd ,15pF Load 输出高电平 VOH 90% - - Vdd 输出低电平 VOL - - 10% Vdd 输出负载 Ld - - 15 PF输入高电平 VIH 70% - - Vdd Pin 1,OE or ST 输入低电平 VIL - - 30% Vdd Pin 1,OE or ST上电时间 T_osc - 6 10 ms 上电启动时间 恢复时间 T_resume - 3.0 4 ms 休眠到振荡时间周期抖动 T_jitt - 2 - ps f=75MHZ,All Vdd;相位抖动T_phj-0.6-psf=75MHZ ,测试带宽：900Khz to 7.5MHZ, all Vdd.OE 模式：当1脚为高或悬空时，正常输出CLK 信号； 当1脚为低时，输出禁止，呈高阻状态。
SiTime MEMS硅晶振汽车解决方案
Frequency Stability
50
40
Quartz
30
20
10
0
-10
SiT8924/5 & SiT2024/5
-20
-30
-40
-50
-50 -30 -10
10
30
50
70
SiTime is
2.5x Better
90 110 130
Temperature (°C)
dBM
Spread Spectrum
7.0 x 5.0
Output Logic
LVCMOS
Features
8 output drive strength options, Field Programmable
SiT8934 SiT8935
1 to 150 MHz
-40 to +85, -40 to +105, -40 to +125, -55 to +125
Electrical Control Unit (ECU)
±20 ppm over -55 to 125°C, Any frequency from 1 to 150 MHz, Higher reliability >1 B hours MTBF
SiT8924 | SiT9825 Oscillators
Wireless Charger
Short lead time even for custom frequencies,
Flexible capacity for quick ramp up
SiT8924 | SiT2024 | SiT9025 Oscillators
SiTime MEMS硅晶振与石英晶振的区别
晶振，大家并不陌生。
他是名副其实的电路的“心脏”，我们的处理器、存储、模数转换等芯片，都依赖于其输出的精准时钟源信号而工作。
长久以来，我们习惯于石英晶振。
也同时承受着石英晶振的温漂、品质不统一、抗震性差、交货周期长等问题。
而这一切，我们需要从石英的生产制程上说明。
我们先把石英晶振剖开来看一看。
大体上石英晶振分为上盖、基座、导电胶、晶片，如果是有源的话，还需要一颗起振IC。
而这里面石英工厂要做的只是切割石英晶片，购买上盖、基座、导电胶、起振IC，然后组装在一起。
整个过程包括切割、打磨、镀银、组装、测试等，大概需要23步流程，其中包括关键的开盖组装部分，存在高污染的可能。
复杂的流程工艺，而且存在大量的人工参与，所以石英晶振的不良率（DPPM）在百万分之50-150之间（此数字SiTime MEMS硅晶振小于百万分之0.1）。
下面我们来讲一下石英切割。
石英晶片的切割与频点是一一对应的关系，也就是说不同的频点，对应的石英晶片的大小、厚薄都是不一样的。
而且采用不同的切割方式，石英晶片所表现出的高低温特性是不一样的。
比如常用的AT切，可提供相对较好的温度特性，但对机械应力较为敏感（如下图为AT切石英晶片温度特性）。
采用AT切，温度在+27度以上、-10度以下会产生比较大的漂移。
这也是为什么石英晶振都会有温漂这个参数。
而MEMS硅晶振则在全温范围内无温漂问题。
综上，石英晶振最早产生于1920年代，近百年的发展历史，但依然存在如下问题：1、温漂（高低温与常温频率特性漂移）2、品质不一致（半自动化半人工生产，品质与管理有最直接的关系）3、抗震性差4、生产周期长，紧急交付不灵活MEMS 硅晶振正是在此条件下而生。
半导体发展到今天，微电子技术已经得到了长足的发展。
而晶振则是需要机械震动体，（石英晶振之初也是因为其压电效应的机械震动频率稳定性优于RC振荡），所以MEMS技术（微机电技术）的发展也孕育了MEMS硅晶振的半导体化。
SITIME硅晶振SiT8002低抖动振荡器规格书
@VDD = 2.5V ±10%, -40 to 85°C
Parameter Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Operating Current Standby Current Power Up Time
www.yxc.hk
SiT8002
1 to 125 MHz Programmable Oscillator
DC Electrical Specifications
@VDD = 3.3V ±10%, -40 to 85°C
Parameter Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Operating Current Standby Current Power Up Time
@VDD = 1.8V ±5%, -40 to 85°C
Parameter Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Operating Current Standby Current Power Up Time
Condition IOH = -7 mA IOL = 7 mA Pin 1 Pin 1 Output frequency = 65 MHz, 15 pF load Output is weakly pulled down, ST = GND Time from minimum power supply voltage
Condition IOH = -9 mA IOL = 9 mA Pin 1 Pin 1 Output frequency = 65 MHz, 15 pF load Output is weakly pulled down, ST = GND Time from minimum power supply voltage
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
Confidential
7
硅晶振内部框图/温度补偿
Programmable Oscillator
MEMS Resonator
VDD
Oscillator
5MHz
Frac-N PLL
CLK
(1~800MHz)
Prog. frequency Temperature Sensor GND A/D Digital Temperature Compensation
OSC、震盪器、晶振、 有源晶振
長晶
切割 清洗、抛光
披银
測試 校正
封装、黏贴 氮气密封
老化 测试
测试 筛选
打标
卷带封装
自日系起振芯片厂商采购起振芯片以及基座
Confidential
4
石英振荡器与MEMS硅晶振的区别
石英振荡器
• • • 石英切割组合简单三极管电路，易受环境 影响（湿度、温度、震动等） 金属封装，存在气密性问题 人工切割，人工的参与质量不稳定，产能 扩充困难，每一个频点需要不同的晶片
SiTime整合 8 个供应商
Confidential
11
SiTime MEMS时脉产品价值和优势
SiTime可编程 MEMS振荡器
交货期 质量
库存管理及风险
２-4周 全自动生产，质量稳定
只需2-4周存货，节省库存成本
传统固定频率 石英振荡器
８－１6周 人工切割，质量受工人素质影响
进货周期长，需存货不同频点，电压，等
SiTime 全硅 MEMS 时钟方案
可靠性更高、任意频点可编程、成本更低
Confidential
SiTime 概览
• 美国硅谷VC投资Fabless IC创业公司具有业界 唯一量产，Bosch验证成熟的MEMS时脉技术及 最小，最薄的封装（<0.30um) 2007年三季量产，无一客户产品质量问题 高性能可编程MEMS时脉产品支持低抖动，高 频率，展频，低功耗，差分输出，多锁相环 (PLL)、多输出频率等功能 在九大应用领域里(网通,通讯,消费,服务器等） 超过800个客户,1500个计划进行测试或量产 与石英振荡器比较,超短交货期(2周),24小时克 制化样品,10倍的质量稳定性及无温飘的烦恼 业界标准封装，焊接管脚，直接替代石英组件 全球硅机电时钟领导者，年出货超越三千五百 万，并以指数快速增长。
温飘和温度稳定性
产品强度（防震能力）
出色，全温保证（线性）
50,000G
频偏受温度影响较大（二次曲线关系）
2,000 G
频率抖动系数 相噪 封装尺寸 制造优势
< 3ps RMS 近端相造暂时不符合部分射频应用 不受限，2520到7050都有 适合大量、一致性高自动制造 Blue = 超过
Confidential
MEMS硅晶振: • 全硅组件，MEMS谐振器加CMOS芯片，可忍受 恶劣环境（高低温，高湿度，高压） • 高质量，标准Plastic QFN封装，无气密问题 • 标准半导体制成，外包世界著名IC厂（TSMC, Carsem等）全自动生产，质量一致性好！
Confidential
5
石英晶振与硅晶振的工艺流程对比
50
2 3 N D 0 未溫度補償前之純矽諧振器溫度特性 (線性關係）
Nome 5ppm p3v ewCoeff ata 07GClean
40
25 PPM SiTime震荡器 较好的系统设计余量
30
20
± 25ppm
Frequency ppm error
10
0
-10
-20
-30
-40
25 PPM Quartz 石英产品高低温设计余量较差
组件及供应商整合可能性 产品稳定性 最高输出频率
规格弹性
好.通过可编程方式实现 500M hrs MTBF 通过编程达到800MHz
可编程，任意频点，正偏频、负偏频，精 确度，电压等可随时克制
差。多家供应商，料号复杂 20M – 33M hrs MTBF 150MHz以上需filter，制造困难
需专门制造，周期可长达8-12周
• •
• •
• •
Confidential
2
SITIME产品的主要客户
传统石英晶体、晶振的生产工艺流程图
镀膜前把晶片按+/-300ppm分档
镀膜前 8000ppm+/-300ppm
被银后1000ppm+/-300ppm
点胶
微调时加的银层
Crystal、諧振器、晶體、 晶振、無源晶振
起振晶片Bonding
2 – 7ps RMS 依厂商切割方式 封装越小，产品种类越少、质量越不易控制 大量人工 Red = 低于 Black = 平等
12
总结
• SiTime丰富的时序产品组合(高性能, 低功耗，展频，差分输出，多锁相环 (PLL)、多输出频率） 高度可编程设计，给客户提供时序组件及供应商整合之条件 ２周交货期降低库存管理风险，避免缺货风险 24-48小時客制化样品为R&D提供最快，最灵活的服务 低抖动，低温飘, 高可靠性的特点更适合于网通，通讯设备及Serial IO中的应 用 界标准封装，焊接管脚，直接替代石英组件 可为战略性客户以最短的时间提供可治化的产品，以满足客户设计上特殊需 求
Typical OEM AVL
Part Description OSC,24.576 MHz,50ppm,3.3V,MINI OSC,33.333MHz,100ppm,3.3V,MINI OSC 24.576M 50PPM 3.3V 7.5 OSC, 8.192MHz,3.3V,100ppm,7.5X5mm OSC,66.666MHz,50ppm,3.3V,MINI OSC,27MHz,25ppm,3.3V,SMT5x7-5 OSC,40MHz,25ppm,15pF,SMT-5x7-4 OSC,27MHz,25ppm,3.3V,SMT5x7-4 OSC,44MHZ,25PPM,3.0V,SMT OSC,CLOCK,48 MHZ,50PPM,3.2X2.5MM Original Supplier Epson AVX CTS CTS Saronix Pericom Pericom Connor-Winfield Fox Suntsu Original Supplier Part SG-710ECK C31E00 CB3LV-3C CB3LV-3C S1613B S1613A S1613A CWX8131 126LF SOX129 New Supplier SiTime SiTime SiTime SiTime SiTime SiTime SiTime SiTime SiTime SiTime SiTime Part SiT8002 SiT8002 SiT8002 SiT8002 SiT8002 SiT8102 SiT8102 SiT8102 SiT8102 SiT8102
Customer Order
石英震荡器制造工艺流程
6 – 16 weeks
長晶
切割 清洗、抛光
披银
測試 校正
封装、黏贴 氮气密封
老化 测试
测试 筛选
打标
卷带封装
自日系起振芯片厂商采购起振芯片以及基座
SiTime 全硅半导体制造工艺流程 客戶訂單 1週
MEMS 晶元 拋薄 切割 標準SIP 封裝 CMOS 起振 晶元
-40 -30 -20 -10 0 10 20 30 Temperature (C) 40 50 60 70 80 90
-50
-40° C to 85° C
SiTime Confidential – Do Not Distribute
SiTime 高度整合供应商成为可能.......
SiTime以2个MEMS振荡 器替代8 个石英振荡器
I/O
18
Bandgap
& Bias
Non Volatile Memory
PROG
SiTime重要优伙伴用编程器可提供定制化的样品，任意 频点、任意电压、精度都可以在24小时内可提供免费样 品。
Confidential
9
强势：温漂影响小，全溫度範圍频率特性稳定
晶元庫存
SiTime Confidential – Do Not Distribute
1週
打標
測試 編程
卷带封装
拋薄 切割
空白片庫存 7050/5032/3225/2520
6
石英產品製造所伴隨之問題
• • • • • 製造過程複雜、透過量產機制控制品質、良率 不同頻率需研磨不同厚度之石英晶片、或搭配不同起振晶片 同頻率但不同封裝尺寸，需研磨不同石英晶片。 成本依頻段不同以及封裝不同因製造難易度及生產數量而改變。 溫漂（頻率因工作溫度改變而偏移）透過石英晶片研磨的角度、精度來控制。
Confidential
• • • •
• •
13