ChemicalMechanicalPolishing(CMP)Overview[化学机械研磨(CMP)概述](PPT-54)

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ChemicalMechanicalPolishing(CMP)Overview[化学机械研磨(CMP)概述](PPT-54)

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CMP Consumables
• Slurries for oxide (SiO2) polishing – colloidal suspension of silica particles in alkaline medium – hydroxyl ions attack SiO2, causing softening and chemical dissolution (mechanism unverified) – particles range from 10 to 3000 nm, mean size 160 nm – 12% (wt) particles, KOH used to set pH ~11 – other concerns: particle size distribution (scratching), particle shape, particle agglomeration
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CMP Apparatus
Beaudoin, et al.
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
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CMP Basics (cont’d)
• Why do we need CMP? – for precise photolithography for advanced devices – for advanced multilevel metallization processes (Damascene)
– Mechanical action
• polisher rotation and pressure

CMP

Chemical Mechanical Polishing(CMP)This document is intended to introduce the techniques of Chemical Mechanical Polishing (CMP) to the new user so that they may be better prepared to integrate CMP into their process flow. CMP can be used for many different purposes but it is limited in what it can do and what substrates it can handle. If after reading through this document you still have questions regarding what can be done here at the CNF, please contact the staff member in charge of the tool.HistoryIBM invented CMP in the late 80s toallow for more metal layers in the integrated circuits (IC) that they produced. Originally it was called Chemical Mechanical Planarization (CMP) since that was the purpose for which it was created. A typical transistor wiring process flow of the time is shown.After creating the transistors in the silicon, a dielectric (typically silicon oxide) was deposited. The deposited material replicates the step height of the underlying surface and in some cases can actuallyincrease the topology. When the metal is deposited to form the first wiring level, the metal thickness can significant thin over the edges of the feature. This causes a reduction in the wire cross-section and a subsequent increase in the wire resistivity.Additionally, the step height causes problems when trying to do high-resolution lithography. Pushing optical lithography tools to print ever-smaller features requires moving toward high numerical aperture (NA) tools. These tools can print smallerfeatures at the expense of a smaller depth-of-focus (DOF) window. This requires that the surface height of the film they are patterning to be within a narrow range for the image to print accurately. Any topology in the surface makes it difficult to focus the image on both the high and low areas.Other Planarization Techniques To remove step heights in thedielectric, IC companies used a varietyof techniques prior to CMP. Onetechnique was to deposit a siliconoxide layer heavily doped with boronand phosphorus, (Boron-Doped Phosphosilicate Glass-BPSG). This material has a lower melting point than undoped silicon oxide. A hightemperature anneal was performedand the material would reflow slightlyand smooth out the step heights.An alternate strategy was to use a Spinon Glass (SOG) material. This is aliquid silicon oxide organic precursorthat is spun on the wafer in a mannersimilar to photoresist. Being liquid, the material planarizes the surface beforethe solvent is baked off. After it is spun on, the material undergoes a high temperature curing process. Duringthis cure, most of the organicconstituents are driven off and thematerial shrinks to form a type ofsilicon oxide dielectric. The mainissues with this type of process is thatthe quality of the oxide is very poor compared to a thermal oxide, and itdoes not completely remove the stepheight due to differences in the totalfilm shrinkage between thick and thinareas.Many other techniques were utilized aswell but all of them suffered fromvarious drawbacks. The main problemwith even the best techniques was thatthey only achieved local planarization. There was still a height variationbetween areas of the chips that had different pattern densities. This caused depth of focus problems with the lithography steps.CMP PlanarizationCMP improved on the alternate planarization techniques in many ways. The basic process is to deposit the silicon oxide thicker than the final thickness you want and polish the material back until the step heights are removed. This gives you a good flat surface for the next level. In addition, the process can be repeated for every level of wiring that is added.CMP is the only technique that performs global planarization of the wafer. This is absolutely required to increase the number of wiring levels inthe integrated circuits. Prior to CMP, DOF issues due to global planarization problems limited the total number of IC wiring levels to 3 — 4. With CMP, current state of the art IC production is able to achieve 7 — 8 wiring levels. These achievements did not come without any cost. Many companies were hesitant to integrate CMP for several different reasons. One is that the process suffers from defect issues due to scratching of the wafer surface and from problems removing the abrasive particles when the polishing is finished. In addition, early CMPsuffered from being a bit more of an art than a science. The polishing process was not well understood and variations in the material used to perform the polishing caused process shifts that were hard to correct. As the process has matured, many of those issues have been resolved and CMP is now viewed as a more accepted IC processing technology.Damascene CMPAn alternate use for the CMP processwas for creating inlaid metal patterns onthe wafer for the wiring levels. This iscalled a damascene process. It wasused to replace the traditional method ofmaking electrical contacts between theIC wiring levels.Traditionally to contact the source,drain, and gates of the transistors, largesloped holes or vias were etched intothe dielectric, and the wiring metal waspatterned over the hole and allowed tocontact the lower level directly. Themain detractor with this process is theamount of lateral space each contacttook up, preventing high-density packingof the transistors.The tungsten damascene process starts with a fully planarized dielectric surface that is patterned with vertical contact holes. These holes can be made much smaller and spaced tighter than the sloped vias of the previous process. Tungsten (W) is then deposited using a chemical vapor deposition process to produce a uniform coating thickness on all exposed parts of the wafer. In this two phase process, the tungsten precursor (WF6) migrates to the wafer surface where is decomposes into solid tungsten and a volatile by-product. The CVD process grows a crystalline tungsten film that fills the holes from all sides, producing a hole that is completely filled with metal, leaving only a very narrow seam down the middle of the contact hole. Usually a barrier / adhesion layer is put down first (not shown) to reduce electrical resistance to the underlying metal and protect it from the corrosive W CVD chemistry. A CMP process is thenemployed to remove the surface tungsten, leaving behind the filled contact holes. This polishing process is designed to be highly selective in removing the tungsten versus the underlying dielectric. This allows the process to use the dielectric as a stopping layer, improving the process latitude. Finally a metal layer is patterned on top of the filled contacts to complete the circuit. This process is repeated with the oxide planarization step to add each wiring level to an IC.Instead of just being used to pattern vias for connecting two wiring levels, the damascene process can be used with trenches patterned in the dielectric to form the wiring themselves. In this process, a shallow trench is etched in the dielectric in the shape of the desired wire, the metal is deposited on the wafer, and the CMP process selectively removes the material to leave the trench filled. This process is one of the key technologies that has enabled the integration of copper into IC wiring levels. Prior to this, there was no way to easily pattern small copper features since copper cannot be plasma etched. The damascene process is also utilized in the Shallow Trench Isolation (STI) scheme to further permit tighter transistor packing.Dual Damascene CMPIn the dual damascene process, both the wiring level and the interlevel connections are created with a single polishing step. Two patterning steps are used to create features of two different depths. Blanket metal is deposited and a single CMP step is used to create the inlaid structure. This is the current process used by many IC companies to integrate copper into their circuits.Traditional Structure Step 1Step 2Step 3Step 4CMP Pattern Density IssuesCMP is seen by most of thesemiconductor industry as critical forproducing 0.35um devices and smaller,although it does suffer from someproblems that need to be accounted forduring the process integration. Whenpolishing a wafer that has step features,only the top of the features touch thepolishing pad, concentrating the pressureon these contact points. This increasesthe polishing rate above that of a blanketwafer. In addition, it causes nonuniformityin the removal rate across patterns ofdifferent densities due to variations in thepressure distribution across the pattern.This pattern density effect on removal rate can cause problems if you have very dense and very sparse pattern in your design. Some ways to account for this is to create dummy shapes around the sparse pattern to try and match the higher pattern density.The damascene process also suffers fromseveral different issues. One issue is thatthe material being removed usually has afaster etch rate than the material thestructure is inlaid in. This can cause twosimilar problems called plug recess anddishing. Plug recess is where thedamascene structure sits slightly lowerthan the field area due to the fasterremoval rate than the field. Due to themechanical limitation on how much thepad can deform, it is usually notexcessive. In general, higher chemicallyactive slurries will have a higher amountof recess due to the wet etching action of the slurry.Dishing occurs when the polishing pad under the pressure of polishing, is able to deform into the damascene structure and polish it below the field area. The amount of dishing that occurs is related to the polishing pad characteristics, the size of the structure, and the polishing parameters (speed, pressure, temperature).Erosion of the field material can also occur due to the enhanced polishing at the edges of the structures. As the damascene structure gets recessed, the corners of the field area are exposed and erode more rapidly than the unpatterned areas. This affects the local field material polishing rate and can lead to a variation in the field thickness based on the damascene pattern density. The polishing variables can be tuned to reduce this effect but usually at the expense of other parameters (removal rate, uniformity, etc.).GlossaryBack pressure — During the polishing process, the wafer is held in place on the carrier head by the retaining ring without vacuum assistance. During polishing, air may be blown out the holes in the backing plate to affect the uniformity of the removal rate. This blowing of air is generally measured in pounds per square inch (psi). Nominal values for the back pressure are from 0 — 2 psi. If you set the back pressure too high it will blow the wafer out of the pocket.Backing film — a cushioning polymer film attached to the backing plate with a pressure sensitive adhesive. It cushions the wafer during the polishing and compensates for slight flatness variations in the wafer or backing plate. The quality of the backing film is important to prevent uneven polishing.Backing plate — Located in the carrier head, the backing plate is a precision flat stainless steel disk slightly larger than the wafer. It presses against the back of the wafer and transfers the polishing force to the wafer during CMP. Attached to the backing plate between the plate and the wafer is the backing film. There are many small holes in the backing plate to allow the tool to apply vacuum on the back of the wafer to transport it from the load station to the polishing pad. Vacuum is not generally applied during the polishing process.Brushcleaner — a tool used to clean and dry wafers after CMP.Carrier head — Tool fixture that holds the wafer against the polishing pad during the polishing operation. The carrier head is specific for the wafer you are polishing. The CNF has carrier heads for 3, 4, and 6 wafers.CMP — chemical mechanical polishing, or chemical mechanical planarization. Polishing process utilizing both chemical etching and mechanical removal for nanofabrication.Conditioning profile — varying the pad conditioning parameters over the polishing pad to affect the polishing uniformity. The Strasbaugh 6EC breaks the conditioning arm sweep into 10 zones in which you can set both the conditioning down force and dwell time for each zone. This allows you to alter the pad characteristics across the wafer track to make improvements in the removal rate uniformity.Damascene process — CMP process in which a feature is etched in to an already planar film. The features are typically trenches or holes. A second material is then deposited on the wafer filling the feature. The CMP tool is then used to selectively remove the deposited film in the field area, leaving behind the filled feature flush with the planar film.Diamond disk — a metal disk with embedded industrial diamond particles for conditioning the pad.Dishing — the thinning of damascene structures below the field area due to pad deformation. Dishing is related to the structure size, pad hardness, and other polishing parameters. See also recess.Down force — the pressure applied to the wafer during the polishing process. It is expressed in pounds per square inch (psi) with common pressures in CMP being 4 — 10 psi. Below 4 psi the wafer predominantly hydroplanes over the polishing pad and above 10 psi you risk breaking the wafer. The polishing pressure used has a large effect on uniformity and planarization.Dual damascene — combining etched structures of different heights to fabricate both wiring and interconnects in one damascene polishing processErosion — thinning of the field area around damascene structures due to enhanced polishing at the feature edges. The more feature edges you have in a given area, the higher the erosion rate. Erosion issues almost always makes the actual selectivity of a given process lower than that measured on nonpatterned wafers.Extension — the amount that the top surface of the wafer sits above the retaining ring in the carrier head. If the extension is too low, the etch rate will be reduced on the wafer edge and additionally, the retaining ring will wear down. If the extension is too high the wafer will slip out of the pocket and break during the polishing. Usually measured in mils (thousandths of an inch ¯ 25 microns). The opposite of wafer capture.Fixed abrasive pads — pads with the abrasive component embedded into it instead of in the slurry. It is used with a chemical only liquid to perform CMP. Recent development in CMP that supposedly gives excellent selectivity.Microscratching — micro scale scratching caused by debris on the polishing pad, agglomerated slurry particles, and pad defects. These are very hard to prevent from occurring but steps can be taken post polishing to minimize impact.Pad conditioning — surface treatment of the polishing pad to improve removal rate stability. Hard polishing pads will glaze over from use during polishing and the removal rate will decrease over time. Rubbing the polishing pad with a diamond abrasive disk removes this top glazed surface and uncovers fresh pad material for polishing. Proper conditioning parameters can lead to very stable removal rates.Planarization — the removal of surface topology in a nanofabricated strucuture. This was original purpose of the CMP process. Planarization can be either justlocal removal of step heights, called local planarization, or it can also be uniform removal of material across a die, called global planarization. CMP is currentlythe only planarization process that gives global planarization.Polishing pad — a polymer pad that the wafer is rubbed against during the CMP process. It is applied to the polishing table which rotates under the polishing arm. Slurry is dispensed on to the pad and the polishing arm pushes the carrier head against the pad to polish the wafer. Polishing pads are designed with a variety of properties and purposes.Post-CMP cleaning — CMP slurries contain abrasive particles to perform the mechanical removal of the surface material. These abrasive particles must be removed from the wafer surface after polishing to prevent defects. After CMP, the wafers must be kept wet prior to cleaning because once the slurry is allowed to dry on the wafer, it is very hard to get off mechanically. Due to electrostatic attraction forces though, simply rinsing the wafers with water after polishing will remove little if any of those particles. Modern production equipment use wafer brushcleaners to clean and dry the wafers after CMP. These tools use PVA brushes to mechanical wipe the surface of the wafer and remove the abrasive particles. Additionally, they use dilute ammonium hydroxide to reduce the electrostatic attraction of the slurry particles to the wafer surface. It is important for any CMP process to determine how you are going to clean the wafers when you are done.PVA — polyvinylalcohol, a soft spongy hydrophilic polymer material used in post-CMP cleaning to mechanically remove slurry particles.Quill — or Spindle. The motor on the polishing arm that rotates the carrier against the pad. It turns in the same direction as the polishing table.Removal Rate — the average rate at which material is removed from the surface of the wafer. Most often reported with a uniformity value as measured on a unpatterned wafer.Retaining ring — a hard polymer ring on the carrier head that surround the wafer when it is mounted on the carrier head. The top surface of the ring sits above the wafer backing plate by a set amount to form a recessed circular area called the pocket. The depth of the pocket is important for successful polishing.Selectivity — a ratio of removal rates between two different materials for a given CMP process. This is often determined by measuring the average removal rates on blanket film wafers. As an example, for the polysilicon damascene process, the vendor states that the slurry, when used in a specific CMP process, gives a 300:1 selectivity between polysilicon and thermal oxide. The value reported by this method is often much higher than what is achieved on a patterned wafer due to erosion effects.Shallow Trench Isolation (STI) — Device isolation process for CMOS that utilizes CMP to allow for tighter device spacing. First, a silicon oxide and nitride layer is put down on the wafer to protect the surface from CMP damage. The wafer is etched to leave the device areas raised as mesas with a lower trench area surrounding it. An oxide is deposited over the wafer thick enough to fill the trenches above the height of the mesas. An oxide CMP process is then utilizedto remove the oxide over the mesas to expose the active device areas. The silicon nitride layer acts as a stopping layer for the CMP process and protects the silicon from mechanical damage during CMP.Slurry — a mixture of abrasive and chemicals used to perform CMP. It is continuously pumped on the polishing pad during the CMP process. Most slurries remove material through a combination of chemical and mechanical methods so they are generally material specific. A given slurry may be used to polish materials other than the material it was designed for but unwanted results may occur.Spindle — or Quill. The motor on the polishing arm that rotates the carrier against the pad. It turns in the same direction as the polishing table.Surface roughness — a measurement of the surface irregularities. Most often expressed as a root mean square (RMS) value of the height variation in angstroms. A given polishing process will give you a set surface roughness on the small scale, but if measured over large areas it will measure higher due to the microscratching that occurs.Touch up polish — a quick, low removal polishing step optimized for scratch removal and low surface roughness. Utilized after a primary polishing step to improve the surface finish and reduce defect levels. This type of polish was developed due to the high defect levels from the tungsten damascene process. After the tungsten CMP step, an oxide touch up or buff step would be performed to improve the silicon oxide surface qualities.Uniformity — a measurement of how uniform the removal rate is across the wafer. It can be measured many ways but the most common is the standard deviation (SD or _) of the measured removal rate expressed as a percentage of the removal rate. It is also sometimes called a measurement of non-uniformity. Wafer capture — the amount of the wafer that is in the pocket usually expressed as a percentage of the wafer thickness. The opposite of wafer extension.。

2024年化学机械抛光(CMP)技市场规模分析

2024年化学机械抛光（CMP）技市场规模分析简介化学机械抛光（CMP）技术是集机械磨削与化学物质作用于一体的表面处理技术，广泛应用于半导体、光电子、平板显示等行业。

本文将对化学机械抛光技术市场规模进行分析。

市场规模化学机械抛光技术作为半导体制造工艺中不可或缺的一环，在半导体行业中有着巨大的市场规模。

目前，全球化学机械抛光技术市场规模总体呈现稳步增长的趋势。

根据市场研究机构的数据显示，在2019年，全球化学机械抛光技术市场规模达到XX亿美元。

预计到2025年，该市场规模有望增长至XX亿美元，年均复合增长率约为X%。

市场驱动因素1.半导体产业的发展：随着5G、人工智能、物联网等技术的快速发展，对高集成度、高精度、高可靠性的半导体设备需求不断增加，进而推动了化学机械抛光技术的需求。

2.新兴应用领域的崛起：除了传统的半导体行业，化学机械抛光技术在光电子、平板显示、MEMS等领域也得到了广泛应用。

这些新兴领域的发展带动了对化学机械抛光技术的需求增长。

3.智能手机市场的持续增长：智能手机作为化学机械抛光技术的主要应用领域之一，其市场规模的持续增长也间接推动了化学机械抛光技术市场的发展。

市场挑战1.成本压力加大：化学机械抛光技术对设备、耗材以及人力成本的需求较高，随着市场竞争的加剧，企业面临着降低成本的压力。

2.技术创新的需求：随着行业技术的不断进步和应用领域的拓展，市场对更高性能、更高效率、更环保的化学机械抛光技术有着更高的要求。

企业需要进行技术创新，以满足市场需求。

3.市场竞争加剧：随着国内外企业对化学机械抛光技术市场的投入增加，市场竞争日趋激烈。

企业需要提升产品品质和竞争力，以保持市场份额。

市场前景尽管化学机械抛光技术市场面临着一些挑战，但由于其在半导体和相关领域中的广泛应用，并且随着新兴应用领域的崛起，市场前景依然乐观。

未来，化学机械抛光技术将更加注重技术创新，提高抛光效果和效率，降低成本，并且在环保可持续发展方面加强自身。

化学机械研磨後清洗技术简介

第六卷第一期化學機械研磨後清洗技術簡介蔡明蒔國家奈米元件實驗室前言自1997年開始，半導體製程邁進0.5微米元件線幅以下，幾乎所有半導體製造廠開始採用化學機械研磨技術(Chemical Mechanical Polishing, CMP)。

此乃由於愈來愈嚴苛的曝光景深要求，對於曝光區內晶圓表面之起伏輪廓必須借助研磨方式才能獲得全域性平坦化(Global planarity)。

故在多層導線結構製程之IMD介電層平坦化及鎢金屬栓塞(W plugs)之製作，以CMP取代傳統以乾式蝕刻回蝕法，不但可確保晶圓表面之平整度且製程簡化，大幅提昇製程良率。

除了應用在後段導線之製作，CMP亦應用於前段元件隔離之oxide回蝕製程，即淺溝槽隔離(Shallow Trench Isolation, STI)，大幅增加晶圓上元件之可用面積。

當元件線幅小於0.18微米，傳統鋁銅合金導線之RC延遲將大過於元件開關速度，此時較低電阻之銅導線則勢必被採用。

由於銅之電漿乾蝕不易，應用Cu-CMP金屬嵌入式導線之大馬士革製程(Metal Inlaid Damascene Process)則為形成導線製作之主要方式。

CMP製程雖為先進半導體製程之關鍵技術，但在無塵室中卻屬高污染性之製程(dirty process)。

由於製程中必須引入研磨泥漿(slurry)於晶圓表面進行研磨，泥漿中包含約5-10%，30-100奈米之微細研磨粉體(abrasive)，種類包括SiO2、Al2O3、CeO2、ZrO2等。

此外還必須加入化學助劑，有pH緩衝劑如KOH、NH4OH、HNO3或有機酸等；氧化劑如雙氧水、硝酸鐵、碘酸鉀等；亦必須加入界面活性劑(Surfactants)幫助粉體在水溶液中之懸浮穩定性。

故晶圓經過研磨之後，晶圓表面勢必殘留大量之研磨粉體(>10k/wafers)、金屬離子(>1012 atoms/cm2)及其他不純物之污染。

氧化铝cmp化学机械抛光钨

氧化铝cmp化学机械抛光钨以氧化铝CMP化学机械抛光钨引言：氧化铝化学机械抛光（CMP）是一种常用的表面处理技术，它在集成电路制造、半导体封装、光电子器件制造等领域有着广泛的应用。

而钨是一种重要的材料，在电子、光电、航空航天等领域都有着广泛的应用。

本文将介绍氧化铝CMP化学机械抛光钨的原理、过程和应用。

一、氧化铝CMP化学机械抛光原理氧化铝CMP化学机械抛光是一种同时使用化学和机械作用来改变材料表面形貌的技术。

其原理是在研磨液中加入一定的氧化铝颗粒，通过与材料表面的摩擦作用和化学反应，来实现对材料表面的去除和平整。

在氧化铝CMP过程中，研磨液中的氧化铝颗粒通过与钨表面的摩擦作用和化学反应，可以去除钨表面的不平整和杂质，使其达到所需的光洁度和平整度。

二、氧化铝CMP化学机械抛光过程氧化铝CMP化学机械抛光钨的过程可以分为几个关键步骤：1. 研磨液的准备：选择适当的研磨液，其中主要成分是氧化铝颗粒和化学添加剂。

研磨液的配比和pH值的控制对于抛光过程的效果具有重要影响。

2. 研磨头的选择：根据不同的抛光要求和材料特性选择合适的研磨头，以实现对钨表面的去除和平整。

3. 抛光机的设置：根据具体的抛光要求设置合适的抛光参数，如旋转速度、压力和时间等，以控制抛光过程的效果。

4. 抛光过程的控制：在抛光过程中，通过控制研磨液的流量和抛光头的运动轨迹，来实现对钨表面的均匀去除和平整。

5. 清洗和检测：抛光完成后，需要对样品进行清洗和表面检测，以确保抛光效果和质量的要求。

三、氧化铝CMP化学机械抛光钨的应用氧化铝CMP化学机械抛光钨在微电子工艺、集成电路制造和半导体封装等领域有着广泛的应用。

1. 微电子工艺：在微电子工艺中，钨常用作金属导线和电极材料。

通过氧化铝CMP化学机械抛光钨，可以实现对钨表面的平整和去除杂质，提高电子器件的性能和可靠性。

2. 集成电路制造：在集成电路制造中，氧化铝CMP化学机械抛光钨被广泛应用于金属化层的制备。

ILD CMP Process工艺简介

ILD CMP 简介
ILD CMP：(Inter Layer Dielectric,层间介质)CMP，它主要是研磨氧化硅（Oxide)，将Oxide磨到一定的厚度，从而达到平坦化；
ILD CMP 的前一站是长Oxide的CVD/PVD区，后一站是CNT Photo区。
CMP 前
CMP 后
ILD CMP 的机理
2)By APC(Automatic Process Control)：APC系统根据前面跑的wafer的厚度情况，以及当前 wafer的ILD Dep厚度值，自动计算出polish time，APC方法厚度精度控制高，Rework ratio 低，但在使用APC前需要建好ILD Dep前值和后值的量测Recipe；
ILD CMP Polishing System
ILD CMP Polishing System
ILD CMP Polishing System
CMP 作业流程(Mirra-Mesa 机台)
12: FI 的机器手从cassette 中拿出未加工的WAFER并送到WAFER的暂放台。
23: Mirra 的机器手接着把WAFER从暂放台运送到LOADCUP。LOADCUP 是 WAFER 上载与卸载的地方。
1.2 um 0.7 um
0.3 um
M2
1.0 um
IMD
M1 0.5 um
2.2 um M2
M1 0.4 um
Isolation
Why use CMP
没有平坦化情况下的PHOTO
在IC工艺技术发展过程中，遇到了硅片的表面起伏（即不平坦）这个非常严重的问题，它使亚微米光刻无法进行，表面起伏使光刻胶的厚度不均、超出光刻胶的胶深范围，无法实现亚微米线宽的图形转移；

纳米集成电路中镍基cmp工艺

纳米集成电路中镍基cmp工艺纳米集成电路（nanoelectronics）是一种以纳米级尺度制造电子器件的技术。

在纳米集成电路制造过程中，需要使用一种叫做化学机械抛光（Chemical Mechanical Polishing, CMP）的工艺来平整表面并去除不必要的材料。

镍基CMP工艺是CMP工艺的一种变种，主要用于去除铜、钨等金属材料，用于制造互连结构。

下面是一些关于镍基CMP工艺的要点：
CMP过程中使用的化学药剂：镍基CMP过程中使用的化学药剂包括硝酸、氯化铵、氧化铜等。

硝酸和氯化铵用于去除材料表面的氧化物，而氧化铜则可以作为氧化剂帮助去除表面材料。

CMP过程中的机械抛光：镍基CMP过程中的机械抛光主要是通过研磨头进行的。

研磨头表面覆盖有一层聚氨酯泡沫，用于平衡压力并保证研磨头与晶圆表面保持接触。

CMP过程中的控制参数：镍基CMP过程中需要控制的参数包括压力、速度、药剂浓度、PH值等。

这些参数的控制需要结合CMP设备和材料的特性进行优化。

CMP工艺的影响因素：镍基CMP工艺的影响因素包括压力、速度、药剂浓度、PH值、材料的性质、机械抛光的时间等。

这些因素之间存在相互作用，需要进行综合考虑。

总之，镍基CMP工艺是制造纳米集成电路中必不可少的工艺之一。

在镍基CMP过程中，需要控制好化学药剂的配方、机械抛光的参数，以及对材料的影响因素进行综合考虑，以保证制造出高质量的互连结构。

1/ 1。

碳化硅化学机械抛光中材料去除非均匀性研究进展　

第53卷第4期2024年4月人㊀工㊀晶㊀体㊀学㊀报JOURNAL OF SYNTHETIC CRYSTALS Vol.53㊀No.4April,2024碳化硅化学机械抛光中材料去除非均匀性研究进展孙兴汉1,李纪虎2,张㊀伟1,曾群锋2,张俊锋3(1.中电建(西安)港航船舶科技有限公司,西安㊀710100;2.西安交通大学现代设计及转子轴承系统教育部重点实验室,西安㊀710049;3.上海船舶设备研究所,上海㊀200031)摘要:化学机械抛光已经成为半导体制造中关键的工艺步骤之一,该技术是目前实现碳化硅晶片超精密加工的一种常用且有效的方法,可用于加工晶片表面,以获得高材料去除率㊁高表面质量和高表面平整性的晶片㊂然而,在碳化硅晶片化学机械抛光中,晶片表面材料去除非均匀性一直是一个具有挑战性的问题,减小晶片表面材料去除非均匀性对确保半导体器件的高性能和稳定性至关重要㊂本文介绍了碳化硅材料的性质及应用与化学机械抛光工艺,研究了不同碳化硅化学机械抛光技术的材料去除机理㊁不同化学机械抛光技术的发展状况和性能及优缺点,综述了碳化硅晶片化学机械抛光中材料去除非均匀性影响因素,如:抛光压力㊁抛光液(磨粒)和转速等因素,最后对未来碳化硅化学机械抛光中材料去除非均匀性研究做出了展望㊂关键词:碳化硅;化学机械抛光;材料去除;抛光压力;抛光液;抛光垫中图分类号:TG175;TM23;TQ163+.4㊀㊀文献标志码:A ㊀㊀文章编号:1000-985X (2024)04-0585-15Research Progress on Material Removal Non-Uniformity in Silicon Carbide Chemical Mechanical PolishingSUN Xinghan 1,LI Jihu 2,ZHANG Wei 1,ZENG Qunfeng 2,ZHANG Junfeng 3(1.Power China (Xi an)Port Nevigation Shipbuilding Technology Co.,Ltd.,Xi an 710100,China;2.Xi an Jiaotong University Laboratory of Education Ministry for Modern Design and Rotor-Bearing System,Xi an 710049,China;3.Shanghai Marine Equipment Research Institute,Shanghai 200031,China)Abstract :Chemical mechanical polishing (CMP)has become a critical process step in semiconductor manufacturing.This technique is a commonly used and effective method for achieving ultra-precision processing of silicon carbide wafers,playing a key role in the fabrication of semiconductor devices.CMP is employed to process the wafer surface,resulting in high material removal rates,excellent surface quality,and superior surface planarity of the chips.However,in the CMP of silicon carbide (SiC)wafers,the non-uniformity of material removal on the chip surface has been a challenging issue.Reducing the non-uniformity of material removal is essential for ensuring the high performance and stability of semiconductor devices.This article introduces the properties and applications of silicon carbide,along with the CMP process.It investigates the material removal mechanisms of different CMP techniques for silicon carbide,explores the development status of various CMP technologies,and evaluates the performance and pros and cons of different CMP techniques.The article provides an overview of the factors influencing material removal non-uniformity in CMP of silicon carbide wafers,including factors such as polishing pressure,polishing slurry (abrasives),and rotation speed.Finally,the article provides prospects for future research on material removal non-uniformity in silicon carbide CMP.Key words :silicon carbide;chemical mechanical polishing;material removal;polishing pressure;polishing slurry;polishing pad ㊀㊀收稿日期:2023-10-27㊀㊀基金项目:陕西省自然科学基金(2022JM-251)㊀㊀作者简介:孙兴汉(1988 ),男,陕西省人,硕士研究生㊂E-mail:sunxingh@ ㊀㊀通信作者:曾群锋,博士,副教授㊂E-mail:xiaozeng0011@0㊀引㊀㊀言碳化硅单晶作为电力电子器件的新一代衬底材料,表面质量至关重要㊂要求其具有超光滑和超平坦的586㊀综合评述人工晶体学报㊀㊀㊀㊀㊀㊀第53卷表面,以确保单晶衬底表面粗糙度低于0.3nm,从而满足外延薄膜生长的要求[1-2]㊂然而,碳化硅单晶的高硬度和化学惰性造成了在抛光加工中的困难,因此需要寻求更加适用的抛光技术,这对于确保材料的质量和性能至关重要[3-7]㊂化学机械抛光(chemical mechanical polishing,CMP)技术是半导体晶片表面加工的关键技术之一㊂该技术综合了抛光液的化学腐蚀作用和磨粒及抛光垫的机械去除作用,以实现抛光后工件表面的良好质量㊁无损伤和高面形精度[8]㊂在碳化硅晶片的CMP过程中,研究者尽管控制晶片表面各点的速度相同并施加均匀载荷,实验结果却显示晶片下表面各点的材料去除率(material removal rate,MRR)不同㊂MRR随着从晶片中心到边缘的位置变化而变化,且边缘处的MRR较高,容易导致过磨(over-grinding) 现象[9-11],即晶片表面材料去除非均匀性现象㊂在碳化硅晶片CMP过程中,晶片表面材料去除非均匀性受抛光头与抛光盘转速㊁抛光压力㊁抛光垫和抛光液特性等因素,以及这些因素相互作用的影响,这给碳化硅晶片CMP中材料去除非均匀性机理及控制方法等方面的研究带来诸多困难㊂对于材料去除非均匀性的问题,许多学者根据不同的理论和实验,对不同参数下的材料去除非均匀性进行了研究,得出了不同的结论㊂在研究过程中,主要关注抛光压力㊁抛光液㊁相对转速㊁温度和抛光头的摆动参数等因素对非均匀性的影响[12-15]㊂目前,关于材料去除非均匀性形成机制的研究还不够深入,由于涉及多个因素和复杂的相互作用,存在争议和不确定性[16-17]㊂尤其是电力电子器件的发展对CMP技术提出了很高要求,研究碳化硅CMP中材料去除非均匀性对提高碳化硅CMP技术水平有重要理论意义和应用价值[18]㊂因此,进一步深入研究材料去除非均匀性的机制是必要的㊂本文将从碳化硅材料的基本性质㊁微观结构特点,以及与材料去除特性之间的关联关系出发,阐述碳化硅CMP技术和材料去除非均匀性的机理,研究碳化硅CMP中影响材料去除非均匀性的因素,最后对未来碳化硅CMP中材料去除非均匀性的研究方向做出展望㊂1㊀碳化硅的性质与应用碳化硅又称金刚砂,分子式为SiC,每一个C原子周围通过共价键形式连接四个Si原子,每一个Si原子周围通过共价键形式连接四个C原子,即:碳化硅是由诸多CSi4单元和SiC4单元彼此穿插组成的四面体结构,这种四面体结构以共边形式连接形成平面层,通过顶点与下一层的四面体相连形成三维结构㊂这种典型的晶体结构如图1所示,因此,碳化硅优越的力学性能与其自身结构密切相关[19]㊂图1㊀碳化硅结构Fig.1㊀Silicon carbide structure碳化硅的物理性质主要表现在高硬度㊁高耐磨性㊁高导热率等方面,且密度为3.211g/cm3㊁莫氏硬度高达9.5㊁显微硬度在3000~3300kg/mm2,其硬度仅次于金刚石,并且当温度在1500ħ时,碳化硅仍能保持优良的硬度和强度[20]㊂此外,碳化硅还具有出色的热导率(达到4.9W/(K㊃cm))㊁高击穿电场和良好的电学性能㊂因此,它在高频㊁高效㊁高温微电子领域被广泛应用作为大功率元器件㊂同时,碳化硅还具有卓越的抗辐射性能(>103W/cm),使其在人造卫星㊁航空航天和核能等领域得到广泛应用㊂碳化硅的物理性质如㊀第4期孙兴汉等:碳化硅化学机械抛光中材料去除非均匀性研究进展587㊀表1所示㊂表1㊀碳化硅的物理性质[1]Table 1㊀Physical properties of silicon carbide [1]Property Value Band gap /eV 2.3~3.3Density /(g㊃cm -3) 3.211Thermal conductivity /(W㊃K -1㊃cm -1)3~4.9Saturated electron drift rate /(107cm㊃s -1) 2.0Breakdown field /(MV㊃cm-1)0.8~3.0Microhardness /(kg㊃mm -2)3000~3300Mohs hardness 9.5Melting point /ħ2700碳化硅具有出色的化学和热稳定性㊂在常温下,它不与酸㊁碱发生反应,表现出良好的化学稳定性㊂在碱性环境且存在氧化剂的情况下,能够生成可溶性硅酸盐,这为碳化硅CMP 提供了关键的化学反应原理㊂此外,碳化硅还具备良好的热稳定性,当加热到1300ħ时,在空气中形成的二氧化硅保护层能够防止碳化硅继续被氧化㊂在空气中加热到1627ħ时,碳化硅表面的保护膜开始被破坏,达到最高工作温度,因此,工业高温使用时,温度一般控制在1600ħ以下㊂2㊀碳化硅CMP 技术简介CMP 技术是半导体制造过程中实现晶片表面平坦化的关键工艺[17,19],该工艺结合传统纯机械和纯化学抛光方法去除晶片表面微米/纳米级不同材料,从而实现晶片表面的高度(纳米级)平坦化㊂根据不同工艺制程要求,每一片晶片都会历经几道甚至几十道CMP 技术步骤㊂CMP 技术中使用的抛光材料包括抛光液㊁抛光垫和清洁剂等,其中占比最大的是抛光液和抛光垫㊂CMP 工作原理示意图如图2所示㊂在碳化硅晶片CMP 技术中,抛光液起到化学去除的作用,抛光液中的化学成分与碳化硅晶片表面进行化学反应,把晶片损伤表面和表面附着物质通过反应转变成更容易抛光的氧化层;抛光垫起到机械去除的作用[21],抛光垫对碳化硅晶片表面研磨,将软化层抛离抛光表面,并使未反应的晶片表面重新暴露出来,从而保证晶片表面化学作用继续进行,如此反复的氧化成膜-机械去除过程可实现有效抛光的目的,其CMP 反应原理如图3所示㊂图2㊀CMP 工作原理示意图[20]Fig.2㊀Schematic diagram of CMP working principle [20]图3㊀CMP 反应原理示意图[22]Fig.3㊀Schematic diagram of CMP reaction principle [22]3㊀碳化硅CMP 中材料去除机理对于碳化硅晶片而言,采用不同的CMP 技术,其MRR㊁加工后表面质量,以及材料去除机理也不相同[23]㊂该部分将从不同碳化硅CMP 技术的材料去除机理出发,研究碳化硅CMP 中材料去除的非均匀性,为后续研究者提供参考㊂588㊀综合评述人工晶体学报㊀㊀㊀㊀㊀㊀第53卷3.1㊀传统CMP在传统CMP 过程中,化学反应和机械磨削相互作用,共同促进碳化硅材料的去除㊂化学反应使表面材料发生溶解或转化,而机械磨削则通过磨料颗粒的切削和磨损作用去除材料㊂同时,通过合理调节抛光液的成分㊁压力和磨料颗粒的特性,可以实现对碳化硅表面的控制去除,获得所需的表面质量和形貌㊂按照磨料的存在状态,碳化硅的传统CMP 分为游离磨粒抛光和固结磨粒抛光[24]㊂图4㊀游离磨粒抛光示意图[24]Fig.4㊀Schematic diagram of free abrasive polishing [24]游离磨料抛光工艺装置主要由旋转工作台㊁工件承载器及研磨液输送装置三部分组成[24],游离磨粒抛光示意图如图4所示,其原理为:将抛光垫固定在旋转工作台上,使组成的部分进行自旋转,同时通过外部承载器给晶片表面施加正压力,使它们能够进行相对运动㊂在传统游离磨料抛光中,通常采用三体摩擦方式对材料进行去除,即晶片表面㊁抛光垫表面和磨料之间的三体相互作用㊂这种三体摩擦方式是实现抛光和材料去除的核心方法,通过控制这三者之间的相互作用,可以实现表面的加工和改进㊂固结磨粒抛光加工装置与游离磨粒抛光装置类似,区别在于抛光垫,即固结磨粒抛光使用的是固结磨粒研磨抛光垫,同时使用树脂结合剂固结磨粒和去离子水及环保的化学试剂作为抛光液㊂该抛光过程的原理为:利用固结磨粒研磨抛光垫表面露出的磨粒尖端对晶片表面实现材料的有效去除㊂固结磨粒加工技术的核心是固结磨粒研磨抛光垫,其结构图如图5所示㊂图5㊀固结磨粒垫结构图[24]Fig.5㊀Schematic diagram of bonded abrasive pad structure [24]游离磨粒抛光和固结磨粒抛光均属于传统CMP 方式,这两种方式均结合了化学反应和机械力的去除作用,实现碳化硅晶片表面的材料去除,但是在碳化硅晶片上,机械力可能在不同区域施加得不均匀,导致材料去除的非均匀性,且抛光效率低,这些因素使传统CMP 在处理碳化硅时面临更大的挑战㊂3.2㊀等离子辅助抛光(plasma assisted polishing ,PAP )PAP 技术由日本大阪大学的Yamamura 于2010年首次提出[26-27]㊂碳化硅PAP 是一种在传统CMP 过程中引入等离子体辅助作用的技术㊂PAP 的材料去除机理主要涉及等离子体化学反应和机械磨削作用,即:通过化学反应实现晶片表面的无损伤加工,同时结合机械磨削作用对材料进行去除,提高晶片表面材料的去除率㊂PAP 技术结合了离子体化学反应和机械磨削作用两者的优势,不会对晶片亚表面造成损伤㊂碳化硅PAP 的原理为[28]:首先,对碳化硅表面改性,即进行等离子体辐照;其次,具有强氧化性等离子体中的自由基与碳化硅表面的原子发生化学反应,生成较软的改性层;最后,使用软磨料对改性层进行抛光,去除该改性层㊂如此交替进行的过程,使晶片的表面逐渐变平整,最终产生无损伤的晶片平坦表面㊂PAP 技术的原理如图6所示㊂PAP 加工装置由以下两个单元组成:等离子体发生单元㊁材料去除单元㊂其中,等射频电源产生离子体,载气使用惰性气体,使用强氧化性自由基团的气体作为反应气体㊂PAP 加工装置示意图如图7所示㊂㊀第4期孙兴汉等:碳化硅化学机械抛光中材料去除非均匀性研究进展589㊀图6㊀PAP技术原理图[28]Fig.6㊀Schematic diagram of PAP technology principle[28]图7㊀PAP加工装置示意图[28]Fig.7㊀Schematic diagram of PAP processing equipment[28]在PAP碳化硅中,材料去除率不仅受活性自由基及氧化层生成速率较低的影响,还受磨料硬度的影响,因此在PAP碳化硅中要解决以上因素的影响㊂另外,PAP设备价格昂贵,加工费用较高,限制了PAP碳化硅晶片的推广㊂3.3㊀催化剂辅助刻蚀(catalyst-assisted reactive etching,CARE)CARE的材料去除原理为:碳化硅在催化剂的作用下,其表面反应生成硬度较低的氧化层,然后在磨料机械去除的作用下,去除晶片表面的氧化层,最终获得高质量的晶片表面㊂Okamoto等[29]以铂作为催化剂,氢氟酸(HF)或水(H2O)作为刻蚀剂,研究CARE工艺对碳化硅晶片表面材料的去除过程㊂在铂催化剂的作用下,刻蚀剂的分解物与晶片反应生成硬度较低的氧化层,其中氧化层与HF反应生成H2SiF6,以形成新鲜的表面,最终获得高表面质量的晶片㊂该技术不需要添加磨料即可实现晶片表面的加工,但是效率较低㊂其加工装置示意图如图8所示㊂3.4㊀紫外线辅助化学机械抛光(ultraviolet-assisted chemical mechanical polishing,UV-CMP)紫外光催化反应是一种强氧化反应,其原理为:在紫外光的作用下,电子捕捉剂与光催化剂发生光催化反应,生成氧化性较强的活性自由基(㊃OH)㊂其次,活性自由基(㊃OH)与碳化硅的表层发生氧化反应生成硬度较低的SiO2氧化层,然后使用磨料进行机械抛光,去除晶片表面的SiO2氧化层,最终获得高质量的晶片表面㊂叶子凡等[30]选取催化剂作为紫外光的吸收剂,催化剂在紫外光的辐射下发生能级跃迁,产生电子-空穴对,并用氧化剂产生的活性自由基对晶片表面进行改性处理,生成硬度较低的氧化层,最后在磨料的机械去除作用下去除氧化层,以实现高质量的晶片表面㊂同时,提出了紫外CMP抛光模型:他认为紫外系统会对碳化硅晶片表面生成的SiO2氧化层厚度有影响,当加入紫外系统,晶片表面的MRR有很大的提高,其抛光模型如图9所示㊂590㊀综合评述人工晶体学报㊀㊀㊀㊀㊀㊀第53卷图8㊀CARE 加工装置示意图[29]Fig.8㊀Schematic diagram of CARE processing equipment [29]图9㊀UV-CMP 抛光模型[30]Fig.9㊀UV-CMP polishing model [30]在UV-CMP 碳化硅中,引入紫外光可进一步提高晶片表面的氧化速度,促进晶片表面材料的有效去除,但是在操作中很难控制紫外光和催化剂生成活性自由基的速率,从而影响晶片表面材料去除的速率与材料去除的非均匀性㊂3.5㊀基于芬顿反应的化学机械抛光(Fenton reaction-based chemical mechanical polishing ,Fenton-CMP )芬顿反应是法国科学家Fenton 最早发现并提出的,该反应为:二价铁离子(Fe 2+)与过氧化氢(H 2O 2)发生反应,生成羟基自由基(㊃OH),以氧化分解有机物[31-32]㊂基于芬顿反应碳化硅CMP 原理为:用芬顿反应生成的含有游离氧气(O 2)的㊃OH 溶液,对SiC 表面进行氧化处理,使其表面生成硬度较低且结合力小的SiO 2氧化层[33],然后在磨料的机械作用下去除该氧化层,最终获得高质量的晶片表面㊂其化学反应为Fe 2++H 2O 2ңFe 3++OH -+gOH (1)SiC +4gOH +O 2ңSiO 2+2H 2O +CO 2ʏ(2)Fe 3++H 2O 2ңFe 2++H ++gOOH (3)由以上反应可以发现:羟基自由基(㊃OH)是基于芬顿反应碳化硅CMP 的关键,且Fe 2+在反应中仅起催化的作用㊂从式(3)的化学反应可以看出:生成的㊃OH 浓度越高,晶片表面的化学反应速度越快,促使更多的高硬度晶片表面转化为更多软质的SiO 2氧化层,进而促使机械去除过程更容易[34]㊂因此,芬顿反应生成的㊃OH 浓度对晶片表面材料的高效去除至关重要[35]㊂碳化硅Fenton-CMP 技术材料去除过程示意图如图10所示㊂图10㊀碳化硅Fenton-CMP 技术材料去除过程示意图[34]Fig.10㊀Schematic diagram of the material removal process in silicon carbide Fenton-CMP technology [34]在Fenton-CMP 碳化硅中,无法控制羟基自由基(㊃OH)的产生量,且在操作过程中耗时,使晶片表面的氧化效率较低,从而影响晶片表面材料去除的速率与材料去除的非均匀性㊂3.6㊀电化学机械抛光(electrochemical mechanical polishing ,ECMP )ECMP 技术的原理为:利用电化学改性原理促使碳化硅表面的改性层硬度降低,即生成氧化层,然后在氧化铝等磨粒的机械作用下去除该氧化层,最终获得高质量的晶片表面[36]㊂其加工装置示意图如图11所示㊂㊀第4期孙兴汉等:碳化硅化学机械抛光中材料去除非均匀性研究进展591㊀图11㊀电化学机械抛光装置[36]Fig.11㊀Electrochemical mechanical polishing device [36]王磊等[37]使用ECMP 技术对碳化硅晶体的材料去除进行了研究,对比了三种电解液(NaOH㊁NaNO 3和H 3PO 4)对碳化硅晶体的电化学氧化效果,并选择了浓度为0.6mol /L 的NaNO 3作为电解液,同时使用金刚石-氧化铝混合磨粒的机械去除作用对碳化硅晶体进行了表面处理,得到了高质量的晶体表面,混合磨粒的去除机理示意图如图12所示㊂Murata 等[38]开发了一种环保高效的碳化硅ECMP 方法,该方法不需要含有催化性化学物质,并使用由固体聚合物电解质和CeO 2组成的复合垫,实现了约15μm /h 的高MRR,几乎是传统CMP技术获得的碳化硅晶片的10倍㊂在ECMP 碳化硅中,通过外加电场和化学作用使晶片表面氧化层硬度降低,可进一步快速提高晶片表面MRR,同时通过控制电流强度可提高晶片表面精度㊂另外,控制好晶片表面的氧化速率和材料去除率是高效获得光滑表面与解决材料去除非均匀性问题的关键㊂图12㊀混合磨粒去除机理示意图[37]Fig.12㊀Schematic diagram of the hybrid abrasive material removal mechanism [37]3.7㊀化学机械磁流变复合抛光(chemo-mechanical magnetorheological finishing ,CMMRF )碳化硅CMMRF 是一种先进的表面加工技术,可实现对碳化硅材料的高效材料去除㊂通过梁华卓等[39]的研究,碳化硅CMMRF 材料去除机理可总结为:通过使用抛光液与碳化硅表面的改性层发生化学反应,生图13㊀CMMRF 材料去除模型[40]Fig.13㊀CMMRF material removal model [40]成硬度较低的氧化层,然后在磁流变抛光垫和磨粒的机械作用下对氧化层进行去除,以实现晶片表面材料的高效去除㊂同时,他们还发现了磁性粒子电离出来的二价铁与抛光液中的过氧化氢发生芬顿反应[40],生成具有超强氧化性的羟基自由基(㊃OH),然后㊃OH 与晶片表面的改性层发生反应,生成硬度较低的SiO 2层,最终在磨料和磁流变抛光垫的作用下进行机械去除,如此重复的过程可实现高质量的晶片表面㊂碳化硅CMMRF 的材料去除模型如图13所示㊂在CMMRF 碳化硅中,该工艺的磨料为半固着状592㊀综合评述人工晶体学报㊀㊀㊀㊀㊀㊀第53卷态,相比于游离磨料工艺,该工艺材料去除高,但加工过程较复杂,还需进行工艺优化㊂通过以上机理及现状研究,不同CMP技术下碳化硅材料去除非均匀性的研究显示了各种方法的潜在优势㊂其中,ECMP和CMMRF对碳化硅材料的去除率较高,可进一步提高晶片表面材料去除的均匀性,但是CMMRF过程复杂,还需进行工艺优化以提高晶片表面材料去除的均匀性㊂不同CMP技术性能及优缺点如表2所示㊂表2㊀不同化学机械抛光技术性能及优缺点Table2㊀Performance and advantages/disadvantages of different chemical mechanical polishing technologies CMP技术晶片表面质量最大MRR优缺点传统CMP RMS<0.8nm(Si面)Ra<0.1nm<1000nm/h(Si面)表面质量好且加工损伤小,但抛光效率低PAP RMS>0.1nm<200nm/h软磨料将因活性自由基生成的氧化层去除且加工损伤小,但抛光效率最低CARE RMS<0.08nmRa<0.1nm<492nm/h㊃OH直接作用于晶片,不需添加磨料就能实现基晶片加工,但抛光效率低UV-CMP Ra>0.0539nm<400nm/h引入紫外光作用,可实现超精密加工,但受紫外光和催化剂影响且抛光效率低Fenton-CMP Ra>0.0965nm<200nm/h反应设备简单,但反应过程复杂且抛光效率低ECMP Ra>0.23nm<4000nm/h电化学作用且效率高,加工过程可控CMMRF Ra>0.42nm<6000nm/h磨料为半固着状态,突破了游离磨料对晶片的加工,材料去除高,但加工质量还需进行工艺优化综上所述,对于碳化硅晶片而言,不同的CMP技术具有特定的材料去除机理,CMP技术的选择要根据具体的应用情况来定㊂PAP㊁CARE㊁UV-CMP和CMMRF等技术均结合了化学反应和机械去除作用,可实现高质量的晶片表面,同时也可以减少纯机械作用对晶片表面的损伤㊂ECMP技术利用电化学改性和机械磨削相结合,能够实现高效抛光㊂然而,每种技术都有其适用的特定应用场景,选择合适的技术需要考虑加工要求㊁材料特性和设备条件等因素㊂4㊀碳化硅CMP中材料去除非均匀性影响因素分析在碳化硅CMP中,材料去除的非均匀性是指在抛光过程中不同位置或不同晶面的材料去除速率不同㊂通过文献调研,发现影响碳化硅CMP材料去除非均匀性的主要因素有:抛光压力㊁抛光液(磨粒)和转速㊂该部分将综述影响碳化硅CMP材料去除非均匀性的主要因素,分析不同因素对碳化硅晶片表面平整性的影响㊂4.1㊀抛光压力对材料去除非均匀性的影响抛光压力是碳化硅材料去除非均匀性的一个重要因素㊂如果抛光压力不足,可能导致磨料与碳化硅表面之间的接触不充分,减少了磨料对材料的切削作用㊂这会导致材料去除速率不均匀,表现为一些区域的材料去除较慢,而其他区域的材料去除较快㊂非均匀的材料去除可能导致晶片表面粗糙度和平坦度的不一致性㊂与压力不足相反,过大的抛光压力可能会导致磨料对碳化硅表面的切削过度㊂这可能引起表面的过度去除,形成凹陷或坑洞,导致表面不平整和不均匀的去除㊂过大的压力还可能引起磨料的堵塞或过度磨损,进一步影响材料去除的均匀性㊂为了实现材料去除的均匀性,抛光过程中需要实现压力均匀分布㊂压力均匀分布可以确保磨料在整个表面上均匀切削材料,从而获得一致的材料去除速率㊂因此,在碳化硅晶片CMP过程中,适当的抛光压力对实现均匀地材料去除非常重要㊂确保适当的压力水平,并实现均匀的压力分布,有助于获得表面平整度高㊁表面质量一致的抛光结果㊂庞龙飞等[1]基于CMP不同接触状态模型,研究了碳化硅晶片在抛光压力分别为160㊁220㊁280和340g/cm2下Si面的粗糙度,发现抛光后的晶片表面粗糙度会随着抛光压力的增大而变差,并对造成该现象的原因进行了分析:抛光压力的增加导致抛光垫压缩量变大,降低了抛光垫表面储存抛光液的能力,进而导致晶片与上下抛光盘之间的摩擦力增大,同时也导致晶片表面的粗糙度增大,晶片表面材料去除出现不均匀现象㊂晶㊀第4期孙兴汉等:碳化硅化学机械抛光中材料去除非均匀性研究进展593㊀片Si面在不同抛光压力下的粗糙度如图14所示㊂图14㊀不同抛光压力下晶片Si面粗糙度[1]Fig.14㊀Surface roughness of the Si face of chips at different polishing pressures[1]甘琨等[41]将抛光盘和抛光头转速分别固定为30和50r/min,控制抛光液的速率为4.2mL/min,抛光时间为10h,分析抛光后晶片表面粗糙度随抛光头压力变化的影响,也发现晶片表面粗糙度受抛光压力影响;通过实验对比分析,发现抛光压力为200N时,抛光后晶片表面材料去除均匀,且其表面质量最好,抛光压力对晶片表面粗糙度影响如图15所示㊂图15㊀不同抛光压力情况下碳化硅晶片表面粗糙度[41]Fig.15㊀Surface roughness of silicon carbide wafers at different polishing pressures[41]哈尔滨工业大学陈浩[9]通过理论和实验分析了碳化硅CMP后的平整性,其建立的SiC与抛光垫的有限元接触模型如图16所示㊂通过有限元仿真,得出了晶片表面接触应力云图,如图17(a)所示,并对不同压力下晶片表面接触应力进行分析,发现:随着下压力的增加,边缘处的接触应力随之增加,导致晶片边缘区域出现过抛现象,即导致晶片表面出现材料去除非均匀性现象,降低了晶片表面的平整性㊂郭钰等[6]研究了抛光压力和pH值共同作用对晶片表面材料去除的影响,发现抛光压力为200g/cm2㊁pH值为8.5时,抛光压力为300g/cm2㊁pH值为9.5时,抛光压力为400g/cm2㊁pH值为9.5时,晶片表面的材料去除逐渐增大,之后再增加pH值也不能有效提高晶片表面材料的去除率㊂因此,抛光压力越大,需要匹配的抛光液的pH值越高,从而达到更大的去除速率,促使晶片表面材料去除更加均匀㊂。

CMP工艺介绍及用滤芯

CMP工艺介绍及用滤芯Chemical Mechanical Polishing(CMP)化学机械抛光是一个化学腐蚀和机械摩擦的结合。

是目前最为普遍的半导体材料表面平整技术，兼收了机械摩擦和化学腐蚀的优点，从而避免了由单纯机械抛光造成的表面损伤和由单纯化学抛光易造成的抛光速度慢、表面平整度和抛光一致性差等缺点。

可以获得比较完美的晶片表面。

国际上普遍认为，器件特征尺寸在0.35μm以下时，必须进行全局平面化以保证光刻影像传递的精确度和分辨率，而CMP是目前几乎唯一的可以提供全局平面化的技术。

其设备作用原理图如下：CMP耗材主要有以下几种：研磨液：研磨时添加的液体状物质，颗粒大小跟研磨后的刮伤等缺陷有关，颗粒越小越好。

基本形式是由SiO2抛光剂和一个碱性组分水溶液组成，SiO2颗粒的大小1-100nm，浓度1.5%-50%，碱性组成一般是KOH，氨或有机胺，pH为9.5-11，颗粒越大对晶片的损伤越大。

研磨垫：研磨时垫在晶片下面的片状物。

研磨垫整理器：钻石盘状物，整理研磨液。

研磨液过滤系统（Pall家资料）输送流程如下：不同的制程，需要的研磨液可能不同，研磨液的整个传输和应用流程都会用到滤芯进行过滤，主要是对研磨液中的颗粒进行过滤除杂，保证研磨液中颗粒大小的均匀性和稳定性。

半导体制备中常用的CMP制程如下：（1）前段制程中STI-CMP（Shallow trench isolation）电解质隔层，浅沟槽隔离技术，将wafer表面的氧化层磨平，前一站是CVD（化学气相沉积）区，后一站是WET（湿刻）区，抛光后露出SIN（硬质介质材料）。

STI研磨液通常由氧化铈磨料（5％-10％）的固含量。

高固含量（>10％）的气相二氧化硅研磨液也已被用于该制程。

Slurry Type 1.Tote to Day Tank 2.Global Loop 3.Point of Use(POU)Ceria（二氧化铈）Profile II Y002Profile II Y030Profile II Y002(capsule or cartridge)Fumed Silica（气相二氧化硅）CMPure CMPD1.5CMPure CMPD10Starkleen A010(capsule)CMPure CMPD1.5(cartridge)（2）后段制程中应用。

ChemicalMechanicalPolishing(CMP)Overview[化学机械研磨(CMP)概述](PPT-54).

5
CMP Basics (cont’d)
• How does CMP work? – A rotating wafer is pressed face-down against a rotating polishing pad; an aqueous suspension of abrasive (slurry) is pressed against the face of the wafer by the pad.
Beaudoin, et al.
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 10
CMP Consumables (cont’d)
• Slurries for metal (W, Al, Cu) polishing – oxidants cause metal dissolution and passivation (reactions to form protective layer on metal surface) – typically alumina particles (a or g), 100 to 2000 nm in diameter, 12% (wt) particles, pH 3 to 4
• caused by variations in local removal rate
– important parameter is removal rate (RR)
• RR = average thickness change during polishing divided by polishing time

2024年化学机械抛光(CMP)技市场调查报告

2024年化学机械抛光（CMP）技市场调查报告1. 简介化学机械抛光（Chemical Mechanical Polishing，简称CMP）是一种常用于半导体制造过程中的超精密加工技术。

该技术结合了化学溶液和机械摩擦的作用，有效地去除材料表面的微米或纳米级缺陷，以获得高质量的平整表面。

2. 市场规模根据市场调查数据显示，CMP技术在半导体制造行业中有着广泛的应用。

随着半导体行业的发展和需求的增长，CMP市场规模也在不断扩大。

预计到2025年，CMP 技术市场的价值将超过100亿美元。

3. 市场驱动因素CMP技术在半导体行业中的应用越来越广泛，主要得益于以下几个市场驱动因素：3.1 半导体产业的发展随着消费电子产品市场的扩大，半导体产业也得到了快速发展。

半导体元件的制造需要高精度和高质量的表面处理，而CMP技术正是满足这一需求的最佳选择。

3.2 新一代芯片设计新一代芯片的设计越来越复杂，要求更高的制造工艺。

CMP技术能够提供优质的平整表面，有助于实现更高的芯片集成度和性能。

3.3 纳米技术的应用纳米技术的快速发展推动了CMP技术的需求。

纳米级的尺寸要求对制造工艺的精度和控制能力提出了更高的要求，CMP技术在这一领域的优势得到了充分发挥。

4. 市场竞争CMP技术市场竞争激烈，主要供应商包括：•Applied Materials•Cabot Microelectronics Corporation•Ebara Corporation•Dow Chemical Company•3M Company这些公司通过不断的技术创新和产品改进来提高市场份额。

5. 市场前景与机会CMP技术市场前景广阔，未来几年预计将保持稳定增长。

随着新兴技术的发展，如人工智能、物联网和汽车电子等领域的快速增长，CMP技术将得到进一步的推动和应用。

目前，CMP技术仍然存在一些挑战，如成本高、工艺复杂等问题，但随着技术的进步和市场需求的增长，这些挑战也将逐渐得到解决。

化学机械研磨发展历程

化学机械研磨发展历程化学机械研磨，又称CMP（Chemical Mechanical Polishing），是一种同时利用化学反应和机械研磨作用将材料表面平整化的技术。

它广泛应用于半导体制造工艺中，用于制作平坦的晶体硅衬底和集成电路芯片。

化学机械研磨最初是在20世纪80年代末在美国发展起来的。

当时，半导体工业急需一种能够克服化学腐蚀和切割磨损的技术来平整化硅表面。

经过多年的努力，科学家们最终发展出了化学机械研磨的原理和方法。

早期的化学机械研磨主要应用于硅衬底的制备过程。

在这个过程中，硅衬底表面经过了一系列的化学处理，然后被放置在旋转的平坦台上。

硅衬底与搭载研磨液的研磨头接触，并施加适当的力，使硅表面产生切割和化学反应，进而实现表面平整化。

这一方法不仅平整度高，而且可以达到亚纳米级的表面粗糙度。

随着半导体工业的迅速发展，化学机械研磨技术也逐渐得到了进一步的改进和扩展。

在1994年，化学机械研磨技术首次被应用于集成电路的制造过程中。

CMOS（互补金属氧化物半导体）制造工艺中，化学机械研磨被广泛应用于化学气相沉积膜（如氧化层和聚酰亚胺层）和金属膜（如铝或钨）的平整化。

在21世纪的发展中，化学机械研磨技术进一步得到了提升。

一方面，人们对研磨液的配方进行了改进，使其能够在更宽的材料范围内实现高效的研磨效果。

另一方面，不断提高的半导体工艺要求也推动了化学机械研磨技术的进步。

例如，在近年来的芯片制造中，多层金属结构和超低K介电常数薄膜的制备对研磨技术提出了更高的要求。

因此，化学机械研磨技术不断进行改进，以满足不断发展的半导体制造工艺。

化学机械研磨技术的发展不仅在半导体制造工艺中发挥了重要作用，而且在其他领域也得到了应用。

例如，在光学芯片制造和微机电系统（MEMS）制造中，化学机械研磨技术也被广泛采用。

此外，由于其能够兼顾高效性和高精度的特点，化学机械研磨技术在材料科学和工程领域的表面处理和制备过程中也具有广阔的应用前景。

化学机械抛光(CMP)技术、设备及投资概况

责任编辑：毛烁
化学机械抛光（CMP）技术、设备及投资概况
Overview of CMP technology, equipment and investment
作者/李丹赛迪顾问集成电路产业研究中心高级分析师（北京 100048）
摘要：分析了CMP设备技术、设备供应商及投资要点。关键词：CMP；设备；投资
1.2 CMP抛光工艺技术原理 CMP从概念上很简单，但纳米级CMP其实是一项
很复杂的工艺。在晶圆表面堆叠的不同薄膜各自具有不同的硬度，需以不同的速率进行研磨。这可能会导致“凹陷”现象，也就是较软的部分会凹到较硬材料的平面之下。区别于传统的纯机械或纯化学的抛光方法，CMP通过化学的和机械的综合作用，最大程度减少较硬材料与较软材料在材料去除速率上的差异，也有效避免了由单纯机械抛光造成的表面损伤和由单纯化学抛光易造成的抛光速度慢、表面平整度和抛光一致性差等缺点。
2017年11月21日上午，由电科装备45所研发的国产首台200 mm CMP商用机通过了严格的万片马拉松式测试，启程发往中芯国际(天津)公司进行上线验证。这意味着电科装备45所的设备得到了用户的认可，产品从中低端迈向了高端，也标志着电科装备向着实现集成电路核心装备自主可控，担起大国重器的责任迈出了重要的一步。杭州众德是新成立的一家公司，由中电科45所中的CMP技术专家创业建立。 2.5 盛美半导体
荏原在欧洲、日本等全球的研发团队继续推动最先进的应用程序定位于行业生产和新技术要求的前沿。除了MEMS / SOI /磁介质行业的挑战外，荏原的高通量F-REX系列CMP系统正在运行当今最严苛的应用，如用于IC制造的氧化物、ILD、STI、钨和铜。它们具有出色的可靠性，性能超过250小时MTBF。适用于200和300 mm晶圆直径的F-REX200和 F-REX300SII平台分别提供最先进的设计和性能，以满足最先进的器件制造需求。它们提供面向用户的系统配置，旨在实现最大吞吐量和所有干燥/干燥晶圆处理功能。F-REX200工具代表了适用于200 mm晶圆的最新CMP技术（也可用150 mm）。它采用了EB原专利的干进干出晶圆处理技术。清洁模块集成在CMP工具内，从而将干晶片输送到后续工艺中。F-REX200 系统配备2个压板，每个压板1个头和4个清洁站，可选配4个盒式SMIF兼容装载端口和CIM主机通信。其

化学机械研磨（CMP）

芯片黏贴研磨抛光系统( CMP ) 仪器介绍一.目的化学机械研磨是一个移除制程，它借着结合化学反应和机械研磨达到其目的。

并且我们使用它在半导的薄膜体制程中，利用它来剥除薄膜使得表面更加平滑和更加平坦。

它也被用在半导体的金属化制程中，用来移除在其表面大量的金属薄膜以在介电质薄膜中形成联机的栓塞或是金属线。

并且当晶圆从单晶硅晶棒被切下来后，就有很多的制程步骤被用来准备平坦的、光亮的以及无缺陷的晶圆畏面以满足集成电路的制程所需，而化学机械研磨制程通常被用在晶圆生产的最后一道步骤，它可以使晶圆平坦化，并且可以从表面完全消除晶圆锯切步骤所引起的表面缺陷。

当硅单晶棒被锯成薄片，在锯开的过程中在晶圆的两面会留有锯痕，必须除去，晶圆然后放在一抛光板上，用蜡和真空固定住，抛光板再放在抛光机上将晶圆一面磨成像镜子一样，才可以开始进入制作集成电路与组件的制程。

二.实验原理化学机械研磨的原理是将晶圆置在承载体与一表面承载抛光垫的旋转工作台之间，同时浸在含有悬浮磨粒、氧化剂、活化剂的酸性或碱性溶液，晶圆相对于抛光垫运动，在化学蚀刻与磨削两个材料移除机制交互作用下达成平坦化,其结构如下图所示。

CMP研磨機制的概略圖通常，一个化学机械研磨的设备架构，由几个主要部分组成，一是负责研磨晶圆表面的研磨平台，另一部分是负责抓住待磨晶圆的握柄。

其中，握柄是利用抽真空的方式，吸咐待磨晶圆的背面，然后向下压在铺有一层研磨垫的研磨台上，进行平坦化过程。

当CMP进行的时候，研磨平台将会与握柄顺着同一方向旋转，同时，提供研磨过程中化学反应的研磨液将由一条管线，输送到系统中，不断滴在研磨垫上，帮助研磨。

CMP-Lapping磨粒是以悬浮方式添加到硬的盘面，这些磨粒不会被压入或固定在盘面，而是朝向各方向自由自在地滚动，因此这些磨粒会对试片进行敲击作用。

Lapping的运动模式：1.磨粒滚入试片与盘面中间2.磨粒滚动过试片表面并且敲下一块试片材料3.磨粒又再次滚动，没有接触试片表面而滚出Lapping原理與機制示意圖CMP-Polishing将抛光液中的磨粒固定于盘面上，并且利用此种方式，对试片材料进行切削的作用，因而产生屑片。

cmp化学机械抛光极限精度

cmp化学机械抛光极限精度（原创实用版）目录1.化学机械抛光（CMP）简介2.CMP 的极限精度3.CMP 技术的发展前景正文一、化学机械抛光（CMP）简介化学机械抛光（Chemical Mechanical Polishing，简称 CMP）是一种在半导体制造过程中用于平滑和抛光硅片的先进技术。

CMP 技术通过化学腐蚀和机械研磨的共同作用，能够实现对硅片表面的高精度抛光，从而满足集成电路对表面平整度的严苛要求。

二、CMP 的极限精度CMP 技术的极限精度是指该技术能够实现的最高表面平整度。

在实际应用中，CMP 的极限精度受到多种因素的影响，包括抛光液的成分、抛光垫的材质和硬度、抛光过程中产生的热量等。

随着半导体工艺的不断发展，对 CMP 技术的极限精度要求也越来越高。

目前，CMP 技术已经能够实现纳米级别的极限精度，满足了最先进的集成电路制造需求。

然而，随着制程技术的进一步发展，CMP 技术需要继续提高其极限精度，以满足未来半导体产业的发展需求。

三、CMP 技术的发展前景CMP 技术作为半导体制造领域的关键技术之一，其发展前景十分广阔。

未来，CMP 技术将继续向更高精度、更高效率和更环保的方向发展。

首先，随着集成电路制程技术的不断演进，对 CMP 技术的极限精度要求将不断提高。

因此，研究人员需要不断优化抛光液、抛光垫等关键材料，以提高 CMP 技术的极限精度。

其次，CMP 技术的效率也是未来发展的重要方向。

通过改进抛光工艺、提高抛光液的利用率等方式，可以提高 CMP 技术的抛光效率，降低生产成本。

最后，环保是 CMP 技术发展的重要趋势。

在抛光过程中产生的废液、废气等污染物需要得到妥善处理，以减少对环境的影响。

因此，研发更环保的 CMP 技术将成为未来的重要发展方向。

总之，CMP 技术在半导体制造领域具有举足轻重的地位。

Chemical mechanical polishing (CMP) apparatus and

专利名称：Chemical mechanical polishing (CMP)apparatus and CMP method using the same 发明人：Byoung-hun Lee,Joon-hee Lee申请号：US08/805659申请日：19970227公开号：US05837610A公开日：19981117专利内容由知识产权出版社提供摘要：A chemical mechanical polishing (CMP) apparatus for planarizing a semiconductor wafer includes a wafer carrier for loading and fixing a semiconductor wafer to be polished and a polishing platen rotating at a constant speed, disposed at a lower portion of the wafer carrier. A polishing pad is provided on an upper surface of the polishing platen, and is in contact with a surface of the semiconductor wafer. A spiral slurry feed line supplies a slurry solution to the polishing pad. An end of the spiral slurry feed line is provided with a plurality of nozzles and the spiral slurry feed line is connected to a deionized water feed line that is opened or closed by a valve. Accordingly, abrasives are prevented from being precipitated, and the slurry solution is uniformly supplied to the semiconductor wafer, to thereby enhance polishing uniformity.申请人：SAMSUNG ELECTRONICS CO., LTD.代理机构：Jones & Volentine, LP.更多信息请下载全文后查看。

Chemical-mechanical polishing (CMP) slurry and met

专利名称：Chemical-mechanical polishing (CMP) slurryand method of planarizing computermemory disk surfaces发明人：Mingming Fang,Michael R. Ianiro,Don D.Eisenhour申请号：US11447212申请日：20060605公开号：US20060226125A1公开日：20061012专利内容由知识产权出版社提供专利附图：摘要：Compositions and methods for planarizing or polishing a surface, particularly asemiconductor wafer surface. The polishing compositions described herein comprise (a) a liquid carrier; (b) purified clay; and optional additives, such as (c) a chemical accelerator; and (d) a complexing or coupling agent capable of chemically or ionically complexing with, or coupling to, the metal and/or insulating material removed during the polishing process. The complexing or coupling agent carries away the removed metal and/or silicon dioxide insulator particles, during polishing, to prevent the separated particles from returning to the surface from which they were removed. Also disclosed are methods of planarizing or polishing a surface comprising contacting the surface with the compositions.申请人：Mingming Fang,Michael R. Ianiro,Don D. Eisenhour地址：Naperville IL US,Macon GA US,Grayslake IL US国籍：US,US,US更多信息请下载全文后查看。

ChemicalMechanicalPolishing(CMP)Overview[化学机械研磨(CMP)概述](PPT-54)

ChemicalMechanicalPolishing(CMP)Overview[化学机械研磨(CMP)概述](PPT-54)

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ChemicalMechanicalPolishing(CMP)Overview[化学机械研磨(CMP)概述](PPT-54).

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Chemical mechanical polishing (CMP) apparatus and

Chemical-mechanical polishing (CMP) slurry and met

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