《实验二加法器设计 》实验报告

实验二加法器设计实验报告

A B CO CI

S

A B

CO CI

S

A B

CO CI

S

A B

CO CI

S

A3A2A1A0

B3B2B1B0

S3S2S1S0

‘0’

图1 4位全加器电路原理图

给出sy1程序、原理图以及仿真波形图。

一位加法器：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY sy2 IS

PORT (a,b,ci:IN STD_LOGIC;

s,co:OUT STD_LOGIC);

END sy2;

ARCHITECTURE behav of sy2 IS

BEGIN

s<=a XOR b XOR ci;

co<=(a AND b) OR (a AND ci) OR (b AND ci);

END behav;

四位加法器：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY sy1 IS

PORT (a,b,ci:IN STD_LOGIC;

s,co:OUT STD_LOGIC);

END sy1;

ARCHITECTURE behav of sy1 IS

BEGIN

s<=a XOR b XOR ci;

co<=(a AND b) OR (a AND ci) OR (b AND ci); END behav;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY sy3 IS

PORT(an,bn:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

cin:IN STD_LOGIC;

con:OUT STD_LOGIC;

sn:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END sy3;

ARCHITECTURE full1 of sy3 IS

COMPONENT sy1 IS

PORT(a,b,ci:IN STD_LOGIC;

s,co:OUT STD_LOGIC);

END COMPONENT;

SIGNAL u0_co,u1_co,u2_co,u3_co:STD_LOGIC; BEGIN

U0:sy1 PORT MAP(an(0),bn(0),cin,sn(0),u0_co);

U1:sy1 PORT MAP(an(1),bn(1), u0_co,sn(1),u1_co);

U2:sy1 PORT MAP(an(2),bn(2), u1_co,sn(2),u2_co);

U3:sy1 PORT MAP(an(3),bn(3), u2_co,sn(3),u3_co);

Con<=u3_co;

END

full1;