逻辑与计算机设计基础 复习课件 浙江大学

A F1 = A BC + A B C + A B C F1 = AB + AC + BC + A B C F2 = AB + AC + BC F2 = AC + AB + B C PLA programming table C
X X X X X X X X 1 2 3 4 X X X X X
B
Outputs Product Inputs (C) (T) term A B C F1 F2 AB AC BC F1 F2 1 2 3 4 1 1 – 1 – 1 – 1 1 1 1 1 –
ABOUT FINAL EXAM
Final Exam 1. 2. 3. 4. Fill in the blank (20 points, 2pt/per) Multiple Choice (20 points, 2pt/per) Optimization (12 points, 6pt/per) Circuit Analysis (18 points)
Chapter 1
Conversion between number systems
•
Binary number, hexadecimal number
Eg. ( 1101 1111)2 = (DF)16
Decimal 369.3125 189.625 214.625 62407.625 Binary 101110001.0101 10111101.101 11010110.101 1111001111000111.101 Octal 561.24 275.5 326.5 171707.5 Hexadecimal 171.5 BD.A D6.A F3C7.A
Gray Code & ASCII Character Code
Chapter 2
Boolean algebra
• • • •
• • • • • •
Dual of an algebraic expression: OR<->AND, 0’s <-> 1’s DeMorgan’s theorem: (X + Y)’ = X’ Y’ and (XY)’ = X’ + Y’ Identities of Boolean algebra: X+YZ=(X+Y)(X+Z) Consensus theorem: XY+X’Z+YZ = XY+X’Z, (X+Y)(X’+Z)(Y+Z)=(X+Y)(X’+Z)
Conversion between binary number and decimal code
• •
BCD (binary-coded decimal)
Eg. (1001 0101)BCD -> ( 0101 1111)2 -> (5F)16
Parity Bit
100 0001 -> 0100 0001 (with even parity) -> 1100 0001 (with odd parity) How to generate odd parity bit P for any 5-bit binary number D4D3D2D1D0？
Exclusive-OR operator and gates
• Odd function and even function
Use odd function to generate even parity bit Use even function to generate odd parity bit The even function is obtained by replacing the output gate with an XNOR gate. Podd=X⊕Y⊕Z, Peven= Podd’=(X⊕Y⊕Z)’
High-impedance outputs • 3-state buffer (Hi-Z) • Transmission gates
EN 0 1 1
IN X 0 1
OUT Hi-Z 0 1
Chapter 2
Exercises:
• • •
The dual of an algebraic expression is obtained by 1) interchanging OR and AND operations and 2) replacing 1’s by 0’s and 0’s by 1’s. Use DeMorgan's Theorem to complement a function: 1) Interchange AND and OR operators 2).Complement each constant value and literal Four variables odd function has __________ “1” squares in its corresponding K-Map. A. 4 B. 7 C. 8 D. 14 The gate input cost G of function F AB(C D) C ( BD AD) is ____. A. 15 B. 14 C. 13 D. 12 Which of the following logical gates can be used as a controllable inverter? __________. A. AND gate B. XOR gate C. Buffer gate D. OR gate The Essential Prime Implicants in the K-Map given below are ______. A. Y’Z’, XZ’ B. X’Y’, XY C. XY, XZ’ D. Y’Z’, X’Y’ Given below are the waveforms of input A, B and output F of a logic device. Then the device is a ______ gate. A. NAND B. NOR C. XOR D. OR Y
Logic and Computer Design Fundamentals
Course Review
Wang Dong-hui dhwang@ Jan. 2011
Outline About Final Exam Highlights & Exercises
Course Review
Technology mapping
•
How to implement a Boolean function with NAND gates?
X Y
S C
X Y
C S
•
How to implement a Boolean function with a small cell library?
Chapter 3
Chapter 3
Design procedure: specification, formulation, optimization, technology mapping, verification Technology parameters: fan-in, fan-out, noise margin, cost, propagation delay, power dissipation
Delay Model: Transport delay, Inertial delay, rejection time Programmable implementation technologies 0 1 AND gates inputs8 9 2 3 4 5 6 7 Product 1 • ROM, PROM, PAL term
AB B C X Fuse intact
Fuse blown
AC AB
X X
CC B B AA
0 1
Chapter 4
n-to-m-Line Decoder: n m 2n
•
3-to-8-Line decoder
Demultiplexer: Decoder with Enable m-to-n-Line Encoder: n m 2n Multiplexers
2 F1
D7 D6 D5 D4 A2 D3 D2 A1 D1 A0 D0
X X
X
X X
3
I 1=A
4 5 6 F2
X
X X X X
I 2= B
7 8 9 F3
I 3= C
10
F3
F2
F1
F0
I4
11 12
F4
0 1 2 3 4 5 6 7 8 9
Chapter 3
Programmable implementation technologies • PLA
2. Given a Boolean function F(W, X, Y, Z) =
m(4, 6, 7, 8, 12, 15) + d (2, 3, 5, 10, 11)
Optimize F together with the don't-care conditions d using a K-map
Complement of a function Standard forms
Product terms, sum terms, SOP, POS Minterms, Maxterms, SOM, POM Relationship between SOP and SOM? SOM and POM? Karnaugh map (K-map), Prime implicants, essential prime implicants Simplifying in SOP form (with don’t care conditions) Cost criteria: gate input cost