74hc573(细读)

INPUTS
OE LE DN LH L LH H
INTERNAL LATCHES
L H
OUTPUTS
Q0 to Q7 L H
LL l
L
L
LL h
H
H
HL l
L
Z
HL h
H
Z
Notes
1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state
CI CPD
PARAMETER
CONDITIONS
propagation delay Dn to Qn LE to Qn
input capacitance
CL = 15 pF; VCC = 5 V
power dissipation capacitance per latch notes 1 and 2
44 140
175
210 ns 2.0 Fig.8
time OE to Qn
16 28
35
42
4.5
13 24
30
36
6.0
tPHZ/ tPLZ 3-state output disable
55 150
190
225 ns 2.0 Fig.8
time OE to Qn
20 30
38
45
4.5
16 26
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver ICC category: MSI
AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF
TYPICAL
HC
HCT
14
17
15
15
3.5
3.5
26
26
UNIT
ns ns pF pF
Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF; VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V
tPHL/ tPLH propagation delay LE to Qn
47 150
190
225 ns 2.0 Fig.6
17 30
38
45
4.5
14 26
33
38
6.0
50 150
190
225 ns 2.0 Fig.7
18 30
38
45
4.5
14 26
ቤተ መጻሕፍቲ ባይዱ
33
38
6.0
tPZH/ tPZL 3-state output enable
INTEGRATED CIRCUITS
DATA SHEET
数据表
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information逻辑封装信息 • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 逻辑包概述
产品规格 Product specification
Octal D-type transparent latch; 3-state
八进制D型透明锁存器
The “573” consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at
the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes.
74HC/HCT573
PIN DESCRIPTION
PIN NO. 2, 3, 4, 5, 6, 7, 8, 9 11 1 10 19, 18, 17, 16, 15, 14, 13, 12 20
SYMBOL
D0 to D7 LE OE GND Q0 to Q7 VCC
NAME AND FUNCTION data inputs latch enable input (active HIGH) 3-state output enable input (active LOW) ground (0 V) 3-state latch outputs positive supply voltage
• Useful as input or output port for microprocessors/microcomputers
• 3-state non-inverting outputs for bus oriented applications
• Common 3-state output enable input
The 74HC/HCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.
ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
min.
+25 typ.
max.
74HC −40 to +85 min. max.
−40 to +125 min. max.
UNIT
VCC (V)
WAVEFORMS
tPHL/ tPLH propagation delay Dn to Qn
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
Octal D-type transparent latch; 3-state
Product specification
74HC/HCT573
FEATURES 特征
GENERAL DESCRIPTION
• Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
74HC/HCT573
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODES
enable and read register (transparent mode)
latch and read register
latch register and disable outputs
The “573” is functionally identical to the “563” and “373”, but the “563” has inverted outputs and the “373” has a different pin arrangement.
SYMBOL tPHL/ tPLH
tsu
set-up time
Dn to LE
th
hold time
Dn to LE
50 11 10 4 93
53 51 51
65
75
13
15
11
13
5
5
5
5
5
5
ns 2.0 Fig.9 4.5 6.0
ns 2.0 Fig.9 4.5 6.0
December 1990
5
Philips Semiconductors 飞利浦半导体
December 1990
Fig.5 Logic diagram. 4
Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
74HC/HCT573
DC CHARACTERISTICS FOR 74HC
33
38
6.0
tTHL/ tTLH output transition time
14 60
75
90 ns 2.0 Fig.6
5 12
15
18
4.5
4 10
13
15
6.0
tW
enable pulse width
80 14
HIGH
16 5
14 4
100
120
20
24
17
20
ns 2.0 Fig.7 4.5 6.0
When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.
74HC/HCT573 Octal D-type transparent latch; 3-state
Product specification File under Integrated Circuits, IC06
集成电路
December 1990
LE Philips Semiconductors OE非
• Functionally identical to the “563” and “373”
• Output capability: bus driver • ICC category: MSI
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns