数字跑表实验报告(电子科技大学)

数字跑表设计报告学院：物理电子学院学号：2014040206029姓名：刘明哲班级：电子六班一 系统总体设计设计要求设计一个数字秒表，有6个输出显示，分别为百分之一秒、十分之一秒、秒、十秒、分、十分，系统主要由显示译码器、分频器、十进制计数器和六进制计数器组成。

整个秒表还需有一个启动/停止信号和一个复位信号，以便秒表能随意停止及启动。

要求：（1） 秒表计时范围为：1小时；（2） 秒表精度为0.01秒；（3） 具有开始计时、停止计时控制功能，且开始计时、停止计时为一个复用按键；（4） 在正常计时显示过程中，能够在存储按键作用下存储某一计时时间；存储的时间组数为确定值或1至任意值；（5） 在读取按键作用下存储的时间能够回放显示;回放显示时，秒表计时可停止或在后台正常进行；回放显示可手动或自动依次显示；（6） 具有复位功能；（7） 用六位数码管显示时间读数。

系统工作原理数字跑表通过系统将48MHz时钟进行分频得到100Hz的秒表时钟，之后通过对时钟信号进行计数得到具体的跑表显示数值，跑表数值作为显示单元电路的输入，显示单元控制数码管动态扫描显示计数因此，系统主要划分为：分频器，计数器，显示控制，开始\停在使能控制，清零控制，存储读取功能，按键消抖。

原理图如下：二 单元电路设计1. 分频器设计思路：输入信号48MHz，将其48000分频可得1KHz信号，再将1KHz信号10分频可得100Hz信号。

1KHz用于显示LED扫描，100Hz用于计数器时钟。

源程序如下：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity pp isPORT(CLKIN:IN STD_LOGIC;CLKOUT1K:OUT STD_LOGIC;CLKOUT100:OUT STD_LOGIC);end ENTITY pp;architecture Behavioral of pp isSIGNAL CNTER0:INTEGER RANGE 0 TO 23999 :=0;SIGNAL CNTER1:INTEGER RANGE 0 TO 4 :=0;SIGNAL CLKOUT1K_TMP,CLKOUT100_TMP: STD_LOGIC:='0'; beginPROCESS(CLKIN) ISBEGINIF CLKIN'EVENT AND CLKIN ='1' THENIF CNTER0=23999 THENCNTER0 <=0;CLKOUT1K_TMP <= NOT CLKOUT1K_TMP;ELSECNTER0 <= CNTER0 + 1 ;END IF;END IF;END PROCESS;CLKOUT1K <= CLKOUT1K_TMP;PROCESS(CLKOUT1K_TMP) ISBEGINIF CLKOUT1K_TMP'EVENT AND CLKOUT1K_TMP='1' THEN IF CNTER1 =4 THENCNTER1 <=0;CLKOUT100_TMP <= NOT CLKOUT100_TMP;ELSE CNTER1 <= CNTER1 + 1;END IF;END IF;END PROCESS;CLKOUT100<=CLKOUT100_TMP;end Behavioral;2. 计数器以及清零装置实验需要用到2个六进制计数器和4个十进制计数器，并且将六个计数器级联十进制计数器的源程序：library IEEE;use IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity COUNTER isPORT(RST,CLK:IN STD_LOGIC;CARRY_IN:IN STD_LOGIC;CARRY_OUT:OUT STD_LOGIC;COUNT_OUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));end COUNTER;architecture Behavioral of COUNTER isSIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; beginPROCESS(RST,CLK)BEGINIF RST='1' THENCOUNT<="0000";ELSIF CLK'EVENT AND CLK='1' THENIF CARRY_IN='1' THENIF COUNT< "1001" THENCOUNT <= COUNT + 1;ELSECOUNT<="0000";END IF;ELSE NULL;END IF;END IF;END PROCESS;COUNT_OUT<=COUNT;CARRY_OUT<='1' WHEN CARRY_IN='1' AND COUNT="1001"ELSE'0';end Behavioral;仿真结果：六进制计数器的源程序为：library IEEE;use IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity COUNTER2 isPORT(RST,CLK:IN STD_LOGIC;CARRY_IN:IN STD_LOGIC;CARRY_OUT:OUT STD_LOGIC;COUNT_OUT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));end COUNTER2;architecture Behavioral of COUNTER2 isSIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; beginPROCESS(RST,CLK)BEGINIF RST='1' THENCOUNT<="0000";ELSIF CLK'EVENT AND CLK='1' THENIF CARRY_IN='1' THENIF COUNT< "0101" THENCOUNT <= COUNT + 1;ELSECOUNT<="0000";END IF;ELSE NULL;END IF;END IF;END PROCESS;COUNT_OUT<=COUNT;CARRY_OUT<='1' WHEN CARRY_IN='1' AND COUNT="0101"ELSE'0';end Behavioral;仿真结果：级联的源程序如下：entity COUNTER6 isPORT(CSIGNAL:IN STD_LOGIC;CLEAR: IN STD_LOGIC;COUNT_EN:IN STD_LOGIC;RESULT1 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);RESULT2 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);RESULT3 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);RESULT4 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);RESULT5 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);RESULT6 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));end COUNTER6;architecture Behavioral of COUNTER6 isCOMPONENT COUNTER ISPORT(RST,CLK: IN STD_LOGIC;CARRY_IN: IN STD_LOGIC;CARRY_OUT: OUT STD_LOGIC;COUNT_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END COMPONENT COUNTER;COMPONENT COUNTER2 ISPORT(RST,CLK: IN STD_LOGIC;CARRY_IN: IN STD_LOGIC;CARRY_OUT: OUT STD_LOGIC;COUNT_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END COMPONENT COUNTER2;SIGNALCARRY1,CARRY2,CARRY3,CARRY4,CARRY5,CARRY6:STD_LOGIC; beginU1:COUNTER PORT MAP(RST => CLEAR,CLK => CSIGNAL,CARRY_IN => COUNT_EN,CARRY_OUT => CARRY1,COUNT_OUT => RESULT1);U2:COUNTER PORT MAP(RST => CLEAR,CLK => CSIGNAL,CARRY_IN => CARRY1,CARRY_OUT => CARRY2,COUNT_OUT => RESULT2);U3:COUNTER PORT MAP(RST => CLEAR,CLK => CSIGNAL,CARRY_IN => CARRY2,CARRY_OUT => CARRY3,COUNT_OUT => RESULT3);U4:COUNTER2 PORT MAP(RST => CLEAR,CLK => CSIGNAL,CARRY_IN => CARRY3,CARRY_OUT => CARRY4,COUNT_OUT => RESULT4);U5:COUNTER PORT MAP(RST => CLEAR,CLK => CSIGNAL,CARRY_IN => CARRY4,CARRY_OUT => CARRY5,COUNT_OUT => RESULT5);U6:COUNTER2 PORT MAP(RST => CLEAR,CLK => CSIGNAL,CARRY_IN => CARRY5,CARRY_OUT => CARRY6,COUNT_OUT => RESULT6);end Behavioral;3. 使能控制按一下使能控制键，跑表开始计时，再次按下，跑表暂停计时，且计数器使能端高电平有效。