TI 反激变压器设计

26.5W AC/DC Isolated Flyback Converter DesignTASK : 26.5W 9-Outputs AC/DC Isolated Flyback Converter Design SPECIFICATION: Technical Specification on Sept 10, 2008DATE: 15 Sept. 2008Customer Specificationf L 100Hz :=Line frequencyfs 100kHz:=Switching frequencyVo 1 5.0V :=Main output voltage Io 1_max 2A :=Main Nominal load currentVo 215.0V :=Io 2_max 30mA :=Vo 315.0V :=Io 3_max 30mA :=Vo 415.0V :=Io 4_max 0.3A :=Vo 524.0V :=Io 5_max 0.1A :=Vo 618.0V :=Io 6_max 0.12A :=Vo 718.0V :=Io 7_max 0.12A :=Vo 818.0V :=Io 8_max 0.12A :=Vo 918.0V:=Io 9_max 0.12A:=+5V Output ripple voltageVr 100mV:=+5VStep load output ripple voltageΔVo step 150mV :=ΔIo 5V Io 1_max 80⋅%:=+5V Step load current amplitudeη0.70:=Definition Of Symbolsu t ()Φt ():=Unit step functionm Ω103−Ω:=MilliohmMillisecondMicrosecondNanosecondMilliwattsmJ 103−J :=MillijouleμJ 106−J :=MicrojouleNanocoulombMicrometerμo 4π⋅107−⋅H m 1−⋅:=Permeability of free spaceρθ() 1.72410.0042θ20−()+[]106−Ωcm ⋅:=Resistivity of copper at θ degCComponent SummaryPrimary FET - IRFBC30A - 600V, 3.6A, 2.2Ωζirfbc30a 1.7:=Channel resistance elevation factor to 100 degCRon irfbc30a 2.2Ωζirfbc30a ⋅:=Channel resistance at 100 degCQg irfbc30a 23nC :=Total Gate charge at Vgs of 10VVgMiller irfbc30a 5.5V :=Gate Miller plateau from Gate Charge CurveVth irfbc30a 4.5V :=Gate threshold voltageVds irfbc30a 25V :=Vds test voltage for capacitance valueCrss irfbc30a 3.5pF :=Reverse transfer capacitance at Vds of 25VCiss irfbc30a 510pF :=Input capacitanceCoss_eff irfbc30a 70pF:=Effective output capacitanceAmerican Wire Gauge Table FormulaeAWG 1011, 40..:=American wire gauge rangeDiameter of bare copper wireDiameter of wire with heavy insulationBare copper cross section areaResistance per unit length of AWGConverter ParametersConverter period :=Nominal input voltage Vg nom220V:=Minimum input voltage ⋅−Vg min Vg nom120%()=Vg min176V⋅():=Maximum input voltage Vg max Vg nom120%+=Vg max264VP out1Vo1Io1_max⋅:=++Vo3Io3_max⋅⋅Vo2Io2_maxP out2Vo4Io4_max:=+⋅Vo5Io5_max⋅P out3Vo6Io6_max⋅:=+Vo9Io9_max++Vo8Io8_max⋅⋅Vo7Io7_max⋅P out P out1P out2:=+P out3+=P out26.44WInput Capacitor and Minimum Input DC VoltageC in79.32μF=T C 2ms :=Estimated valueD ch T C f L⋅:=D ch 0.2=V MIN 236.45V=Minimum input DC voltageC in 78.322μF =V MAX 373.352V=D max 0.45:=Set maximum duty cycle at minimum input voltageV RO 193.459V=V DS V RO V MAX +:=V DS 566.811V=Check Vds of primary MOSFETPrimary Current Calculation=Ip AVG0.16A=I P0.71A=Ip RMS0.275A=L m 1.499mHPrimary Inductance with Energy Transform Point L m 1.499mH=Primary Inductance with Core Saturated Point L m1 1.499mH=:=B m1500gauss:=Winding Utilized FactorK W0.15K J 5A ⋅mm2−⋅:=AP 0.635cm4=AP20.52cm4=AP30.492cm 4=AP40.26cm4=Power Transformer - EER28L/PC40 from TDKAe EER35107mm2:=Effective cross section areaAw EER35152.7mm2:=Winding area base on BEER35-1112CPFR standarbobbinAP EER35Ae EER35Aw EER35⋅:=AP EER35 1.634cm4=Wt EER3552g:=Ae EE3589.3mm2:=Effective cross section areaAw EE3588.7mm2:=Winding area base on BEE35-1112CPLFR standar bobbinAP EE35Ae EE35Aw EE35⋅:=AP EE350.792cm4=Wt EE3557g:=Ae EE3283.2mm2:=Effective cross section areaAw EE3288.8mm2:=Winding area base on BEE33-1112CPLFR standar bobbinAP EE32Ae EE32Aw EE32⋅:=AP EE320.739cm4=Wt EE3232g:=Ae EE30109mm2:=Effective cross section areaAw EE3044.5mm2:=Winding area base on BE30-1110CPFR standard bobbinAP EE30Ae EE30Aw EE30⋅:=AP EE300.485cm4=Wt EE3032g:=Ae EER28L 81.4mm2:=Effective cross section areaAw EER28L 96.3mm2:=Winding area base on BEER28L-1110CPFR standa bobbinAP EER28L Ae EER28L Aw EER28L⋅:=AP EER28L 0.784cm4=Wt EER28L 32g:=μi PC402300:=Initial permeability of PC40 core materialVe EER28L 6150mm3:=Core volumele EER28L 75.5mm:=Effective path lengthAL EER28L_PC402520109−H ⋅:=Nominal inductance of ungapped core setTape 0.06mm:=Wrapping tape thicknessMLT EER28L 2 3.14⋅7.0⋅mm :=Average length of turnAvailable winding heightBw EER28L 212.53⋅mm:=Available winding breadthGeometrical constant of corePower Transformer Flux Swing With EER28L-PC40 from TDKV F 0.5V:=Transformer primary to secondary turn ration 35.174=I plim 1.35I P⋅:=I plim 0.958A=Bs PC403500gauss:=Select number of secondary turnBr PC40500gauss:=ΔB PC4048%Bs PC40Br PC40−()⋅:=ΔB PC40 1.44103×gauss=Np min 50.419=Np cal 90.775=Np 106:=Ns1cal 3.014=Primary no of turnsNs1round Ns1cal():=Ns13=V F20.7V:=V cc 14V:=N Vc 8=Ns29=Ns39=Ns49=Ns513=Ns610=Ns710=Ns810=Ns910=Verification of Design ParametersV ROact n act Vo 1V F+()⋅:=V ROact 194.333V=Vds on 0.5V:=D maxact 0.452=D minact 0.343=Vds act V MAX V ROact+:=Vds act 567.686V=l g 0.726mm=Nom inductance with ungapped core set Lm act 1.514mH=Ip act0.705A=Bm0.124T=Ip act0.845A=Bm0.148T=Bpp max maxBpp V MAX()Bpp V MIN()⎛⎜⎜⎝⎞⎟⎟⎠⎛⎜⎜⎝⎞⎟⎟⎠:=Bpp max0.148T=Check flux density of transformerPower Transformer Winding Currenti p V MIN()0.705A=D1off0.311=I1sp12.842A=I1RMS 4.138A=I1AVG2A=Cp2:=Number of switching pulse todisplayD2off0.066=I2sp0.908A=I2RMS0.135A=I2AVG0.03A=D3off0.066=I3sp0.908A=I3RMS 0.135A=D4off 0.209=I4sp 2.872A=I4RMS 0.758A=D5off 0.138=I5sp 1.452A=I5RMS 0.311A=D6off 0.134=I6sp 1.791A=I6RMS 0.378A=Evaluate Possible Wire GaugeWindow area should be allocated according to the apparent current of individual windingIp RMS V MIN ()0.274A=Kcu trf 0.2:=Window fill factorS m 2.5mm:=Safety creepage distanceAw Bw EER28L 2S m ⋅−:=Available bobbin breadthAw 20.06mm=Primary winding Np 6Secondary winding Ns1Ax pri 0.182mm 2=Ax s10.713mm2=Dx p 0.322mm =Dx s10.322mm=turn_per_layer pri 62=turn_per_layer s15=Primary winding Np Secondary winding Ns1layer pri 2=layer s11=StackUp pri layer pri Dx p Tape +()⋅:=StackUp sec 9layer s1⋅Dx s1Tape +()⋅:=StackUp pri 0.764mm=StackUp sec 3.437mm=TotalStackUp va StackUp pri StackUp sec +5Tape ⋅+:=TotalStackUp va 4.501mm =Resistance per unit length at 100 degCRw pri Rx 10028, ():=Rw s1Rx 10028, ():=Rw pri 2.831103−×Ωcm1−⋅=Rw s1 2.831103−×Ωcm1−⋅=The dc resistance is thenRdc pri MLT EER28L Rw pri ⋅Np ⋅:=Rdc pri 1.319Ω=Rdc s1 3.111m Ω=The ac resistance isδskin0.211mm =Rac pri 2.011Ω=Rac s1 4.742m Ω=Transformer Copper LossPcu tx V MAX ()0.809W =Pcu tx V MIN ()0.787W=Transformer Core Loss EstimationCore loss estimation based on empirical curve fit formula and fit parameters from TDK for PC40 material data within a frequency range of 100 to 200kHz, assumming transformer temperature of 100 degC.C m 0.928:=x 1.61:=y 2.68:=Pcore tx V MAX ()0.6W =Transformer core lossPcore tx V MIN ()0.37W=Total Transformer LossesP tx Vg ()Pcu tx Vg ()Pcore tx Vg ()+:=P tx V MAX ()1.409W =Power transformer loss at high line, FLP tx V MIN ()1.157W=Loss at low line, FLSecondary Rectifier Stress=Vs1diode15.567V=Vs2diode46.7V=Vs3diode46.7V=Vs4diode46.7V=Vs5diode69.788V=Vs6diode53.222V=Vs7diode53.222V=Vc diode42.178VPd rectifier V F Io1_max+4V F2⋅Io6_max :=⋅+⋅⋅⋅⋅V F2Io2_max+V F2Io5_max+V F2Io3_max⋅+V F2Io4_max=Pd rectifier 1.658WOutput Filtering Capacitance StressC out12200μF :=ESR 15m Ω:=C out2220μF :=ESR 220m Ω:=C out3220μF :=ESR 320m Ω:=C out4440μF :=ESR 410m Ω:=C out5220μF :=ESR 520m Ω:=C out6220μF:=ESR 620m Ω:=Is1cap 3.623A=ΔV s10.068V=Is2cap 0.131A=ΔV s20.019V=Is3cap 0.131A=ΔV s30.019V=Is4cap 0.696A=ΔV s40.032V=Is5cap 0.295A==ΔV s50.031V=Is6cap0.359A=ΔV s60.038VCapacitance requirement - Transient response dependence⋅:=Assume delay time before converter response to a τ15Tschange in load currentCapacitive voltage change due to load step ⋅=Voltage change across esr due to a load step ΔVo esrΔIo Resr=Output voltage change due to a load step ignoring ΔVoΔVo capΔVo esr+effect of ESLCapacitance required for a voltage deviation of ΔVowith say Resr:=Select number of capacitor required no_of_cap1=Effective ESR with capacitor chosen Resr5mΩCapacitor ripple current and effective current handling capacityAC rms current seen by cap=ΔIcap 3.623AOutput ripple voltage with selected capacitorsΔVr I1sp ESR 1⋅:=Output ripple voltage due to esrΔVr 64.21mV=Maximum output voltage ripple at room temperaturAt low temperature, esr of capacitor changes significantlyResr lotemp Resr 2⋅:=Resr lotemp 0.01Ω=ΔVr lotemp ΔIcap Resr lotemp ⋅:=ΔVr lotemp 0.036V=Maximum output ripple at low temperatureκripple 63.775%=Ripple voltage design margin at low temperature Step load ripple voltageCo min no_of_cap C out1⋅110%−()⋅:=Voltage change due to step loadΔVo 0.137V=κstep 8.525%=Step response ripple deviation design margin at low temperatureEstimate Power Loss In Capacitor ESRPesr V MAX ()5.468mW=Design RCD SnubberLp leak Lm act 0.2⋅%:=Lp leak 3.028μH=Vsn 220V:=Maximum snubber capacitor voltageK Vsn 5%:=V ROact 194.333V =Psn RES 0.926W=Rsn 52.244K Ω=Csn 3.828nF=Primary FET Voltage StressVds max Vg ()Vg Vsn 1K Vsn+()⋅+:==Peak switch voltage stress at high line Vds max604.352VPrimary Switch CurrentMain FET conducts the transformer primary currentIQ Vg t , ()I mosfet Vg t , ():=Main switch currentMain switch rms currentMain switch peak currentPrimary FET Loss Estimation - IRFBC30AGate drive lossV gate 10V:=Gate drive voltageP gate V gate Qg irfbc30a ⋅fs ⋅:=P gate 0.023W =Gate drive lossSaturation lossPQ on Vg ()IQ RMS Vg ()2Ron irfbc30a ⋅:=PQ on V MAX ()0.305W =Saturation loss at high line, FLPQ on V MIN ()0.28W =Output capacitance lossPQ cap Vg max ()0.244W=Output capacitance loss at high lineSwitch lossV plt VgMiller irfbc30a:=Gate Miller plateau voltage V th Vth irfbc30a:=Gate threshold voltage R gate 5.6Ω:=Gate series resistorGate current that charges the input capacitancefrom from gate threshold to VpltIga0.893A=Gate current that discharge Miller capacitance Crsswhen drain voltage starts to fall to zeroIgb0.804A=PQ switch_on V MIN()7.556103−×W=PQ switch_on V MAX()0.016W=Assumming the same order of magnitude for the switch turn off lost with a fast turn off gate drive circuit, the total switch loss is,PQ switch Vg()2PQ switch_on Vg()⋅:=PQ switch V MIN()0.015W=PQ switch V MAX()0.031W=Total transitional loss at high line, FLTotal Primary FET lossPQ Vg ()P gate PQ on Vg ()+PQ cap Vg ()+PQ switch Vg ()+:=PQ V MIN ()0.514W =PQ V MAX ()0.847W=Primary switch losses at high line, FLDesign Feeback Control LoopBode Plot of Power Stageωn ()2π⋅f n ()⋅:=Small signal moel with feedfoward of UCC2570Small signal model of DCM flyback converter operated in voltage mode controlf z114.469KHz=f z2V MIN()218.443KHz =f z2V MAX ()413.81KHz=f o V MIN ()1.69KHz=f o V MAX ()2.026KHz=G pwrmin ω()G pwr V MIN ω, ():=P pwrmin ω()P pwr V MIN ω, ():=G pwrmax ω()G pwr V MAX ω, ():=P pwrmax ω()P pwr V MAX ω, ():=Loop stability criteriaHow to arrange the crossover frequency?It is the best with as high as possible bandwidth. But the crossover frequency is limited by the parameters:1. Sampling theory limit the crossover freqency not to over 1/2operation frequency.2. The effect fo right plane zero which is changed followed with input voltage, load, and filtering inductance. It can't be compensated.Therefore, the bandwidth shall be far away the right plane zero,1/4--1/5 of RHZ.3. The limitation of error amplifier bandwidth. 1/6-1/10 of operation frequency.fc 7.281KHz =Phase 169.073−=Because of LC resonant at the output, the phase big change and close to 180 degree. As a result, the compensation of type III will be used to boost the phase.Zero-pole arrangement:1. 1st pole at the origin to boost the gain at the low frequencies.2. 2 zeros at LC resonant point.3. 2nd pole at the output capacitor esr zero.4. 3nd pole at the RHZ.Bode Plot of Error AmplifierK-Factor Method:ϕm45 :=P shift360ϕm−:=P shift315=P errorpermitted P shift Phase+:=P errorpermitted145.927=K fac 4.016=f z4f z3:=f z30.747KHz=f p2fc K fac⋅:=f p3f p2:=f p212.049KHz=G pwr.fc G pwr V MIN2πfc⋅,():=G pwr.fc18.471=G error.fz330.547−=R120K Ω:=R20.594K Ω=C20.022μF=C10.359μF=C30.011μF=R3 1.24K Ω=:=()G compfc G comp2πfc⋅=G compfc18.471−Bode Plot of Closed-LoopT loop V in ω, ()T comp ω()T pwr V in ω, ()⋅:=G maxmax ω()G loop V MAX ω, ():=G minmax ω()G loop V MIN ω, ():=P minmax ω()P loop V MIN ω, ():=P maxmax ω()P loop V MAX ω, ():==−Phase loop135Margin180Phase loop+=:=Margin45rd dd ardSecondary winding Ns4Ax s40.238mm2=Dx s40.322mm=turn_per_layer s420=Secondary winding Ns4layer s41=Rw s4Rx10028,():=Rw s4 2.831103−×Ωcm1−⋅=Rdc s437.331mΩ=Rac s456.905mΩ=re w06。