数字逻辑 第五章 常见数字模块 更新 DDCA_Ch5 -2

A31 B31 A30 B30
Cout
+
C30
S31
+
C29
S30
A1 B1 A0 B0
C1 +
C0 +
Cin
S1
S0
图5-5 32位行波进位加法器
Chapter 5 <8>
Ripple-Carry Adder Delay
行波进位加法器的延迟
tripple = NtFA
where tFA is the delay of a full adder
• Some definitions:一些定义
– Column i produces a carry out by either generating a carry out or propagating a carry in to the carry out
– Generate (Gi) and propagate (Pi) signals for each column:
其中tFA是一个全加器的延迟
Chapter 5 <9>
Carry-Lookahead Adder先行进位加法器
• Compute carry out (Cout) for k-bit blocks using generate and propagate signals计算输出进位Cout 对k位块用G和P两个信号
路选择器、译码器等）组成。每个模块都有定义好的接口，当底层
实现不重要时，可以被视为黑盒。每一个规整结构的模块都应易于
扩展为不同规模。
Chapter 5 <3>
1-Bit Adders一位加法器
Half Adder
A
B
Cout
+
S
A B Cout S 00 01 10 11
S= Cout =
图5-1 1 位半加器
1-Bit Adders一位加法器
Half Adder
A
B
Cout
+
S
A B Cout S 00 00 01 01 10 01 11 10
S =AB Cout = AB
图5-1 1 位半加器
Full Adder
A
B
Cout
+
Cin
S
Cin A B Cout S 00 0 0 0 00 1 0 1 01 0 0 1 01 1 1 0 10 0 0 1 10 1 1 0 11 0 1 0 11 1 1 1
Full Adder
A
B
Cout
+
Cin
S
Cin A B Cout S 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1
S= Cout =
图5-3 1位全加器
Chapter 5 <4>
1-Bit Adders一位加法器
Half Adder
A
B
Cout
+
S
A B Cout S 00 00 01 01 10 01 11 10
Chapter 5
Digital Design and Computer Architecture, 2nd Edition
David Money Harris and Sarah L. Harris
常见数字模块
Chapter 5 <1>
Chapter 5 :: Topics
• Introduction引言 • Arithmetic Circuits算术电路 • Number Systems数制系统 • Sequential Building Blocks
S= Cout =
图5-1 1 位半加器
Full Adder
A
B
Cout
+
Cin
S
Cin A B Cout S 00 0 0 0 00 1 0 1 01 0 0 1 01 1 1 0 10 0 0 1 10 1 1 0 11 0 1 0 11 1 1 1
S= Cout =
图5-3 1位全加器
Chapter 5 <5>
S = A B Cin Cout = AB + ACin + BCin
图5-3 1位全加器
Chapter 5 <6>
Multibit Adders (CPAs)多位加法器
进位传播加法器的类型
• Types of carry propagate adders (CPAs):
– Ripple-carry – Carry-lookahead – Prefix
• Column i will generate a carry out if Ai AND Bi are both 1.
说明了层次化、模块化、 规整化的原则
– Hierarchy of simpler components
– Well-defined interfaces and functions
– Regular structure easily extends to different sizes
复杂模块可以用层次化的方法由更简单的模块（如逻辑门电路、多
(slow) 行波进位加法器 (fast) 先行进位加法器 (faster) 前缀加法器
• Carry-lookahead and prefix adders faster for large adders
but require more hardware
Symbol
AB
对于大位数相加，先行进位 加法器和前缀加法器更快， 但是需要更多的硬件
N
N
Cout
+
Cin
N
S
图5-4 进位传播加法C器hapter 5 <7>
Ripple-Carry Adder行波进位加法器Fra Baidu bibliotek
• Chain 1-bit adders together连续串联一位全加器 • Carry ripples through entire chain行波进位通过整个链 • Disadvantage: slow缺点是速度慢
circuits, counters, memory arrays, logic arrays逻辑门电
路、多路选择器、译码器、寄存器、算术运算电路、计算器、存 储器阵列、逻辑阵列
• Building blocks demonstrate hierarchy,
modularity, and regularity:
时序电路模块
• Memory Arrays存储器阵列 • Logic Arrays逻辑阵列
Chapter 5 <2>
Introduction引言
• Digital building blocks:数字模块
– Gates, multiplexers, decoders, registers, arithmetic