ARM Instruction Set(ARM汇编指令集)

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Division There is no division instruction
Advanced Arithmetic
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Used to calculate values larger than 32-Bits Split value into 32-bit sections Start with the least signification section and work up to the most signification section, using the Carry to bridge sections Add with Carry
Barrel Shifter
IR
Control Unit
CPSR
32-Bit ALU
External Memory
MAR: Memory Address Register
MBR: Memory Buffer Register
Address Incrementer
R15 / PC
R14 / LR
R13 / SP
R11
R10 R9 R8
R7
R6 R5 R4
R3
R2 R1 R0
R12
User Registers Booth's Multiplier
MOV Move value MOVS Move value and set condition codes MOV cc S
cc Rd,
op1
cc : Rd ← op1 S : CPSR ← ALU(Flags)
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Rd is the destination (must be a register) op1 is the source, may be any of the DataProcessing addressing modes:
LDR cc B
Rd,
op2
cc : Rd(7:0) cc : Rd(31:8)
← M( op2 ) ←0
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Load Register with Signed Byte from memory
LDR cc SB
Rd,
op2
cc : Rd(7:0) cc : Rd(31:8)
← M( op2 ) ← Rd(7)
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Subtraction
SUB cc S
Rd, Rn,
op1
cc
cc : S :
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Multiplication
MUL cc S
Rd, Rn, Rs cc
cc : S :
Multiplying two 16-bit values (Rn and Rs), produces a 32-bit result (Rd)
Load Register Store Register
Rd, Rd, Rd,
Load Register unsigned Byte Load Register Signed Byte Store Register Byte
Rd, Rd, Rd,
Load Register unsigned Halfword LoadBiblioteka BaiduRegister Signed Halfword Store Register Halfword
Rd, Rm, Rs Rd, Rn, Rd, Rn,
op1 op1
Summary: Memory Access
LDR cc STR cc LDR cc B LDR cc SB STR cc B LDR cc H LDR cc SH STR cc H
Rd, Rd,
op2 op2 op2 op2 op2 op2 op2 op2
Data Movement
MOV cc S
Arithmetic
Rd,
op1
Move Data
ADD cc S SUB cc S MUL cc S ADC cc S SBC cc S
Rd, Rn, Rd, Rn,
op1 op1
Add Subtract Multiply Add with Carry Subtract with Carry
Systems Architecture
ARM Instruction Set
Data, Arithmetic and Memory Access
Notations
Rd Destination register d d may be any register R0 – R15 Condition Code Instruction executed under condition Set Condition Codes Instruction sets condition for cc Data-Processing Addressing Mode Immediate / Register / Scaled Memory Access Addressing Mode Offset / Pre-indexed / Post-Indexed
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Store Register in a Halfword of memory STR cc H Rd, op2 cc : M( op2 ) Memory Reference must be Halfword aligned
← Rd(15:0)
Summary: Movement/Arithmetic
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Store Register in a Byte of memory STR cc B Rd, op2 cc : M( op2 ) ← Rd(7:0)
Load / Store Halfword
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Does not work in the ARMulator An ARM word is 32-bits, so a Halfword is 16-bits Load Register with unsigned Halfword from memory
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ADC cc S
Rd, Rn, op1 cc : Rd ← Rn + op1 cc S : CSPR ← ALU(Flags)
+ CSPR(C)
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Subtract with Carry SBC cc S Rd, Rn, op1 cc : Rd ← (Rn − op1 ) − CSPR(C) cc S : CSPR ← ALU(Flags)
Rd Rm
Instruction Groups
1 2 3 4 5 6 Data Movement Arithmetic Memory Access Logical Flow Control System Control
Data Movement
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50% to 70% of a program
LDR cc H
Rd ,
op2
cc : Rd(15:0) ← M( op2 ) cc : Rd(31:16) ← 0
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Load Register with Signed Halfword from memory
LDR cc SH
Rd ,
op2
cc : Rd(15:0) ← M( op2 ) cc : Rd(31:16) ← Rd(15)
Memory Access
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Load Register from memory LDR cc Rd, op2 Store Register in memory STR cc Rd, op2
cc : Rd
← M( op2 )
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cc : M( op2 ) ← Rd
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op2 is memory reference, may be any of the Memory Access addressing modes:
Offset Pre-Index Post-Index
[Rn, offset ] [Rn, offset ]! [Rn], offset
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Memory Reference must be word aligned
Load / Store Byte
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Load Register with unsigned Byte from memory
cc
S
op1
op2
Instruction Encoding
MOVS
31 · · · 28 cc 000 cc opcode S 24 · · · 21 opcode 20 S 0000
R0, R1
15 · · · 12 Rd 00000000 3···0 Rm
Always = 1110 (0xE) Ignore condition code – Always execute Move = 1101 (0xD) This is a “Move” operation True (1) Set the condition codes (N and Z) N is true if value is Negative Z is true if value is Zero R0 = 0000 Destination Register R1 = 0001 Source Register
Immediate Register Scaled Immediate Scaled Register
#nnn Rn Rn, shift #nnn Rn, shift Rs
Arithmetic
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Addition
ADD cc S
Rd, Rn,
op1
cc
cc : S :
Rd ← Rn + op1 CPSR ← ALU(Flags) Rd ← Rn − op1 CSPR ← ALU(Flags) Rd ← Rn × Rs CSPR ← ALU(Flags)