使用FPGA做Lvds设计
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Design
FPGA LVDS
LVDS(Low-Voltage Differential Signaling)
IEEE
Std1596.3 SCI-LVDS ANSI/TIA/EIA-644
250MHz624 MHz
TI NS LCD
LVDS
FPGA
LVDS
(High Bandwidth )
(Low Power)
(Low noise)
(Low pins)
EMI(Lower EMI Emission)
LVDS LCD
LAN hub Telecom switches
UXGA(1600x1200)
133MHz 3.29Gbps(
24bits)LVDS 4 bits channel6
432MHz channel
ECL
200MHz
LVDS
LVDS ?ECL
CMOS
ANSI/TIA/EIA-644
Design
:
: LVDS
350mV
3.5mA
(Common mode)
= 350mV x 3.5mA=1.225mW
= 2CF2V=2x8pFx(0.35V)2x311MHz=0.610mW
= 1.225+0.610=1.835mW
(
)
EMI
(
)
FPGA
LVDS
IC
Design
: LVDS
LVCMOS
: Common mode
LVDS 1V
olt
2.4 V
olts
1.2 V
olts
0.2
2.2V
olts
1.0
1.4V
olts(
)
FPGA
LVDS
IC
Design
LVDS
(Skew)
Altera
APEX20KE
FPGA
ANSI/TIA/EIA-644
+-25%48PLL
:
:
PLL
LVDS
PLL
:
FPGA
LVDS
IC
Design
Altera
APEX20K400E
622.08MHz
77.76MHz
4
8
(
)
(
)
: APEX20KE
PLL
: LVDS
LVDS
(Synchronization Registers) Latch
PLL
FPGA
FPGA
LVDS
IC
Design
: LVDS
: LVDS
FPGA
LVDS
IC
Design
FPGA
622MHz
Altera
APEX20KE
77.76MHz
APEX20KE
IC
LVDS
77.76MHz
Layout
FPGA
PCB
LVDS
LVDS I/O
(Termination Resistor),
100
(
90
110
)
: LVDS
:
1. (stub)
12mm
2. 3. (skew)
4. CMRR
5.
LVDS
CMOS
TTL
6. LVDS
7.
8.
(via)
9.
(2.2uF, 0.1uF,0.01uF,0.001uF)(GND_CKLK2/VCC_CKLK2
GND_CKLK3/VCC_CKLK3)
Altera
APEX20KE FineLineBGA
I/O
(
)
FPGA
LVDS
IC
Design
FineLineBGA LVDS
Schematic
HDL
Altera
MegaWizard
Quartus
MegaWizard
channel
clock
Schematic
VHDL
VerilogHDL
FPGA
LVDS
IC
Design
MegaWizard
MegaWizard
IC
I/O
Altera APEX20KE
LVDS
()
FPGA LVDS
IC Design
:LVDS