jtag的经典例子,verilog

jtag的经典例子module jtag(TCK,TMS, TDI, PROGRAM_COUNT, SFR_DATA, SOURCE_DI, XRAMDI, PROGDI, TRESET, SCLK,//OutputTDO, //SOURCE_AJ, DESTIN_AJ, XRAMAJ, PROGAJ, DESTIN_DOJ, XRAMDOJ,PROGRAM_COUNTJ, PROGDOJ,NXRAMRJ, nXRAMWJ, NPSENJ ,PROGWE, SFR_WRITEJ, Write_SFR, Read_SFR, Read_RAM, NDESTIN_WEJ, nDESTIN_WEJ, Write_PC,ICReset,ICDisable,ICClock_Disable,ICClock_Enable);//Inputinput TCK;input TMS;input TDI;input TRESET;input SCLK; //IC stop feedback signal at step_into stateinput [15:0] PROGRAM_COUNT; //present PC value input [7:0] SFR_DATA;input [7:0] SOURCE_DI;input [7:0] XRAMDI;input [7:0] PROGDI;//Outputoutput ICReset;output ICDisable;output ICClock_Disable;output TDO;//output [7:0] SOURCE_AJ;//output [15:0] XRAMAJ;//output [15:0] PROGAJ;//output [7:0] DESTIN_DOJ;//output [7:0] XRAMDOJ;//output [7:0] PROGDOJ;//output [15:0] PROGRAM_COUNTJ;output Write_PC;output NXRAMRJ;output nXRAMWJ;//NXRAMWJ,output NPSENJ;output Write_SFR,SFR_WRITEJ;output Read_SFR;output Read_RAM;output nDESTIN_WEJ,NDESTIN_WEJ;output PROGWE;// Test Access Port(TAP) controller controls the scan chains logic .// The architecture of the TAP design fully complied with the IEEE// Standard 1149.1-2090 Standard Test Access Port and Boundary-Scan Architectur// For further details of it, please refer to the standard.//port declare//data bus and address bus for different areawire [7:0]DESTIN_DOJ;wire [7:0]XRAMDOJ;wire [7:0]PROGDOJ;wire [7:0] SOURCE_AJ;wire [7:0] DESTIN_AJ;wire [15:0]XRAMAJ;wire [15:0]PROGAJ;//read and write flag for different area reg NXRAMRJ;reg nXRAMWJ, NXRAMWJ;reg NPSENJ;reg PROGWE;reg Read_SFR;reg Read_RAM;reg nDESTIN_WEJ, NDESTIN_WEJ; reg Write_SFR;reg SFR_WRITEJ;//Instruction register: IR_WIDTH 8bits reg [7:0]InstructionReg;reg [7:0]InstructionRegLat;//test data registersreg [7:0]IDCodeReg;reg BypassReg;reg [7:0]INTESTReg;reg [7:0]INTESTRegLat;reg [7:0]CtrlReg;reg [7:0]CtrlRegLat;reg [7:0]DataReg;reg [7:0]DataRegLat;reg [15:0]AddrReg;reg [15:0]AddrRegLat;//set break pointreg [15:0]BreakPointReg;reg [15:0]BreakPointLat1;reg [15:0]BreakPointLat2;reg [15:0]BreakPointLat3;reg [15:0]BreakPointLat4;reg [15:0]BreakPointLat5;reg [15:0]PcReg;reg [15:0]PcRegLat;wire [15:0]PROGRAM_COUNTJ;//TDO selectwire TDO;reg OutEnable;reg SelectedTDO; // data outwire OutSelect; // select instruction or test data is cl ocked outwire InstructionOut;wire DataPathOut; // test data register out port ,select which test data path to be clock outwire BypassOut;wire IDCodeOut;wire INTESTOut;wire DataOut;wire AddrOut;wire CtrlOut;wire PcOut;wire BreakPointOut;//ICDisable and reset flagreg ICReset;//wire reset;wire ICClock_Disable;wire ICClock_Enable;reg ICDisable;reg ICClock_Disable1;reg ICClock_Disable2;reg ICClock_Disable3;wire Stepin_flag;reg [1:0] Disable2_CNT ;reg flag;reg flag_sample;wire Breakpoint_flag;//reg [1:0] disable3_CNT;//reg disable3_CNT_enable;// break_point informations and flags //break point enablereg Break1_enable;reg Break2_enable;reg Break3_enable;reg Break4_enable;reg Break5_enable; wire Break1Comp; wire Break2Comp; wire Break3Comp; wire Break4Comp; wire Break5Comp;//disable break point wire Break1Disable; wire Break2Disable; wire Break3Disable; wire Break4Disable; wire Break5Disable;// instruction selected reg [19:0] InstruDecode;wire EXTESTSelected; wire IDCODESelected; wire INTESTSelected; wire BYPASSSelected; wire CTRLSelected;wire DATASelected;wire ADDRSelected;wire PCSelected;wire Write_PC;wire BreakPoint1Selected; wire BreakPoint2Selected; wire BreakPoint3Selected; wire BreakPoint4Selected; wire BreakPoint5Selected;wire BreakPoint_Disable; wire Break1DisableSelected; wire Break2DisableSelected; wire Break3DisableSelected; wire Break4DisableSelected; wire Break5DisableSelected;//TAP state machine reset flag wire TapReset;//TAP state register: 4bitsreg [3:0]TapState;//UPDATA_IR FLAGreg IR_Update_flag;//define the TAP statesparameter EXIT2_DR =4’h0;parameter EXIT1_DR =4’h1;parameter SHIFT_DR =4’h2;parameter PAUSE_DR =4’h3;parameter SELECT_IR_SCAN =4’h4;parameter UPDATE_DR =4’h5;parameter CAPTURE_DR =4’h6;parameter SELECT_DR_SCAN =4’h7;parameter EXIT2_IR =4’h8;parameter EXIT1_IR =4’h9;parameter SHIFT_IR =4’hA;parameter PAUSE_IR =4’hB;parameter RUN_TEST_IDLE =4’hC;parameter UPDATE_IR =4’hD;parameter CAPTURE_IR =4’hE;parameter TEST_LOGIC_RESET =4’hF;parameter DEVICE_IDCODE =1;/************************************TAP StateMachine***********************************/always @ ( posedge TCK or posedge TRESET) begin: p_TAPseqif (TRESET)TapState <=TEST_LOGIC_RESET;elsebegin: TAPStatecase (TapState) // synopsys full_case parallel_case EXIT2_DR: //4’h0beginif (TMS)TapState <= UPDATE_DR;elseTapState <= SHIFT_DR;endEXIT1_DR: //4’h1beginif (TMS)TapState <= UPDATE_DR;elseTapState <= PAUSE_DR;endSHIFT_DR: //4’h2beginif (TMS)TapState <= EXIT1_DR;endPAUSE_DR: //4’h3beginif (TMS)TapState <= EXIT2_DR;endSELECT_IR_SCAN: //4’h4 beginif (TMS)TapState <= TEST_LOGIC_RESET; elseTapState <= CAPTURE_IR;endUPDATE_DR: //4’h5beginif (TMS)TapState <= SELECT_DR_SCAN; elseTapState <= RUN_TEST_IDLE; endCAPTURE_DR: //4’h6beginif (TMS)TapState <= EXIT1_DR;elseTapState <= SHIFT_DR;endSELECT_DR_SCAN: //4’h7 beginif (TMS)TapState <= SELECT_IR_SCAN; elseTapState <= CAPTURE_DR;endEXIT2_IR: //4’h8beginif (TMS)TapState <= UPDATE_IR; elseTapState <= SHIFT_IR; endEXIT1_IR: //4’h9beginif (TMS)TapState <= UPDATE_IR; elseTapState <= PAUSE_IR; endSHIFT_IR: //4’hA beginif (TMS)TapState <= EXIT1_IR; endPAUSE_IR: //4’hB beginif (TMS)TapState <= EXIT2_IR;endRUN_TEST_IDLE: //4’hCif (TMS) TapState <= SELECT_DR_SCAN; UPDATE_IR: //4’hDbeginif (TMS)TapState <= SELECT_DR_SCAN;elseTapState <= RUN_TEST_IDLE;endCAPTURE_IR: //4’hEbeginif (TMS)TapState <= EXIT1_IR;elseTapState <= SHIFT_IR;endTEST_LOGIC_RESET: //4’hFif (!TMS) TapState <= RUN_TEST_IDLE;endcaseend //TAPStateend // p_TAPseq/*always @(TapState)if(TapState==`TEST_LOGIC_RESET) TapReset =1;else TapReset =0;*/assign TapReset = (TapState==TEST_LOGIC_RESET)? 1:0;//assign reset = TapReset || ICReset;/************************************ TAP State Machine end ***********************************//***********************InstructionRegister***********************///The fixed value 0001 is loaded into the instruction register during the CAPTURE_IR controller state.always @ (posedge TCK or posedge TapReset)beginif(TapReset)InstructionReg <= 0;//01;else if(TapState==CAPTURE_IR) InstructionReg[7:0] <= 0;//8’h41;else if(TapState==SHIFT_IR)InstructionReg[7:0] <= {TDI,InstructionReg[7:1]}; endalways @ (posedge TapReset or negedge TCK) beginif(TapReset) beginInstructionRegLat = 0;flag = 0;IR_Update_flag=0;endelse if( TapState==UPDATE_IR)beginInstructionRegLat = InstructionReg;IR_Update_flag=1;if(InstructionRegLat[7:6] == 2’b10)flag = !flag;elseflag=0;endelseIR_Update_flag=0;end//************************Instruction Register End*******************///******************** instruction decode ***********************///instructionregLat select test data register for outputalways @(posedge TapReset or posedge SCLK)beginif(TapReset)InstruDecode[19:0]=20’h00000;else begincase(InstructionRegLat[7:0])8’h40: InstruDecode[19:0]=20’h00001; //EXTESTSelected8’h41: InstruDecode[19:0]=20’h00001<< 1 ; //IDCODESelected8’h42: InstruDecode[19:0]=20’h00001<< 2 ; //PCSelected8’H44: InstruDecode[19:0]=20’h00001<< 3 ; //Write_PC8’H45: InstruDecode[19:0]=20’h00001<< 4; //INTESTSelected 8’h49: InstruDecode[19:0]=20’h00001<< 5 ; //BreakPoint1Sele cted8’h4a: InstruDecode[19:0]=20’h00001<< 6 ; //BreakPoint2Sele cted8’h4b: InstruDecode[19:0]=20’h00001<< 7 ; //BreakPoint3Sele cted8’h4c: InstruDecode[19:0]=20’h00001<< 8 ; //BreakPoint4Sele cted8’h4d: InstruDecode[19:0]=20’h00001<< 9 ; //BreakPoint5Sele cted8’h50: InstruDecode[19:0]=20’h00001<< 10 ; //BreakPoint_Dis able8’h51: InstruDecode[19:0]=20’h00001<< 11; //Break1DisableSe lected8’h52: InstruDecode[19:0]=20’h00001<< 12; //Break2DisableSe lected8’h53: InstruDecode[19:0]=20’h00001<< 13; //Break3DisableSe lected8’h54: InstruDecode[19:0]=20’h00001<< 14; //Break4DisableSelected8’h55: InstruDecode[19:0]=20’h00001<< 15; //Break5DisableSe lected8’h61: InstruDecode[19:0]=20’h00001<< 16; //CTRLSelected8’h62: InstruDecode[19:0]=20’h00001<< 17; //DATASelected8’h64: InstruDecode[19:0]=20’h00001<< 18; //ADDRSelecteddefault: InstruDecode[19:0]=20’h00001<< 19; //BYPASSSelected endcaseendendassign EXTESTSelected = InstruDecode[0];assign IDCODESelected = InstruDecode[1];assign PCSelected = InstruDecode[2];assign Write_PC = InstruDecode[3];assign INTESTSelected = InstruDecode[4];assign BreakPoint1Selected = InstruDecode[5];assign BreakPoint2Selected = InstruDecode[6];assign BreakPoint3Selected = InstruDecode[7];assign BreakPoint4Selected = InstruDecode[8];assign BreakPoint5Selected = InstruDecode[9];assign BreakPoint_Disable = InstruDecode[10];assign Break1DisableSelected = InstruDecode[11];assign Break2DisableSelected = InstruDecode[12];assign Break3DisableSelected = InstruDecode[13];assign Break4DisableSelected = InstruDecode[14];assign Break5DisableSelected = InstruDecode[15];assign CTRLSelected = InstruDecode[16];assign DATASelected = InstruDecode[17];assign ADDRSelected = InstruDecode[18];assign BYPASSSelected = InstruDecode[19];/******************** Instruction Decode End**********************//***************************test Data Registers***************************/always @ (posedge TCK or posedge TapReset)beginif(TapReset)beginIDCodeReg <= DEVICE_IDCODE; INTESTReg <=0;DataReg <= 0;AddrReg <= 0;CtrlReg <= 0;PcReg <= 0;BreakPointReg <= 0;endelse if(TapState==SHIFT_DR)beginif(IDCODESelected)IDCodeReg <= {TDI,IDCodeReg[7:1]}; else if(INTESTSelected) INTESTReg<={TDI,INTESTReg[7:1]}; else if(DATASelected)DataReg <= {TDI,DataReg[7:1]};else if(ADDRSelected)AddrReg <= {TDI,AddrReg[7:1]}; else if(CTRLSelected)CtrlReg <= {TDI,CtrlReg[7:1]};else if(PCSelected ||Write_PC)PcReg<={TDI,PcReg[15:1]};else if(BreakPoint1Selected | BreakPoint2Selected | BreakPoint3Selec ted | BreakPoint4Selected | BreakPoint5Selected)BreakPointReg<={TDI,BreakPointReg[15:1]};else BypassReg <= TDI;endelse if(TapState==CAPTURE_DR)beginif(IDCODESelected)IDCodeReg <= DEVICE_IDCODE;else if(DATASelected)begincase(CtrlRegLat[5:0])6’b000101: DataReg <= SFR_DATA;6’b001001: DataReg <= SOURCE_DI;6’b010001: DataReg <= XRAMDI;6’b100001: DataReg <= PROGDI;endcaseendelse if(ADDRSelected)AddrReg <= 8’h00;else if(INTESTSelected)INTESTReg <=8’h00;else if(CTRLSelected)CtrlReg <= 8’h00;else if(PCSelected)PcReg <= PROGRAM_COUNT;else if(Write_PC)PcReg <= 0;else if(BreakPoint1Selected | BreakPoint2Selected | BreakPoint3Selec ted | BreakPoint4Selected | BreakPoint5Selected)BreakPointReg<=0;else BypassReg <=0;endendalways @(negedge TCK or posedge TapReset)beginif(TapReset)beginDataRegLat = 0;CtrlRegLat = 0;INTESTRegLat =0;PcRegLat = 0;BreakPointLat1 = 0;BreakPointLat2 = 0;BreakPointLat3 = 0;BreakPointLat4 = 0;BreakPointLat5 = 0;endelsebeginif(ICReset) CtrlRegLat=0;elsebeginif(TapState==UPDATE_DR)beginif(DATASelected)//after read the data from data register or after write data to data register DataRegLat=DataReg;else if(CTRLSelected)CtrlRegLat=CtrlReg;else if(Write_PC)PcRegLat=PcReg;else if(INTESTSelected)INTESTRegLat=INTESTReg;else if(BreakPoint1Selected) BreakPointLat1=BreakPointReg;else if(BreakPoint2Selected) BreakPointLat2=BreakPointReg;else if(BreakPoint3Selected) BreakPointLat3=BreakPointReg;else if(BreakPoint4Selected) BreakPointLat4=BreakPointReg;else if(BreakPoint5Selected) BreakPointLat5=BreakPointReg;//elseendendendendassign PROGRAM_COUNTJ=PcRegLat;always @(posedge TapReset or posedge TCK ) beginif(TapReset)AddrRegLat = 0;elseif(TapState==UPDATE_DR)beginif(ADDRSelected)AddrRegLat=AddrReg;else if(DATASelected)AddrRegLat =AddrRegLat + 1’b1;endend//************************ test registers end**********************///********************ICDisablesignal****************************/always @(negedge SCLK or posedge TapReset )beginif(TapReset) beginICClock_Disable1 =0;ICReset =0;endelsebegincase(InstructionRegLat[7:6])2’b01 : //PAUSEbeginICClock_Disable1 =1;end2’b11: //RESETbeginif(IR_Update_flag)ICReset =1;else ICReset =0;enddefault : //step_intobeginICClock_Disable1 =0;ICReset =0;endendcaseendendassign Stepin_flag = (InstructionRegLat[7:6]==2’b10); always @( negedge SCLK or posedge TapReset )beginif(TapReset)beginICClock_Disable2 =0;Disable2_CNT =0;flag_sample =0;endelsebeginif(InstructionRegLat[7:6]==2’b10)beginif(flag_sample ^ flag)beginif(Disable2_CNT==2 && ICClock_Disable2==1) beginDisable2_CNT=0;ICClock_Disable2 =0;endflag_sample = flag;endif(Stepin_flag)beginDisable2_CNT=Disable2_CNT +1;if(Disable2_CNT==2)ICClock_Disable2 =1;endendelsebeginICClock_Disable2 =0;flag_sample =0;Disable2_CNT =0;endendendalways @(negedge SCLK or posedge TapReset)// or posedge Breakpoint_flag)beginif(TapReset)ICClock_Disable3=0;elsebeginif(TapState == UPDATE_IR && IR_Update_flag)// if(TapState == `UPDATE_IR)ICClock_Disable3=0;else if(Breakpoint_flag )ICClock_Disable3 =1;endendassign ICClock_Disable = ICClock_Disable1 || ICClock_Disable2 || ICClock_Disable3;assign ICClock_Enable = (TapState==RUN_TEST_IDLE) && (INTESTSelected);always @(posedge SCLK)beginif(ICClock_Disable)beginICDisable=1;endelse ICDisable=0;end//***************************ICDisable signal end***************************///*************************** BreakPoint set *********************/assign Break1Disable = TapReset || BreakPoint_Disable || Break1DisableSelected;assign Break2Disable = TapReset || BreakPoint_Disable || Break2DisableSelected;assign Break3Disable = TapReset || BreakPoint_Disable || Break3DisableSelected;assign Break4Disable = TapReset || BreakPoint_Disable || Break4DisableSelected;assign Break5Disable = TapReset || BreakPoint_Disable || Break5DisableSelected;always @(posedge Break1Disable or posedge BreakPoint1Selected ) beginif(Break1Disable)Break1_enable<=0;elseBreak1_enable<=1;endalways @(posedge Break2Disable or posedge BreakPoint2Selected ) beginif(Break2Disable)Break2_enable<=0;elseBreak2_enable<=1;endalways @(posedge Break3Disable or posedge BreakPoint3Selected ) beginif(Break3Disable)Break3_enable<=0;elseBreak3_enable<=1;endalways @(posedge Break4Disable or posedge BreakPoint4Selected ) beginif(Break4Disable)Break4_enable<=0;elseBreak4_enable<=1;endalways @(posedge Break5Disable or posedge BreakPoint5Selected ) beginif(Break5Disable)Break5_enable<=0;elseBreak5_enable<=1;endassign Break1Comp = (BreakPointLat1==PROGRAM_COUNT)?1:0; assign Break2Comp = (BreakPointLat2==PROGRAM_COUNT)?1:0; assign Break3Comp = (BreakPointLat3==PROGRAM_COUNT)?1:0; assign Break4Comp = (BreakPointLat4==PROGRAM_COUNT)?1:0; assign Break5Comp = (BreakPointLat5==PROGRAM_COUNT)?1:0;assign Breakpoint_flag = (Break1_enable & Break1Comp) || (Break2_enable & Break2Comp) ||(Break3_enable & Break3Comp) || (Break4_enable &Break4Comp) ||(Break5_enable & Break5Comp);//************************BreakPoint set end********************//*****************************TDOcontrol***************************/assign InstructionOut = InstructionReg[0];assign BypassOut = BypassReg;assign IDCodeOut = IDCodeReg[0];assign DataOut = DataReg[0];assign AddrOut = AddrReg[0];assign CtrlOut = CtrlReg[0];assign PcOut = PcReg[0];assign BreakPointOut = BreakPointReg[0];assign DataPathOut =(IDCODESelected & IDCodeOut) | (BYPASSSelected & BypassOut) |(DATASelected & DataOut) | (ADDRSelected & AddrOut)|(CTRLSelected & CtrlOut) | (PCSelected & PcOut)|((BreakPoint1Selected | BreakPoint2Selected | BreakPoint3 Selected |BreakPoint4Selected | BreakPoint5Selected) & BreakPoint Out );//IR or test data is sent outalways @(TapState)beginif(TapState ==SHIFT_IR || TapState ==SHIFT_DR ) OutEnable = 1;elseOutEnable = 0;endassign OutSelect = TapState[3];always @(negedge TCK)beginif(OutSelect)SelectedTDO = InstructionOut;elseSelectedTDO =DataPathOut;endassign TDO = (SelectedTDO & OutEnable) | (ICDisable & ~OutEnable);/**************************CtrlReg decode *************************///if the last two bit is ’01’: read data from IC core to data register,//else if the last two bit is ’10’:write data from data latch register to IC core//always @(posedge TCK or posedge TapReset)// or negedge InstructionRegLat[6])always @( TapReset or CtrlRegLat or InstructionRegLat[6] or ICReset) beginif(TapReset || ~InstructionRegLat[6] || ICReset)beginRead_SFR = 0;SFR_WRITEJ = 0;Read_RAM = 0; NDESTIN_WEJ = 1; NXRAMRJ = 1; NXRAMWJ = 1; NPSENJ = 1;PROGWE = 0;endelsebeginRead_SFR = 0;SFR_WRITEJ = 0;Read_RAM = 0; NDESTIN_WEJ = 1; NXRAMRJ = 1; NXRAMWJ = 1; NPSENJ = 1;PROGWE = 0;case(CtrlRegLat[5:0])8’h05: Read_SFR =1; 8’h06: SFR_WRITEJ =1; 8’h09: Read_RAM =1;8’h0a: NDESTIN_WEJ =0;8’h11: NXRAMRJ =0;8’h12: NXRAMWJ =0;8’h21: NPSENJ =0;8’h22: PROGWE =1;default:beginRead_SFR = 0;SFR_WRITEJ = 0;Read_RAM = 0;NDESTIN_WEJ = 1;NXRAMRJ = 1;NXRAMWJ = 1;NPSENJ = 1;PROGWE = 0;endendcaseendendalways @(TapReset or TCK or TapState or DATASelected or SFR_WRITEJ or NDESTIN_WEJ or NXRAMWJ or ICReset)beginif(TapReset || ICReset)beginWrite_SFR = 0;nDESTIN_WEJ = 1;nXRAMWJ = 1;endelse if(TapState==UPDATE_DR && DATASelected) beginif(~TCK)beginWrite_SFR = SFR_WRITEJ;nDESTIN_WEJ = NDESTIN_WEJ;nXRAMWJ = NXRAMWJ;endelsebeginWrite_SFR = 0;nDESTIN_WEJ = 1;nXRAMWJ = 1;endendelsebeginWrite_SFR = 0;nDESTIN_WEJ = 1;nXRAMWJ = 1;endend//assign DESTIN_DOJ = DataRegLat[7:0] & {8{ SFR_WRITEJ | ~NDESTIN_WEJ}};//assign XRAMDOJ = DataRegLat[7:0] & {8{ ~NXRAMWJ }};//assign PROGDOJ = DataRegLat[7:0] & {8{ PROGWE }};//assign SOURCE_AJ = AddrRegLat[7:0] & {8{Read_SFR | Read_RAM}};//assign DESTIN_AJ = AddrRegLat[7:0] & {8{SFR_WRITEJ | ~NDESTIN_WEJ}};//assign XRAMAJ = AddrRegLat[15:0] & {16{~(NXRAMWJ & NXRAMRJ)}};//assign PROGAJ = AddrRegLat[15:0] & {16{~NPSENJ | PROGWE }}; endmodule。