verelog闹钟设计

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if(time_m_s==5) begin time_m_s<=0; time_m_g<=0; cin_m<=0; cin_h<=1; end else begin time_m_s<=time_m_s+1; time_m_g<=0; cin_m<=0; end end else begin time_m_g<=time_m_g+3'd1; cin_m<=0; end end if(cin_h==1) begin if(time_h_s==2) begin if(time_h_g==4) begin time_h_s<=0; time_h_g<=0; cin_h<=0;
if(count==4) count<=0;
case(count) 3'b000: begin minute_g<=minute_g; minute_s<=minute_s; hour_g<=hour_g; hour_s<=hour_s; end
default:begin
minute_g<=S; minute_s<=minute_g; hour_g<=minute_s; hour_s<=hour_g; end endcase
always@(posedge clkout) begin if(set==1) begin hour_s<=0; hour_g<=0; minute_s<=0; minute_g<=0; R<=1; end if(R==1) begin if(TIME==1||alarm==1) begin count<=0; R<=0; end
end endmodule
计时器
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • //为仿真需要，此处没有分频。 module jishiqi(clk,set,TIME,alarm,time_h_s,time_h_g,time_m_s,time_m_g,hour_s,hour_g,minute_s,minute_g); input clk,set,TIME,alarm; input[3:0] hour_s,hour_g,minute_s,minute_g; output[3:0] time_h_s,time_h_g,time_m_s,time_m_g; reg[3:0] time_h_s,time_h_g,time_m_s,time_m_g; reg[5:0] Second; reg[25:0] count; reg clk_En,cin_m,cin_h; reg R; always@(posedge clk) begin // count=(count==25'd49999999)?25'd0:(count + 25'd1);//分频系数 49,999,999. // clk_En=(count==25'd49999999)?1'd1:1'd0; // if(clk_En) // begin if(set==1) R<=1; if(R==0) begin if(Second<59) Second<=Second+1; if(Second==59) begin Second<=0; cin_m<=1; end if(cin_m==1) begin if(time_m_g==9) begin
分频器
• • • • • • • • • • • • • • //分频器的作用是对50Mhz的系统时钟信号进行分频，得到频率为1000hz的信号，作为 显示器的输入信号。 module fenpinqi(clk,clkout); input clk; output clkout; reg clkout; reg [31:0] count; reg clk_En; always @(posedge clk ) begin count <= (count == 32'd1) ? 32'd0 : (count + 32'd1);//分频系数49999. clk_En <= (count == 32'd1) ? 1'd1 : 1'd0; clkout <= clk_En; end endmodule
显示器
• module LED(clkout,led_in1,led_in2,led_in3,led_in4,led1,led2,lHale Waihona Puke Baidud3,led4);
end else begin
time_h_g<=time_h_g+1; cin_h<=0; end end
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else begin if(time_h_g==9) begin time_h_s<=time_h_s+1; time_h_g<=0; cin_h<=0; end else begin time_h_g<=time_h_g+1; cin_h<=0; end end end end else begin if(TIME==1) begin time_h_s<=hour_s; time_h_g<=hour_g; time_m_s<=minute_s; time_m_g<=minute_g; R<=0; end if(alarm==1) R<=0; end
顶层模块
• • • • • • • module naozhong(clk,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,led1,led2,led3,led4,fengming,led_in1,led_in2,led_in3,led_in4); input clk,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9; output[6:0] led1,led2,led3,led4,fengming; output[3:0] led_in1,led_in2,led_in3,led_in4; wire clkout; wire[6:0] led1,led2,led3,led4; wire[3:0] time_h_s,time_h_g,time_m_s,time_m_g,clock_h_s,clock_h_g,clock_m_s,clock_m_g,hour_s,hour_g,minute_s,minute_g,led_in1,led_in2, led_in3,led_in4; wire fengming; fenpinqi a1(clk,clkout); anjianbianma b1(clk,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,hour_s,hour_g,minute_s,minute_g); clock c1(clk,set,TIME,alarm,hour_s,hour_g,minute_s,minute_g,clock_h_s,clock_h_g,clock_m_s,clock_m_g); jishiqi d1(clk,set,TIME,alarm,time_h_s,time_h_g,time_m_s,time_m_g,hour_s,hour_g,minute_s,minute_g); kongzhiqi e1(clk,set,TIME,alarm,time_h_s,time_h_g,time_m_s,time_m_g,clock_h_s,clock_h_g,clock_m_s,clock_m_g,hour_s,hour_g,minute_s,min ute_g,led_in1,led_in2,led_in3,led_in4,fengming); LED f1(clkout,led_in1,led_in2,led_in3,led_in4,led1,led2,led3,led4); endmodule
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按键编码器
• module anjianbianma(clkout,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,hour_s,hour_g,minute_s,minute_g);
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input clkout,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9; output[3:0] hour_s,hour_g,minute_s,minute_g; reg[3:0] hour_s,hour_g,minute_s,minute_g; reg R; reg[2:0] count; reg[3:0] S;
// end end endmodule
闹钟
• • • • • • • • • • • • • • • • • • • • • • • • • module clock(clkout,set,TIME,alarm,hour_s,hour_g,minute_s,minute_g,clock_h_s,clock_h_g,clock_m_s,clock_m_g); input clkout,set,TIME,alarm; input[3:0] hour_s,hour_g,minute_s,minute_g; output[3:0] clock_h_s,clock_h_g,clock_m_s,clock_m_g; reg[3:0] clock_h_s,clock_h_g,clock_m_s,clock_m_g; reg R; always@(posedge clkout) begin if(set==1) R=1; if(R==1) begin if(alarm==1) begin clock_h_s<=hour_s; clock_h_g<=hour_g; clock_m_s<=minute_s; clock_m_g<=minute_g; R=0; end if(TIME==1) R=0; end end endmodule
闹钟设计
• 小组成员：
赵亚 简虎 王泽 卢成 潘楠楠 赵峰
作品简介
• 功能一：时钟计时 • 功能二：调整时间 • 功能三：闹钟
程序代码
• • • • • • • 顶层模块：naozhong 按键编码器：anjianbianma 计时器：jishiqi 闹钟：clock 分频器：fenpinqi 显示器：LED 控制器：kongzhiqi
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else if(s0==1) begin S<=0;count<=count+1; end else if(s1==1) begin S<=1;count<=count+1; end else if(s2==1) begin S<=2;count<=count+1; end else if(s3==1) begin S<=3;count<=count+1; end else if(s4==1) begin S<=4;count<=count+1; end else if(s5==1) begin S<=5;count<=count+1; end else if(s6==1) begin S<=6;count<=count+1; end else if(s7==1) begin S<=7;count<=count+1; end else if(s8==1) begin S<=8;count<=count+1; end else if(s9==1) begin S<=9;count<=count+1; end else begin S<=S;count<=0; end