中国科学院--数字集成系统设计--第七次作业+马路+2011E8007361063

ready and /burst
read3
/ready read4
ready States Idle Decision Read1 Read2 Read3 Read4 Write oe 0 0 1 1 1 1 0 we 0 0 0 0 0 0 1 addr[1:0] 00 00 00 01 10 11 00
@else reset (synch.) idle ready Bus_id = “F3” decision /read_write /ready write read_write read1 /ready /ready ready and burst read2 ready /ready ready
boolean; in std_logic; in std_logic; out std_logic; out std_logic
architecture Behavioral of cnt_fsm is type STATE_TYPE is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is "0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111"; signal next_state,current_state: STATE_TYPE; begin
③信号申明部分的 up_down 类型申明为 boolean 类型，同时初值置为 “true” 。
signal up_down : boolean := true;
④最后用于仿真波形使用的激励如下：
stim_proc: process begin rst<='1'; wait for clk_period; rst<='0'; wait for clk_period*20; up_down<=false; wait for clk_period*20; wait; end process;
@else reset (synch.) idle ready Bus_id = “F3” decision /read_write /ready write read_write read1 /ready /ready ready and burst read2 ready /ready ready
空间中心 马路 2011E8007361063
姓名：马路 班级：20110Assignment 7 (OPTIONAL) 1. Design a VHDL model for a 4-bit up-and-down synchronous binary counter with carry and borrow signs using FSM. Verification of this design is especially appreciated. 2. FSM is frequently used to design SRAM controller. Given the bubble diagram of a SRAM controller and its state-and-output table as shown below, please � Verif y this model. For the FSM with states encoded in One-Hot type, � draw schematic circuits for states (1) IDLE, (2) DECISION, (3) WRITE, and (4) READ1, READ2, READ3, READ4 respectively.
说明：所以在写计数器状态机的程序代码时，只需要对照着状态转移图就可以很 轻松地写出代码。首先复位，状态机最先停留在 S0 状态，此时进位信号 carry 和借位信号 borrow 都为 0，此时如果加减计数标志 up_down 为假， 则计数器做减法，此时需要借位，从而转到 S15 状态，并且置借位信号 borrow 为 1；当加减计数标志 up_down 为真时，计数器开始做加法，在时 钟的作用下，从状态 S0 一直计数到状态 S15 ；当计数状态出于 S15 时，此时 如果 up_down 为真，再来一个时钟，计数状态就会从 S15 转到 S0 ，并且置 进位标志 carry 为 1。
空间中心 马路 2011E8007361063
1.5
计数器状态机 TestBench 文件 计数器的 TestBench 文件很好写，但是需要注意几点： ①由于使用了 boolean 类型的端口，所以需要加入下面的两个库文件：
USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL;
②端口映射部分的 up_down 信号应该修改为 boolean 类型（默认为 std_logic 类型） 。
COMPONENT cnt_fsm PORT( up_down : IN boolean; rst : IN std_logic; clk : IN std_logic; carry : OUT std_logic; borrow : OUT std_logic ); END COMPONENT;
空间中心 马路 2011E8007361063
状态机状态转换程序
when s5 => if (up_down) then next_state<=s6; else next_state<=s4; end if; when s6 => if (up_down) then next_state<=s7; else next_state<=s5; end if; when s7 => if (up_down) then next_state<=s8; else next_state<=s6; end if; when s8 => if (up_down) then next_state<=s9; else next_state<=s7; end if; when s9 => if (up_down) then next_state<=s10; else next_state<=s8; end if; when s10 => if (up_down) then next_state<=s11; else next_state<=s9; end if; when s11 => if (up_down) then next_state<=s12; else next_state<=s10; end if; when s12 => if (up_down) then next_state<=s13; else next_state<=s11; end if; when s13 => if (up_down) then next_state<=s14; else next_state<=s12; end if; when s14 => if (up_down) then next_state<=s15; else next_state<=s13; end if; when s15 => borrow<='0'; if (up_down) then next_state<=s0; carry<='1'; else next_state<=s14; end if; end case; end process COMB_PROC; end Behavioral;
空间中心 马路 2011E8007361063
Answers：
1. Design a VHDL model for a 4-bit up-and-down synchronous binary counter with carry and borrow signs using FSM. Verification of this design is especially appreciated. 解答： 1.1 题目要求利用状态机设计一个 4 比特的可加减计数器，并且带有进位和借 位标志。由此可知，一共有 16 种状态，分别定义为： S0 ~ S15 ，对应的状 态分别为： 0000 ~ 1111 。首先根据题目要求画出状态转移图如下：
ready and /burst
read3
/ready read4
ready States Idle Decision Read1 Read2 Read3 Read4 Write oe 0 0 1 1 1 1 0 we 0 0 0 0 0 0 1 addr[1:0] 00 00 00 01 10 11 00
空间中心 马路 2011E8007361063
2. FSM is frequently used to design SRAM controller. Given the bubble diagram of a SRAM controller and its state-and-output table as shown below, please � Verif y this model. For the FSM with states encoded in One-Hot type, � draw schematic circuits for states (1) IDLE, (2) DECISION, (3) WRITE, and (4) READ1, READ2, READ3, READ4 respectively.