AD5543BR电流输出串行输入型AD
单片机ad转换原理
单片机ad转换原理
单片机的AD转换原理基于模拟信号的数字化处理。
在单片机中，AD转换是将模拟信号转换为数字信号的过程，以便于单片机进行数字信号的处理和运算。
AD转换的过程主要由两个部分组成：采样和量化。
采样是指对模拟信号进行离散化处理，将连续的模拟信号转换为离散的采样值。
这是通过采样定理实现的，采样定理认为，如果采样频率大于模拟信号的最高频率的两倍，那么就能够完全还原原始信号。
量化是将采样后的连续值转换为离散值的过程。
通过使用一个固定的参考电压，将模拟信号的幅值分为若干个等级，然后将每个等级映射为一个数字值。
量化的结果是离散的数字信号，每个数字代表一个特定的幅值范围，通常用二进制表示。
在单片机中，通常使用的AD转换器是SAR（逐次逼近型）的AD转换器。
SAR AD转换器通过逐次逼近的方式，不断调整DAC（数字-模拟转换器）的输出值，使其逼近输入信号的幅值，最后得到一个与输入信号幅值对应的数字量。
AD转换器的输出可以通过串行或并行方式传输给单片机的内部数据总线，供单片机进行后续的数字信号处理和运算。
在程序设计中，可以通过对AD转换器的配置和控制，调整转换精度、采样率等参数，以满足具体应用的需求。
总结起来，单片机的AD转换原理是将模拟信号经过采样和量
化，转换为数字信号，并通过AD转换器将结果传输给单片机进行处理。
这个过程是通过逐次逼近的方式实现的，利用固定的参考电压和二进制编码表示模拟信号的幅值范围。
AD5623、AD5643、AD5663中文资料
应用
过程控制 数据采集系统 便携式电池供电仪表 数字增益和失调电压调整 可编程电压源和电流源 可编程衰减器
概述
AD5623R/AD5643R/AD5663R均属于 nanoDAC系列，分别 是低功耗、双通道、 12/14/16位缓冲电压输出数模转换器 (DAC )，采用 2.7 V 至 5.5 V 单电源供电，通过设计保证单 调性。 这 些 器 件 均 内 置 一 个 片 内 基 准 电 压 源 。 AD5623R-3/ AD5643R-3/AD5663R-3内置一个1.25 V、5 ppm/°C基准电压 源，满量程输出范围可达到2.5 V；AD5623R-5/AD5643R-5/ AD5663R-5内置一个2.5 V、5 ppm/°C基准电压源，满量程输 出范围可达到5 V。上电时，片内基准电压源关闭，因而可 以用外部基准电压。所有器件均可以采用2.7 V至5.5 V单电 源供电。对DAC执行写操作将打开内部基准电压源。 上述器件均内置一个上电复位电路，确保DAC输出上电至 0 V并保持该电平，直到执行一次有效的写操作为止。此外 还具有省电特性，在省电模式下，器件在5 V时的功耗降至 480 nA，并提供软件可选输出负载。
SCLK SYNC DIN
AD5623R/AD5643R/AD5663R
POWER-ON RESET POWER-DOWN LOGIC
LDAC CLR
GND
图1.
表1. 相关器件
产品型号 AD5663 描述 2.7 V至5.5 V、双通道、16位nanoDAC， 集成外部基准电压源
产品特色
1. 双通道、12/14/16位DAC。 2. 1.25 V/2.5 V、5 ppm/ºC片内基准电压源。 3. 提供 10 引脚 MSOP 和 3 mm x 3 mm 、 10 引脚 LFCSP 两种 封装。 4. 低功耗：3 V时典型功耗为0.6 mW，5 V时为1.25 mW。 5. 建立时间(最大值)：4.5 μs (AD5623R)
第10章AD及D
2.ADC 0809接口与应用
图10-2 是ADC0809与8031单片机的一种常用接口电路图。8路模拟量的变化范围在0～5V间，ADC0809的 EOC转换结束信号接803l的外部中断1上，803l通过地址线P2.0和读、写信号来控制转换器的模拟量输入通 道地址锁存、启动和输出允许。模拟输入通道地址A、B、C由P0.0～P0.2经锁存器提供。ADC0809时钟输 入由单片机ALE经2分频电路获得，若单片机时钟频率符合要求，也可不加2分频电路。
MOVX ＠DPTR，A ；启动A／D LP： JB P3.3，LP ；等待A／D转换结束
MOV DPTR，#0FF0lH ；A／D高8位数据口地址A0=0，R／ ＝l MOVX A，＠DPTR ；读高8位数据 MOV ＠Rl，A ；存入片内RAM
INC R1 MOV DPTR，#0FF03H ；低4位数据口地址A0=1，R/ =1 MOVX A，＠DPTR ；读低4位数据 MOV ＠R1，A ；存入片内RAM
ADC0809是28引脚DIP封装的芯片，各引脚功能如下： IN0～IN7（8条）：8路模拟量输入，用于输入被转换的模拟电压。 D7～D0为数字量输出。 A、B、C：模拟输入通道地址选择线，其8位编码分别对应IN0～IN7，用于选择IN7～IN0上哪一路模拟电压 送给比较器进行A/D转换。
ALE：地址锁存允许，高电平有效。由低至高电平的正跳变将通道地址锁存至地址锁存器，经译码后控制八路 模拟开关工作。
②查询方式 A/D转换芯片有表明转换完成的状态信号，例如ADC0809的EOC端。因此，可以用查询方式，软件测试EOC的
AD主要指标
AD主要指标AD:模数转换,将模拟信号变成数字信号,便于数字设备处理.DA:数模转换，将数字信号转换为模拟信号与外部世界接口。
具体可以看看下面的资料，了解一下工作原理：1. AD转换器的分类下面简要介绍常用的几种类型的基本原理及特点：积分型、逐次逼近型、并行比较型/串并行型、∑-Δ调制型、电容阵列逐次比较型及压频变换型.1)积分型(如TLC7135）积分型AD工作原理是将输入电压转换成时间（脉冲宽度信号)或频率(脉冲频率），然后由定时器/计数器获得数字值。
其优点是用简单电路就能获得高分辨率，但缺点是由于转换精度依赖于积分时间，因此转换速率极低。
初期的单片AD转换器大多采用积分型，现在逐次比较型已逐步成为主流.2）逐次比较型(如TLC0831)逐次比较型AD由一个比较器和DA转换器通过逐次比较逻辑构成，从MSB开始，顺序地对每一位将输入电压与内置DA转换器输出进行比较，经n次比较而输出数字值.其电路规模属于中等。
其优点是速度较高、功耗低，在低分辩率（<12位）时价格便宜，但高精度（>12位）时价格很高。
3）并行比较型/串并行比较型（如TLC5510）并行比较型AD采用多个比较器，仅作一次比较而实行转换,又称FLash（快速）型。
由于转换速率极高，n位的转换需要2n—1个比较器，因此电路规模也极大，价格也高，只适用于视频AD转换器等速度特别高的领域.串并行比较型AD结构上介于并行型和逐次比较型之间，最典型的是由2个n/2位的并行型AD转换器配合DA转换器组成,用两次比较实行转换,所以称为Half flash(半快速)型。
还有分成三步或多步实现AD 转换的叫做分级（Multistep/Subrangling）型AD,而从转换时序角度又可称为流水线（Pipelined）型AD,现代的分级型AD中还加入了对多次转换结果作数字运算而修正特性等功能。
这类AD速度比逐次比较型高,电路规模比并行型小。
AD5542设计的高精度数控恒流源技
AD5542 设计的高精度数控恒流源技
本文给出了一种基于AD5542 设计的高精度数控恒流源电路，并已成功应用于陀螺和加速度计等测试中。
随着电子技术向各个领域的渗透，许多场合，尤其是高精度测控系统需要高精度、高稳定性的数控恒流源。
数控恒流源主要由D/A 来控制电流输出大小，恒流源的分辨率、精度、稳定性主要取决于D/A 芯片及其外围电路，因此要达到高精度、高稳定性的恒流源，必须在选器件上慎重考虑。
基本原理
该高精度数控恒流源的结构原理框图如图1 所示，它由总线端、数字隔离电路、D/A 转换电路、V/I 转换电路组成，D/A 采用16 位芯片AD5542，V/I 转换电路采用了高精度运放OP97 和三极管来实现。
图1 高精度数控恒流源的结构原理框图
硬件电路设计
1 D/A 转换电路
数字隔离电路采用专门的磁隔芯片，在此不作介绍。
AD5542 是ADI 公司的一款单通道、16 位、串行输入、电压输出数模转换器，采用5V 单电源供电。
采用多功能三线式接口，并且与SPI、QSPI、MICROWIRE、DSP 接口标准兼容。
可提供16 位性能，无须进行任何调整。
DAC 输出不经过缓冲，。
ADC的应用与编程
TLV2543转换时序图：
AD(TLV2543) 转换实验的编程
芮德华
北京精仪达盛科技有限公司
本讲主要内容：
(1)TLV2543简介 (2) Cortex-M3的GPIO模拟SPI控制TLV2543 转换的实现方法
(1)TLV2543简介
TLC2543是TI公司的12位串行模数转换器， 使用开关电容逐次逼近技术完成A/D转换过 程。 TLC2543具有4线制串行接口，分别为片选 端(CS)，串行数据输出端 (DATA OUT)。它可以直接与SPI器件进行 连接，不需要其他外部逻辑。同时，它还 在高达4MHz的串行速率下与主机进行通信。
TLC2543除了具有高速的转换速度外，片 内还集成了14路多路开关。其中n路为外部 模拟量输入，3路为片内自测电压输入。在 转换结束后，EOC引脚变为高电平，转换 过程中由片内时钟系统提供时钟，无需外 部时钟。在AD转换器空闲期间，可以通过 编程方式进入断电模式，此时器件耗电只 有25pA。
(2) Cortex-M3的GPIO模拟SPI控制 TLV2543转换的实现方法
编程要点： 1、GPIO的配置； 2、TLV2543转换通道的选择与转换时序。 注：GPIO的配置已经在前面讲过，在此不再 重复，可以参照前面的GPIO部分。
转换通道的选择：
如右图所示：通过输入 DATA INPUT管脚0-A来选择 我们所示用的AD转换通道。 具体在程序中采用左移四位 的方式来选择AD转换通道。
AD5554BRS中文资料
Symbol N INL DNL IOUTX IOUTX GFSE TCVFS RFBX VREFX RREFX RREFX CREFX IOUTX COUTX VIL VIH IIL CIL VOL VOH tCH tCL tCSS tCSH tPD tLDAC tDS tDH tLDS tLDH VDD RANGE IDD ISS PDISS PSS
元器件交易网
a
FEATURES AD5544 16-Bit Resolution AD5554 14-Bit Resolution 2 mA Full-Scale Current ؎ 20%, with VREF = ؎ 10 V 2 s Settling Time V SS BIAS for Zero-Scale Error Reduction @ Temp Midscale or Zero-Scale Reset Four Separate 4Q Multiplying Reference Inputs SPI-Compatible 3-Wire Interface Double Buffered Registers Enable Simultaneous Multichannel Change Internal Power ON Reset Compact SSOP-28 Package APPLICATIONS Automatic Test Equipment Instrumentation Digitally-Controlled Calibration
Quad, Current-Output Serial-Input, 16-Bit/14-Bit DACs AD5544/AD5554
FUNCTIONAL BLOCK DIAGRAM
AD5541A中文
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
REF
VLOGIC CS DIN
SCLK LDAC
功能框图
VDD
AD5541A
16-BIT DAC
16-BIT DAC LATCH
CONTROL LOGIC
SERIAL INPUT REGISTER
VOUT AGND
DGND
图1. 典型应用电路
08516-001
产品聚焦
1. 单电源供电。AD5541A的额定电源电压为2.7 V至5.5 V。 2. 低功耗。该器件采用5V电源时的典型功耗为0.625 mW，
微分非线性(DNL)
16
±0.5
±1.0
±0.5
±2.0
±0.5
±1.0
位
LSB
B级
LSB
A级
LSB
保证单调性
增益误差
0.5
增益误差温度系数
±0.1
零代码误差
0.3
零代码温度系数 直流电源抑制比
输出特性1
应用
自动测试设备 精密源测量仪器 数据采集系统 医疗仪器 航空航天仪器仪表 通信基础设施设备 工业控制
概述
AD5541A是一款单通道、16位、串行输入、无缓冲电压输 出数模转换器(DAC)，采用2.7 V至5.5 V单电源供电。
DAC输出范围为0V至VREF，可保证单调性，16位时能提 供1 LSB INL精度，在−40°C至+125°C的额定温度范围内无 需调整。
单片机ad转换的原理
单片机ad转换的原理
单片机AD转换的原理是根据输入电压的大小，通过一定的电路和算法将其转换为对应的数字信号。
其基本流程如下：
1. 参考电压的选择：首先需要确定一个参考电压，用于将输入电压映射到数字量。
单片机通常提供一个内部或外部的参考电压源，可以选择适合应用需求的参考电压。
2. 采样保持电路：在转换开始之前，需要对输入电压进行采样并保持其值稳定。
这通常通过一个采样保持电路来实现，它会将输入电压的瞬时值转换为一个持续的电压供给转换电路。
3. 转换电路：转换电路通常是由一组比较器、计数器和控制逻辑组成。
在采样保持电路稳定后，转换电路开始工作。
它以参考电压为基准，将输入电压与一系列离散的电压级别进行比较，然后确定输入电压所对应的数字值。
4. 输出数字信号：转换电路根据比较结果，将对应的数字值输出，通常以二进制形式表示。
这个数字信号可以与其他单片机模块进行数据传输、处理和控制。
需要注意的是，AD转换存在一定的精度和分辨率，即能够准
确表示输入电压的范围和精度。
根据单片机型号和应用需求的不同，AD转换的位数（最高位数）和精度（有效位数）会有
所不同。
AD5552BR资料
LOGIC INPUTS
Input Current
VINL, Input Low Voltage VINH, Input High Voltage Input Capacitance3 Hysteresis Voltage3
The AD5551 and AD5552 are available in an SO package.
FUNCTIONAL BLOCK DIAGRAMS
VREF
AD5551
VDD 14-BIT DAC
VOUT
CS DIN
SCLK
CONTROL LOGIC
14-BIT DATA LATCH SERIAL INPUT REGISTER
VDD
V
kΩ
kΩ
Unipolar Operation AD5552 Bipolar Operation to 1/2 LSB of FS, CL = 10 pF CL = 10 pF, Measured from 0% to 63% 1 LSB Change Around the Major Carry All 1s Loaded to DAC, VREF = 2.5 V Tolerance Typically 20% ∆VDD ± 10%
元器件交易网
AD5551/AD5552–SPECIFICATIONS (VDD = 5 V ؎ 10%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless otherwise noted.)
With an external op amp the AD5552 can be operated in bipolar mode generating a ± VREF output swing. The AD5552 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. For higher precision applications, please refer to 16-bit DACs AD5541, AD5542, and AD5544.
电流输出型DA转换器AD5545的原理应用及编程
电流输出型DA转换器AD5545的原理应用及编程————————————————————————————————作者：————————————————————————————————日期：电流输出型DA转换器AD5545的原理，应用及编程原理：图1DA转换器内部结构图用作DA转换时，推荐系统连接如图所示，ADR03提供2.5V的参考电压。
上述电路图，在本质上相当于一个反相放大器，构成反相放大的两个电阻为Rfb与Iout之间的等效电阻R1，Vref和Iout之间的等效电阻R2。
则有21RRVrefVout⨯-=，通常情况下，忽略芯片本身影响，则有655362221NNRNRRRnn===，所以有65536NVrefVout⨯-=。
当用作可编程增益放大器时，一般外部都配接一个运放，构成如图2所示电路，而图2在本质上也相当于一个反相放大电路，如图3所示。
VinRfbIout GNDVrefVoutDinIout Rfb VrefVout(Vin)图2 可编程增益电路 图3 等效电路则有增益FBEQ R R Vin VoutG -==， 其中R EQ 为Vref 引脚到Iout 引脚间的等效电阻，其值与数字量D 有关；R FB 为R FB 引脚到I out 引脚间的电阻值。
有NR R in n EQ2=（n ：DAC 的位数；N ：输入的二进制数；Rin ：输入阻抗）假设，芯片本身的增益误差为0，即Rin=Rfb ，则有NR N Rin Vin Vout G n FB n 22-=-== 记nN D 2=，即有VinD Vout 1-=，即放大倍数为D 1。
则有NVin Vout 65536⨯-=将DA 转换器用作双极性输出：电路如图4所示，其在本质上的等效电路如图5所示。
图4 双极性输出4.99K10K 10KVout2Vout1RFBREQ VrefVref（Iout ）图5 等效电路图5中R EQ 为Vref 引脚到Iout 引脚间的等效电阻，其值与数字量D 有关；R FB 为R FB引脚到I out 引脚间的电阻值。
AD5541程序
在本任务中，选择P2端口作为数据输出端口与
DAC0832相连，因此在程序中的输出的数据就只
需要写在P2口就行了。 DAC0832需要使用运放将其电流输出转换为
电压输出，本任务中没有规定输出信号的幅度和
频率，为了方便，将输出确定为正电压输出，幅
度为VCC（＋5V），即将DAC0832的VREF接至
VCC。
for(i=250;i>0;i--)
DAC0832(i); } //三角波的下降沿
2.正弦波的输出 不三角波相似，通过DAC0832也只能输出近 似的正弦波。正弦波如果采用计算的方式来获得
需要输出的数字量，计算正弦值需要较多的程序
代码和计算时间，一般采用查表的方法来获得正
弦值。方法是将900～2700的正弦值放在数组中，
ET0=1; IT0=1; IT1=1; EX0=1; EX1=1; EA=1; TR0=1; flag=0; i=0;
while(1) { if(time==1) //时间到 { time=0; if(i>249) i=0;
else i++; //指向下一个点
switch(flag) //判断标志
GND
Din P1.3 SCLK P1.2
P1.4 CS
设定AD5541的VREF为2.5V。 如果向AD5541写入数据D时，AD5541
输出电压为 Vout= VREF X Din/2n
=2.5V X D/216 =D X 2.5/65536(V) 串行D/A转换应用：在AD5541的第一脚输出一 个变化为0.01V(对应数值变化为262）的阶梯波
的增大或减小，模/数转换器输出模拟量也随之增
大或减小，从模/数转换器输出的三角波丌是理想 才可以看作是线性增长（降低）的。
AD5545资料
Dual, Current-Output,Serial-Input, 16-/14-Bit DACAD5545/AD5555 Rev.0Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2003 Analog Devices, Inc. All rights reserved.FEATURES16-bit resolution AD554514-bit resolution AD5555±1 LSB DNL monotonic±2 LSB INL AD55452 mA full-scale current ±20%, with V REF = 10 V0.5 µs settling time2Q multiplying reference-input 4 MHz BWZero or midscale power-up presetZero or midscale dynamic reset3-wire interfaceCompact TSSOP-16 packageAPPLICATIONSAutomatic test equipmentInstrumentationDigitally controlled calibrationIndustrial control PLCsProgrammable attentuatorPRODUCT OVERVIEWThe AD5545/AD5555 are 16-bit/14-bit, current-output, digital-to-analog converters designed to operate from a single 5 V supply with bipolar output up to ±15 V capability.An external reference is needed to establish the full-scale out-put-current. An internal feedback resistor (R FB) enhances the resistance and temperature tracking when combined with an external op amp to complete the I-to-V conversion.A serial data interface offers high speed, 3-wire microcontroller compatible inputs using serial data in (SDI), clock (CLK), and chip select (CS). Additional LDAC function allows simultane-ous update operation. The internal reset logic allows power-on preset and dynamic reset at either zero or midscale, depending on the state of the MSB pin.The AD5545/AD5555 are packaged in the compact TSSOP-16 package and can be operated from –40°C to +85°C.FUNCTIONAL BLOCK DIAGRAMFB AOUT AGND AFB BOUT BGND BFigure 1.AD5545/AD5555 TABLE OF CONTENTSAD5545/AD5555—Electrical Characteristics (3)Absolute Maximum Ratings (5)Pin Configuration And Functional Descriptions (6)Typical Performance Characteristics (9)Circuit Operation (11)D/A Converter Section (11)Serial Data Interface (11)Power-Up Sequence (12)Layout and Power Supply Bypassing (12)Grounding...................................................................................12Applications. (13)Stability (13)Positive Voltage Output (13)Bipolar Output (13)Programmable Current Source (13)DAC with Programmable Input Reference Range (14)Outline Dimensions (16)ESD Caution (16)Ordering Guide (16)REVISION HISTORYRevision 0: Initial VersionRev. 0 | Page 2 of 16AD5545/AD5555 AD5545/AD5555—ELECTRICAL CHARACTERISTICSTable 1. V DD = 5 V ± 10%, I OUT = Virtual GND, GND = 0 V, V REF = 10 V, T A = Full Operating Tempearture Range,1 All static performance tests (except I OUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 R FB terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C.2 These parameters are guaranteed by design and not subject to production testing.3 All ac characteristic tests are performed in a closed-loop system using an O42 I-to-V converter amplifier.4 All input control signals are specified with t R = t F = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.Rev. 0 | Page 3 of 16AD5545/AD5555Rev. 0 | Page 4 of 16AD5545/AD5555 ABSOLUTE MAXIMUM RATINGSTable 2. AD5545/AD5555 Absolute Maximum RatingsParameter Rating V DD to GND –0.3 V, +8 VV REF to GND –18 V, +18 VLogic Inputs to GND –0.3 V, +8 VV(I OUT) to GND –0.3 V, V DD + 0.3 VInput Current to Any Pin except Supplies ±50 mAPackage Power Dissipation (T J max – T A)/ θJAThermal Resistance θJA16-Lead TSSOP 150°C/WMaximum Junction Temperature (T J max) 150°COperating Temperature Range –40°C to +85°CStorage Temperature Range –65°C to +150°CLead TemperatureRU-16 (Vapor Phase, 60 sec) 215°CRU-16 (Infrared, 15 sec) 220°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification isnot implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Rev. 0 | Page 5 of 16AD5545/AD5555PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONSV REF R FB A GND I OUT R FB A GND I OUT V REF 02918-0-002Figure 2. 16-Lead TSSOPRev. 0 | Page 6 of 16AD5545/AD5555Rev. 0 | Page 7 of 1602918-0-003LDACLDHFigure 3. AD5545 18-Bit Data Word Timing Diagram02918-0-004LDACLDHFigure 4. AD5555 16-Bit Data Word Timing DiagramNOTES1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.2. At power-on, both the input register and the DAC register are loaded with all 0s.AD5545/AD5555NOTES1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.2. At power-on, both the input register and the DAC register are loaded with all 0s.Table 6. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First FormatMSB LSB Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 BitDataWord A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note that only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when thereturns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the pin can be tied logic low to disable the DAC registers.Table 7. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First FormatMSB LSB Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 BitWord A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DataNote that only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the pin can be tied logic low to disable the DAC registers.Table 8. Address DecodeA1 A0 DAC Decoded0 0 NoneA0 1 DACB1 0 DAC1 1 DAC A and DAC BRev. 0 | Page 8 of 16AD5545/AD5555TYPICAL PERFORMANCE CHARACTERISTICS1.00.80.608192163842457632768409604915257344655360.40.2–0.2–0.4–0.6–0.8–1.0INL(LSB)CODE(Decimal)02918-0-009Figure 5. AD5545 Integral Nonlinearity Error1.00.80.608192163842457632768409604915257344655360.40.2–0.2–0.4–0.6–0.8–1.0DNL(LSB)CODE (Decimal)02918-0-010Figure 6. AD5545 Differential Nonlinearity Error1.00.80.602048409661448192102401228814336163840.40.2–0.2–0.4–0.6–0.8–1.0INL(LSB)CODE (Decimal)02918-0-011Figure 7. AD5555 Integral Nonlinearity Error1.00.80.600248409661448192102401228814336163840.40.2–0.2–0.4–0.6–0.8–1.0DNL(LSB)CODE (Decimal)02918-0-012Figure 8. AD5555 Differential Nonlinearity Error1.51.024GEDNLINL680.5–0.5–1.0–1.5LINEARITYERROR(LSB)SUPPLY VOLTAGE V DD (V)V REF=2.5VT A=25°C02918-0-01310Figure 9. Linearity Errors vs. V DD54321SUPPLYCURRENTIDD(LSB)LOGIC INPUT VOLTAGE V IH (V)02918-0-014Figure 10. Supply Current vs. Logic Input VoltageRev. 0 | Page 9 of 16AD5545/AD5555Rev. 0 | Page 10 of 163.02.52.01.51.00.50S U P P L Y C U R R E N T (m A )CLOCK FREQUENCY (Hz)02918-0-015Figure 11. Supply Current vs. Clock Frequency9070504060803010200P S S R (-d B )FREQUENCY (Hz)02918-0-016Figure 12. Power Supply Rejection Ration vs. Frequency0xFFFF 0x80000x4000–12dB –24dB –36dB –48dB –60dB –72dB –84dB –96dB –108dB0x20000x10000x08000x04000x02000x01000x00800x00400x00200x00100x00080x00040x00020x00010x0000101001k100k 10k1M 10M START 10.000HzSTOP 50 000 000.000HzREF LEVEL 0.000dB/DIV12.000dBMARKER 4 41 677.200Hz MAG (A/R)–2.939db02918-0-017Figure 13. Reference Multiplying Bandwidth02918-0-018V OUTCSFigure 14. Settling Time00.5 1.0 1.52.0 2.53.0 3.54.0 4.55.0TIME (µs)V OUT (50mV/DIV)CS (5V/DIV)02918-0-019Figure 15. Midscale Transition and Digital FeedthroughCIRCUIT OPERATIONThe AD5545/AD5555 contain a 16-/14-bit, current-output, digital-to-analog converter, a serial-input register, and a DAC register. Both parts require a minimum of a 3-wire serial data interface with additional LDAC for dual channel simultaneous update.D/A CONVERTER SECTIONThe DAC architecture uses a current-steering R-2R ladder design. Figure 16 shows the typical equivalent DAC. The DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The R FB pin is connected to the output of the external amplifier. The I OUT terminal is connected to the inverting input of the external amplifier. These DACs are designed to operate with both negative or positive reference voltages. The V DD power pin is used only by the logic to drive the DAC switches ON and OFF. Note that a matching switch is used in series with the internal 5 kΩ feedback resistor. If users attempt to measure the R FB value, power must be applied to V DD to achieve continuity. The V REF input voltage and the digital data (D ) loaded into the corresponding DAC register, according to Equation 1 and Equation 2, determine the DAC output voltage.536,65/–D V V REF OUT ×= (1) 384,16/–D V V REF OUT ×= (2) Note that the output full-scale polarity is the opposite of theV REFpolarity for dc reference voltages.V DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:SWITCHES S1 AND S2 ARE CLOSED, V DD MUST BE POWEREDDDFBOUT02918-0-005Figure 16. Equivalent R-2R DAC CircuitThese DACs are also designed to accommodate ac reference input signals. The AD5545/AD5555 will accommodate input reference voltages in the range of –12 V to +12 V . The reference voltage inputs exhibit a constant nominal input-resistance value of 5 kΩ, ±30%. The DAC output (I OUT ) is code dependent, producing various output resistances and capacitances. When choosing an external amplifier, the user should take into account the variation in impedance generated by theAD5545/AD5555 on the amplifiers inverting input node. The feedback resistance in parallel with the DAC ladder resistance dominates output voltage noise.VSWITCHES S1 AND S2 ARE CLOSED, V DD MUST BE POWERED02918-0-006Figure 17. Recommended System ConnectionsSERIAL DATA INTERFACEThe AD5545/AD5555 use a minimum 3-wire (CS , SDI, CLK) serial data interface for single channel update operation. With Table 4 as an example (AD5545), users can tie LDAC low and RS high, then pull CS low for an 18-bit duration. New serial data is then clocked into the serial-input register in an 18-bit data-word format with the MSB bit loaded first. Table 5 defines thetruth table for the AD5555. Data is placed on the SDI pin andclocked into the register on the positive clock edge of CLK. Forthe AD5545, only the last 18-bits clocked into the serial registerwill be interrogated when the CS pin is strobed high, transfer-ring the serial register data to the DAC register and updating the output. If the applied microcontroller outputs serial data in different lengths than the AD5545, such as 8-bit bytes, three right justified data bytes can be written to the AD5545. The AD5545 will ignore the six MSB and recognize the 18 LSB asvalid data. After loading the serial register, the rising edge of CS transfers the serial register data to the DAC register and updates the output; during the be toggled.If users want to program each channel separately but update them simultaneously, they need to program LDAC and RS high initially, then pull CS low for an 18-bit duration and program DAC A with the proper address and data bits. CS is then pulled high to latch data to the DAC A register. At this time, the output is not updated. To load DAC B data, pull CS low for an 18-bit dura-tion and program DAC B with the proper address and data, then pull CS high to latch data to the DAC B register. Finally, pull LDAC low and then high to update both the DAC A and DAC B outputs simultaneously.Table 8 shows that each DAC A and DAC B can be individually loaded with a new data value. In addition, a common new data value can be loaded into both DACs simultaneously by setting Bit A1 = A0 = high. This command enables the parallel combination of both DACs, with I OUT A and I OUT B tied together, to act as one DAC with significant improved noise performance.LAYOUT AND POWER SUPPLY BYPASSINGIt is a good practice to employ compact, minimum lead length layout design. The input leads should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electro-lytic capacitors should also be applied at V DD to minimize any transient disturbance and to filter any low frequency ripple (see Figure 19). Users should not apply switching regulators for V DD due to the power supply rejection ratio degradation over frequency.ESD Protection CircuitsAll logic input pins contain back-biased ESD protection Zeners connected to digital ground (DGND) and V DD as shown in Figure 18.V02918-0-007AD5545/V 02918-0-008Figure 18. Equivalent ESD Protection CircuitsPOWER-UP SEQUENCEIt is recommended to power-up V DD and ground prior to any reference voltages. The ideal power-up sequence is A GND X,DGND, V DD , V REF X, and digital inputs. A noncompliance power-up sequence can elevate reference current, but the device will resume normal operation once V DD is powered. Figure 19. Power Supply Bypassing and Grounding ConnectionGROUNDINGThe DGND and A GND X pins of the AD5545/AD5555 refer to the digital and analog ground references. To minimize the digital ground bounce, the DGND terminal should be joined remotely at a single point to the analog ground plane (see Figure 19).APPLICATIONSSTABILITYV 02918-0-020Figure 20. Operational Compensation Capacitor for Gain Peaking PreventionIn the I-to-V configuration, the I OUT of the DAC and the invert-ing node of the op amp must be connected as close as possible, and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP , and if there is exces-sive parasitic capacitance at the inverting node.An optional compensation capacitor, C1, can be added for sta-bility as shown in Figure 20. C1 should be found empirically, but 20 pF is generally more than adequate for the compensation.POSITIVE VOLTAGE OUTPUTTo achieve the positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resis-tors’ tolerance errors. To generate a negative reference, the reference can be level shifted by an op amp such that the V OUT and GND pins of the reference become the virtual ground and –2.5 V , respectively (see Figure 21).02918-0-021O U2Figure 21. Positive Voltage Output ConfigurationBIPOLAR OUTPUTThe AD5545/AD5555 is inherently a 2-quadrant multiplying D/A converter. It can easily set up for unipolar output opera-tion. The full-scale output polarity is the inverse of the reference input voltage.In some applications, it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This is easily accomplished by using an additional external amplifier, U4, configured as a summing amplifier (see Figure 22). In thiscircuit, the second amplifier, U4, provides a gain of +2, which increases the output span magnitude to 5 V . Biasing the external amplifier with a 2.5 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created because the input data (D ) is incremented from code zero (V OUT = –2.5 V) to midscale (V OUT = 0 V) to full scale (V OUT = +2.5 V).()(55451–768,32/AD V D V REFOUT ×)= (3)()(55551–384,16/AD V D V REFOUT ×)= (4)For the AD5545, the external resistance tolerance becomes the dominant error that users should be aware of.02918-0-022U2Figure 22. Four-Quadrant Multiplying Application CircuitPROGRAMMABLE CURRENT SOURCEFigure 23 shows a versatile V-to-I conversion circuit using improved Howland Current Pump. In addition to the precision current conversion it provides, this circuit enables a bidirec-tional current flow and high voltage compliance. This circuit can be used in a 4 mA to 20 mA current transmitter with up to a 500 Ω of load. In Figure 23, it shows that if the resistor net-work is matched, the load current is()D V 3132REF ××+=R R R R I L (5)R 3, in theory, can be made small to achieve the current needed within the U3 output current driving capability. This circuit is versatile such that the AD8510 can deliver ±20 mA in both directions, and the voltage compliance approaches 15 V , which is mainly limited by the supply voltages of U3. However, users must pay attention to the compensation. Without C1, it can be shown that the output impedance becomes()()()321–3212131R R R R R R R R R R Z O +′′+′+′=(6)If the resistors are perfectly matched, Z O is infinite, which is desirable, and the resistors behave as an ideal current source. On the other hand, if they are not matched, Z O can be either positive or negative. The latter can cause oscillation. As a result, C1 is needed to prevent the oscillation. For critical applications, C1 could be found empirically but typically falls in the range of a few pF. R WB and R WA are digital potentiometer 128-step programmable resistances and are given byAB CWB R D R 128≈ (8) AB CWA R D R 128128−≈(9)CC WA WBD D R R −≈128 (10)V 02918-0-023where D C = Digital Potentiometer Digital Code in Decimal (0 ≤ D C ≤ 127).By putting Equations 7 through 10 together, the following results:C C N AC C REF REFD D D D D V AB V −×−−+×=128211281 (11) Table 9 shows a few examples of V REF AB of the 14-bit AD5555. Table 9. V REF AB vs. D B and D C of the AD5555D C D AV REF AB 0 X V REF32 0 1.33 V REF32 8192 1.6 V REF64 0 2 V REF64 8192 4 V REF96 0 4 V REF96 8192–8 V REFFigure 23. Programmable Current Source with BidirectionalCurrent Control and High Voltage Compliance CapabilitiesDAC WITH PROGRAMMABLE INPUT REFERENCE RANGESince high voltage references can be costly, users may consider using one of the DACs, a digital potentiometer, and a low voltage reference to form a single-channel DAC with aprogrammable input reference range. This approach optimizes the programmable range as well as facilitates future system upgrades with just software changes. Figure 24 shows this implementation. V REF AB is in the feedback network, therefore,The output of DAC B is, therefore,NBREF OB D ABV V 2−= (12) where D B is the DAC B digital code in decimal.The accuracy of V REF AB will be affected by the matching of the input and feedback resistors and, therefore, a digital potenti-ometer is used for U4 because of its inherent resistance matching. The AD7376 is a 30 V or ±15 V , 128-step digital potentiometer. If 15 V or ±7.5 V is adequate for the application, a 256-step AD5260 digital potentiometer can be used instead.×× +×=WA WB N A REF_AB WA WB REF REF R R 2D V R R V AB V ––1 (7) where:V REF AB = Reference Voltage of V REF A and V REF B V REF = External Reference Voltage D A = DAC A Digital Code in Decimal N = Number of Bits of DACFigure 24. DAC with Programmable Input Reference RangeOUTLINE DIMENSIONSPLANECOPLANARITY0.10COMPLIANT TO JEDEC STANDARDS MO-153ABFigure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)—Dimensions shown in millimetersESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performancedegradation or loss of functionality.ORDERING GUIDEAD5545/AD5555 ProductsINL LSBDNL LSBRES (Bits) Temperature RangePackage Description Package Outline Qty AD5545BRU*±2 ±1 16 –40°C to +85°C TSSOP-16 RU–16 96 AD5545BRU–REEL7 ±2 ±1 16 –40°C to +85°C TSSOP-16 RU–16 1000 AD5555CRU±1 ±1 14 –40°C to +85°C TSSOP-16 RU–16 96 AD5555CRU–REEL7±1±114–40°C to +85°CTSSOP-16RU–161000*The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil.© 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis-tered trademarks are the property of their respective companies. C02918-0-7/03(0)。
STC系列单片机内部AD的应用
STC系列单片机内部AD的应用STC89LE52AD、54AD、58AD、516AD这几款89系列的STC单片机内部自带有8路8位的AD转换器，分布在P1口的8位上，当时钟在40MHz以下时，每17个机器周期可完成一次AD转换。
与AD相关的几个寄存器如表1所示。
表1 STC89系列单片机AD相关寄存器P1_ADC_EN：P1.X口的AD使能寄存器。
相应位设置为“1”时，对应的P1. X口作为AD转换使用，内部上拉电阻自动断开。
ADC_CONTR：AD 转换控制寄存器。
ADC_START：AD转换启动控制位，设置为“1”时，AD开始转换。
ADC_FLAG：AD转换结束标志位，当AD转换完成后，ADC_FLAG=1。
CHS2、CHS1、CHS0：为模拟输入通道选择，如表2所示。
表2 STC89系列单片机AD模拟通道选择设置ADC_DATA：AD 转换结果寄存器。
模拟/数字转换结果计算公式如下：结果=256×Vin / VccVin为模拟输入通道输入电压，Vcc为单片机实际工作电压，用单片机工作电压作为模拟参考电压。
下面一个例程演示STC89LE516AD/X2系列单片机的A/D转换功能。
时钟11.0592MHz，转换结果以16进制形式输出到串行口，可以用串行口调试程序观察输出结果。
(本代码摘自宏晶科技芯片手册，经作者调试可正常运行)。
新建文件part3.4.5.c，程序代码如下：#include <reg52.H>#include <intrins.H>// 定义与 ADC 有关的特殊功能寄存器sfr P1_ADC_EN = 0x97; //A/D转换功能允许寄存器sfr ADC_CONTR = 0xC5; //A/D转换控制寄存器sfr ADC_DATA = 0xC6; //A/D转换结果寄存器typedef unsigned char INT8U;typedef unsigned int INT16U;void delay(INT8U delay_time) // 延时函数{INT8U n;INT16U m;for (n=0;n<delay_time;n++){for(m=0;m<10000;m++);}}void initiate_RS232(void) //串口初始化{ES = 0; // 禁止串口中断SCON = 0x50; // 0101,0000 8 位数据位，无奇偶校验T2CON = 0x34; // 0011，0100，由T2 作为波特率发生器RCAP2H = 0xFF; // 时钟11.0592MHz, 9600 波特率RCAP2L = 0xDB;ES = 1; // 允许串口中断}void Send_Byte(INT8U one_byte) // 发送一个字节{TI = 0; // 清零串口发送中断标志SBUF = one_byte;while (TI == 0);TI = 0; // 清零串口发送中断标志}INT8U get_AD_result(INT8U channel){INT8U AD_finished = 0; // 存储 A/D 转换标志ADC_DATA = 0;ADC_CONTR = channel; // 选择 A/D 当前通道delay(1); //使输入电压达到稳定ADC_CONTR |= 0x08; //0000,1000 令 ADC_START = 1, 启动A/D 转换AD_finished = 0;while ( AD_finished == 0 ) // 等待A/D 转换结束{AD_finished = (ADC_CONTR & 0x10); //0001,0000, ADC_FLAG ==1测试A/D转换结束否}ADC_CONTR &= 0xF7; //1111,0111 令 ADC_START = 0, 关闭A/D 转换,return (ADC_DATA); // 返回 A/D 转换结果}void main(){initiate_RS232();P1 = P1 | 0x63; // 0110,0011,要设置为 A/D 转换的P1.x 口,先设为高P1_ADC_EN = 0x63; //0110,0011, P1 的P1.0,P1.1,P1.5,P1.6 设置为 A/D 转换输入脚// 断开P1.0,P1.1,P1.5,P1.6 内部上拉电阻while(1){Send_Byte(get_AD_result(0)); //P1.0 为 A/D 当前通道, 测量并发送结果delay(0x200);Send_Byte(get_AD_result(1)); //P1.1 为 A/D 当前通道, 测量并发送结果delay(0x200);Send_Byte(get_AD_result(5)); //P1.5 为 A/D 当前通道, 测量并发送结果delay(0x200);Send_Byte(get_AD_result(6)); //P1.6 为 A/D 当前通道, 测量并发送结果delay(0x200);Send_Byte(0); // 连续发送 4 个 00H, 便于观察输出显示Send_Byte(0);Send_Byte(0);Send_Byte(0);delay(0x200); // 延时delay(0x200);delay(0x200);delay(0x200);delay(0x200);delay(0x200);}}知识点：typedef与#define的区别typedef：类型定义，其功能是用户为已有数据类型取“别名”。
AD5543_5553_cn电流输出DAC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2002–2012 Analog Devices, Inc. All rights reserved.
INL (LSB)
图1.
1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8
概述
AD5543/AD5553分别是16/14位、低功耗、电流输出、小尺 寸数模转换器(DAC)，设计采用5 V单电源供电，并在±10 V 乘法基准电压下工作。 满量程输出电流由所施加的外部基准电压 (VREF)决定。与 外部运算放大器一起使用时，内部反馈电阻(RFB)支持R-2R 和温度跟踪，以便进行电压转换。 串行数据接口利用串行数据输入(SDI)、时钟(CLK)和芯片 选择(CS)引脚，提供高速、三线式微控制器兼容型输入。 AD5543/AD5553采用超紧凑(3 mm × 4.7 mm) 8引脚MSOP和 8引脚SOIC封装。
电流输出/串行输入、16位/14位DAC
AD5543/AD5553
产品特性
16位分辨率AD5543 AD5553：14位分辨率 ±1 LSB DNL ±1 LSB INL 低噪声：12 nV/√Hz 低功耗：IDD = 10 µA 建立时间：0.5 µs 四象限乘法基准电压输入 满量程电流：2 mA ± 20%，VREF = 10 V 内置RFB便于电压转换 三线式接口 超紧凑型8引脚MSOP和8引脚SOIC封装
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RFIF IC选型指南
ADL5521 ADL5523
1
可调偏置， 3 mm × 3 mm、 8引脚 LFCSP 只需极少的外部元件 可调偏置， 3 mm × 3 mm、 8引脚 LFCSP 只需极少的外部元件
包括外部输入匹配。
/zh/RF
| 5
RF/IF 差分放大器
产品型号 AD8350-15 AD8350-20 AD8351 –3 dB 带宽(MHz) 900 700 2200 (A V = 12 dB) 2200 (A V = 10 dB) 630 增益 (dB) 15 20 0 至 26 二/三阶失真 (dBc) –66/–65 (50 MHz) –65/–66 (50 MHz) –79/–81 (70 MHz) –83/–83 (100 MHz) –85/–92 (200 MHz) –82/–91 (200 MHz) –68/–64 (70 MHz) –65/–62 (70 MHz) –78/–85 (65 MHz) –95/–87 (140 MHz) –104/–87 (140 MHz) –108/–109 (100 MHz) 输出 IP3 (dBm) 28 (50 MHz) 28 (50 MHz) 31 (70 MHz) 41 (140 MHz) 51 (70 MHz) 50 (70 MHz) 19.5 (70 MHz) 35 (70 MHz) 35 (65 MHz) +49 (140 MHz) 47 (140 MHz) 53 (100 MHz) 噪声系数 输入噪声 电源电压 (dB) (nV/√Hz) (V) 6.8 5.6 10 1.7 1.7 2.7 4 至 11 4 至 11 3 至 5.5 电源电流 (mA) 28 28 28 封装 3.1 mm × 5.05 mm、 8引脚 SOIC/MSOP 3.1 mm × 5.05 mm、 8引脚 SOIC/MSOP 3 mm × 4.9 mm、 10引脚 MSOP 3 mm × 3 mm、 16引脚 LFCSP 4 mm × 4 mm、 24引脚 LFCSP 5 mm × 5 mm、 32引脚 LFCSP 5.1 mm × 6.4 mm、 16引脚 TSSOP 5.1 mm × 6.4 mm、 16引脚 TSSOP 5 mm × 5 mm、 32引脚 LFCSP 3 mm × 3 mm、 16引脚 LFCSP 3 mm × 3 mm、 16引脚 LFCSP 3 mm × 3 mm、 16引脚 LFCSP 备注 固定增益、 差分输入/输出 固定增益、 差分输入/输出 可利用外部电阻 调整增益 可利用外部电阻调整 增益/超低失真 差分输入/输出数字 增益放大器 差分输入/输出、 双通道、 数字增益放大器 差分输入/输出 差分输入/输出 差分输入/输出、 通道 引脚绑定增益调整、 超低失真 引脚绑定增益调整、 超低失真 引脚绑定增益调整、 超低失真
输出、无缓冲 16位DAC AD5541A
Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.功能框图V V LOGICDIN REFSCLK CS LDACV OUT AGND08516-001表1. 相关器件产品型号 描述AD5541AD5024/ AD5044/ AD5064 AD5062AD5063 AD5061AD5040/AD5060特性完全16位性能2.7 V 至5.5 V 单电源供电低功耗：0.375 mW (3 V)建立时间：1 μs温度范围：−40°C 至+125°C 低毛刺：1.1 nV-s50 MHz SPI/QSPI/MICROWIRE/DSP 兼容接口标准上电复位可将DAC 输出清零至零电平采用10引脚MSOP 封装硬件LDAC 功能5 kV HBM ESD 额定值应用自动测试设备精密源测量仪器数据采集系统医疗仪器航空航天仪器仪表通信基础设施设备工业控制产品聚焦1. 单电源供电。
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1.0 0.8 0.6 0.4 0.2
0 –0.2 –0.4 –0.6 –0.8 –1.0
0 4096 8152 12288 16384 20480 24575 28672 32768 36864 40960 45056 49152 53248 57344 61440 65536
CODE
Figure 1. Integral Nonlinearity Error
FUNCTIONAL BLOCK DIAGRAM
VDD VREF
CS
CLK SDI
AD5543/AD5553
CONTROL LOGIC
D/A CONVERTER
16 OR 14
DAC REGISTER
16 OR 14
16-/14-BIT SHIFT REGISTER
RFB IOUT
GND
INL – LSB
GENERAL DESCRIPTION The AD5543/AD5553 are precision 16-/14-bit, low power, current output, small form factor digital-to-analog converters. They are designed to operate from a single 5 V supply with a ± 10 V multiplying reference. The applied external reference VREF determines the full-scale output current. An internal feedback resistor (RFB) facilitates the R-2R and temperature tracking for voltage conversion when combined with an external op amp. A serial-data interface offers high speed, 3-wire microcontroller compatible inputs using serial data in (SDI), clock (CLK), and chip select (CS). The AD5543/AD5553 are packaged in ultracompact (3 mm ϫ 4.7 mm) MSOP-8 and SOIC-8 packages.
Parameter
Symbol Condition
5 V ؎ 10% Unit
STATIC PERFORMANCE1 Resolution
Relative Accuracy
Differential Nonlinearity Output Leakage Current
Full-Scale Gain Error Full-Scale Tempco2
AC CHARACTERISTICS4 Output Voltage Settling Time
Reference Multiplying BW DAC Glitch Impulse
Feedthrough Error Digital Feedthrough Total Harmonic Distortion Output Spot Noise Voltage
a
Current Output/ Serial Input, 16-/14-Bit DAC
AD5543/AD5553
FEATURES 16-Bit Resolution AD5543 14-Bit Resolution AD5553 ؎1 LSB DNL ؎2 LSB INL for AD5543 ؎1 LSB INL for AD5553 Low Noise 12 nV/√Hz Low Power, IDD = 10 A 0.5 s Settling Time 4Q Multiplying Reference-Input 2 mA Full-Scale Current ؎ 20%, with VREF = 10 V Built-in RFB Facilitates Voltage Conversion 3-Wire Interface Ultracompact MSOP-8 and SOIC-8 Packages APPLICATIONS Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs
Tel: 781/329-4700
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD5543/AD5553–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VDD = 5 V ؎ 10%, VSS = 0 V, IOUT = Virtual GND, GND = 0 V, VREF = 10 V, TA = Full operating temperature range, unless otherwise noted.)
4.5/5.5 10 0.055 0.006
0.5
V min/max µA max mW max %/% max
µs typ
4
MHz typ
7
nV-s typ
–65
dB
7
பைடு நூலகம்
nV-s typ
–85
dB typ
12
nV/√Hz
NOTES 1All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 R FB terminal is tied to the amplifier output. The op amp +IN is grounded and the DAC I OUT is tied to the op amp –IN. Typical values represent average readings measured at 25 °C. 2These parameters are guaranteed by design and are not subject to production testing. 3All ac characteristic tests are performed in a closed-loop system using an AD841 I-to-V converter amplifier. 4All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
VDD RANGE IDD PDISS PSS
tS
BW Q
VOUT/VREF Q THD eN
Logic Inputs = 0 V Logic Inputs = 0 V ∆VDD = ± 5%
To ± 0.1% of Full Scale, Data = 0000H to FFFFH to 0000H for AD5543 Data = 0000H to 3FFFH to 0000H for AD5553 VREF = 5 V p-p, Data = FFFFH VREF = 0 V, Data = 7FFFH to 8000H for AD5543 Data = 1FFFH to 2000H for AD5553 Data = 0000H, VREF = 100 mV rms, same channel CS = 1, and fCLK = 1 MHz VREF = 5 V p-p, Data = FFFFH, f = 1 kHz f = 1 kHz, BW = 1 Hz
REFERENCE INPUT
VREF Range Input Resistance Input Capacitance2
VREF RREF CREF
–15/+15 5 5
V min/max kΩ typ3
pF typ
ANALOG OUTPUT Output Current
Output Capacitance2
N
INL
DNL IOUT
GFSE TCVFS
1 LSB = VREF/216 = 153 µV when VREF = 10 V AD5543 1 LSB = VREF/214 = 610 µV when VREF = 10 V AD5553 Grade: AD5553C
Grade: AD5543B
Clock to CS Hold
tCSH
Data Setup
tDS
Data Hold
tDH
0.8
V max
2.4
V min
10
µA max
10
pF max
50
MHz
10
ns min
10
ns min
0
ns min
10
ns min
5
ns min
10
ns min
SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Power Dissipation Power Supply Sensitivity