毕业设计-CMOS运算放大器版图设计

摘要

集成电路掩膜版图设计是实现电路制造所必不可少的设计环节，它不仅关系到集成电路的功能是否正确，而且也会极大程度地影响集成电路的性能、成本与功耗。

本文依据基本CMOS集成运算放大电路的设计指标及电路特点，绘制了基本电路图，通过Spectre进行仿真分析，得出性能指标与格元器件参数之间的关系，据此设计出各元件的版图几何尺寸以及工艺参数，建立出从性能指标到版图设计的优化路径。运算放大器的版图设计，是模拟集成电路版图设计的典型，利用Spectre 对设计初稿加以模拟，然后对不符合设计目标的参数加以修改，重复这一过程，最终得到优化设计方案。最后根据参数尺寸等完成了放大器的版图设计以及版图的DRC、LVS验证。

关键词：集成电路，运算放大器，版图设计，仿真

ABSTRACT

Integrated circuit layout design is an essential design part to realize circuit mask manufacturing, it is not only related to the integrated circuit to function correctly, but also can greatly affect the performance of the integrated circuit, the cost and the power consumption.Based on the basic CMOS integrated operational amplifier circuit characteristic and design target, we have rendered the basic circuit diagram, and simulation by Spectre, the simulated results are derived parameters and their relationship between determining factors, thereby defining a line with the design target domain size and processing parameters, finally we builded an optimization from the performance index to layout design .Operational amplifier IC layout design, is the design model of analog integrated circuit layout . Here we used Spectre to design draft which should be simulated, then modified which do not comply with the design goals of the parameters , repeat the process, and finally get the optimization design scheme. Finally, according to the parameters such as size finished the amplifier layout design and the DRC, LVS verification.

KET WORDS: Integrated circuit, Operational amplifier, layout design, Simulation

目录

前言 (5)

第1章绪论 (6)

1.1 课题背景 (6)

1.1.1 研究背景 (6)

1.1.2研究内容 (7)

1.2 电路设计流程 (8)

1.3 主要工作以及任务分配 (10)

1.3.1主要工作 (10)

1.3.2 任务分配 (10)

第2章版图基础知识 (11)

2.1 版图的设计简介 (11)

2.1.1 版图的概念 (11)

2.1.2 版图中层的意义 (11)

2.2 CMOS工艺技术 (14)

2.2.1概述 (14)

2.2.2 CMOS工艺的一些主要步骤 (15)

2.2.3 CMOS制造工艺的基本流程 (16)

2.3 设计规则 (18)

2.4 MOS集成运放的版图设计 (22)

第3章CMOS运算放大器简介 (23)

3.1 概述 (23)

3.2两级CMOS运算放大器的优点 (25)

3.3 两级运算放大器原理简单分析 (25)

第4章CMOS运算放大器的仿真 (28)

4.1 概述 (28)

4.2 MOS运算放大器技术指标总表 (29)

4.3仿真数据 (30)

4.3.1 DC分析 (30)

4.3.2测量输入共模范围 (31)

4.3.3 测量输出电压范围 (32)

4.3.4 测量增益与相位裕度 (34)

4.3.5 电源电压抑制比测试 (35)

4.3.6 运放转换速率和建立时间分析 (37)

4.3.7 CMRR的频率响应测量 (40)

第5章算放大器版图设计 (41)

5.1 Cadence使用说明 (41)

5.2 版图设计 (44)

5.3 CMOS运放版图 (44)

第6章总结 (46)

参考文献 (47)

致谢词 (48)

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