数字集成电路分析与设计考试(广工)
GDOU广东海洋大学数字电路试题集1
海洋大学 —— 学年第 学期《 数字电子技术基础 》课程试题课程号： 16632205√ 考试 √ A 卷 √ 闭卷□ 考查□ B 卷□ 开卷一、填空题（每空1分，共10分）1．如果采用二进制代码为200份文件顺序编码，最少需用 位。
2．和二进制数（1010.01）2等值的十进制数为 。
3．二进制数（+0000110）2的原码为 、反码为补码为 。
4．逻辑函数式A ⊕0的值为 。
5．逻辑函数式Y = A ′ BC ′ + AC ′ + B ′C 的最小项之和的形式为 。
6. 组合逻辑电路的特点是 。
7．若存储器的容量为512K×8位，则地址代码应取 位。
8．D/A 转换器的主要技术指标是转换精度和 。
二、单项选择题（每小题2分，共10分） 1．逻辑代数中的三种基本运算指（ c ）。
(a)加、减运算 (b)乘、除运算 (c)与、或、非运算 (d)优先级运算 2．若两个逻辑式相等，则它们的对偶式（ d ）。
班级：姓名：学号：试题共页加白纸张密封线GDOU-B-11-302(a)不一定相等 (b)可能为0 (c) 可能为1 (d) 一定相等 3.正逻辑的高电平表示为（ b ）。
(a) 0 (b)1 (c)原变量 (d)反变量 4．三态门电路的输出可以为高电平、低电平及（ c ）。
(a)0 (b)1 (c)高阻态 (d)导通状态 5．随着计数脉冲的不断输入而作递增计数的计数器称为（ a ）。
(a)加法计数器 (b)减法计数器 (c)可逆计数器 (d)加/减计数器 三、分析题（每小题10分，共40分）1．已知逻辑函数Y 1 和Y 2的真值表如表1所示，试写出Y 1 和Y 2的逻辑函数式。
表12．分析图1所示时序电路的逻辑功能，写出电路的驱动方程、状态方程和输出方程，画出电路的状态转换图和时序图。
图13．写出如图2A B C Y 0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Y 121 11 00 10 01 11 00 11 0F=ABC+ABC+ABA B C图24．由两个三态门组成的逻辑电路如图3所示，试分析其逻辑功能。
集成电路设计岗位招聘笔试题与参考答案(某大型集团公司)
招聘集成电路设计岗位笔试题与参考答案(某大型集团公司)(答案在后面)一、单项选择题（本大题有10小题，每小题2分，共20分）1、在集成电路设计中，以下哪种类型的设计通常负责处理数字逻辑功能？A、模拟集成电路B、数字集成电路C、混合信号集成电路D、射频集成电路2、以下哪种技术用于在集成电路设计中实现晶体管间的连接？A、光刻技术B、蚀刻技术C、键合技术D、离子注入技术3、在CMOS工艺中，P型MOSFET的阈值电压通常会随着温度的升高而：A. 增加B. 减少C. 不变D. 先增加后减少4、下列哪一项不是减少互连延迟的有效方法？A. 使用更细的金属线B. 使用更高介电常数的绝缘材料C. 减少金属层之间的距离D. 使用铜代替铝作为互连线材料5、集成电路设计中，以下哪种工艺主要用于制造CMOS（互补金属氧化物半导体）逻辑电路？A. 双极型工艺B. 金属氧化物半导体工艺C. 双极型/金属氧化物半导体混合工艺D. 双极型/CMOS混合工艺6、在集成电路设计中，以下哪个参数通常用来描述晶体管的开关速度？A. 饱和电压B. 输入阻抗C. 开关时间D. 集成度7、在集成电路设计中，用于描述电路逻辑功能的硬件描述语言不包括以下哪一种？A. VerilogB. VHDLC. C++D. SystemVerilog8、下列选项中，哪一个不是ASIC（专用集成电路）设计流程中的一个阶段？A. 逻辑综合B. 布局布线C. 系统集成D. 物理验证9、以下哪种工艺技术通常用于制造高性能的集成电路？A. 混合信号工艺B. CMOS工艺C. GaN（氮化镓）工艺D. BiCMOS工艺二、多项选择题（本大题有10小题，每小题4分，共40分）1、在CMOS工艺中，关于阱（well）的概念，下列说法正确的有：A. NMOS晶体管通常位于P型阱中B. PMOS晶体管通常位于N型阱中C. N阱用于隔离不同区域的晶体管，防止电流泄露D. P阱可以与N阱共存于同一层硅片上而不会相互影响2、关于集成电路版图设计中的DRC（Design Rule Check）规则，下列哪些陈述是正确的？A. DRC规则是为了确保电路性能优化B. DRC规则定义了最小特征尺寸、最小间距等制造限制C. 违反DRC规则可能会导致制造缺陷，如短路或开路D. DRC规则在所有半导体制造工艺中都是相同的3、关于集成电路设计，以下哪些是典型的电路设计类型？（）A、模拟电路设计B、数字电路设计C、混合信号电路设计D、射频电路设计E、光电子电路设计4、在集成电路设计中，以下哪些因素会影响电路的功耗？（）A、晶体管的工作状态B、电源电压C、电路的复杂度D、芯片的温度E、外部负载5、在集成电路设计过程中，下列哪些技术用于提高电路的性能？A. 使用更先进的制程技术B. 优化电路布局减少信号延迟C. 增加电源电压以提升速度D. 减少电路层数降低制造成本E. 应用低功耗设计方法6、下列哪些是实现CMOS逻辑门时需要考虑的关键因素？A. 输入电平的阈值B. 输出驱动能力C. 功率消耗D. 静态电流消耗E. 电路的工作频率7、以下哪些技术或方法属于集成电路设计中的模拟设计领域？（）A. 信号处理算法B. 逻辑门电路设计C. 模拟电路仿真D. 功耗分析E. 版图设计8、在集成电路设计中，以下哪些步骤是进行版图设计的必要阶段？（）A. 电路原理图设计B. 布局规划C. 逻辑分割D. 布局布线E. 版图检查9、在CMOS工艺中，影响MOSFET阈值电压的因素有哪些？A. 氧化层厚度B. 衬底掺杂浓度C. 栅极材料类型D. 源漏区掺杂浓度E. 温度F. 器件尺寸三、判断题（本大题有10小题，每小题2分，共20分）1、集成电路设计岗位的工程师需要具备扎实的数学基础和电子工程知识。
华南理工大学数字电子技术试卷(含答案)
诚信应考,考试作弊将带来严重后果！华南理工大学期末考试《数字电子技术》试卷A注意事项：1. 考前请将密封线内填写清楚；2. 所有答案请直接答在试卷上(或答题纸上)；3．考试形式: 闭卷；4. 本试卷共四大题，满分100分，考试时间120分钟。
题号一二三四总分得分评卷人一. 单项选择题：（在每小题的备选答案中选出一个正确的答案，并将正确答案的字母填入下表中对应的格子里。
每小题2分，共20分。
）题号12345678910答案1．十进制数128的8421BCD码是（）。
A.10000000B. 000100101000C.100000000D.1001010002.已知函数F的卡诺图如图1-1, 试求其最简及或表达式3. 已知函数的反演式为，其原函数为（）。
A． B．C． D．4．对于TTL数字集成电路来说，下列说法那个是错误的：（A）电源电压极性不得接反，其额定值为5V；（B）不使用的输入端接1；（C）输入端可串接电阻，但电阻值不应太大；（D） OC门输出端可以并接。
5．欲将正弦信号转换成及之频率相同的脉冲信号，应用A.T，触发器B.施密特触发器C.A/D转换器D.移位寄存器6．下列A/D转换器中转换速度最快的是（）。
A.并联比较型B.双积分型C.计数型D.逐次渐近型7. 一个含有32768个存储单元的ROM，有8个数据输出端，其地址输入端有（）个。
A. 10B. 11C. 12D. 88. 如图1-2，在TTL门组成的电路中，及非门的输入电流为I iL≤–1mA‚I iH≤20μA。
G1输出低电平时输出电流的最大值为I OL(max)=10mA，输出高电平时最大输出电流为I OH(max)=–0.4mA 。
门G1的扇出系数是（）。
A. 1B. 4C. 5D.109.十数制数2006.375转换为二进制数是：A. 11111010110.011B.1101011111.11C. 11111010110.11D. 1101011111.01110. TTL或非门多余输入端的处理是:A. 悬空B. 接高电平C. 接低电平D.接”1”二.填空题(每小题2分，共20分)1.CMOS传输门的静态功耗非常小，当输入信号的频率增加时，其功耗将______________。
最新深圳大学数字电路试题B参考答案及评分标准
数字电路试题B参考答案及评分标准、用公式法将下列函数化简为最简与或式(每小题5分，共10分) F^(A AB ABC)(A B C)二A(A B C)=AB ACF 2 二A B AC B C=AB (A B)C二AB ABC二AB C参考评分说明：每小题完全正确给6分，结果错误但部分正确的，每对一步给一分。
(每小题6分，共12分)、用卡诺图法将下列函数化简为最简或与式F1(A,B,C^i.l M (0,1,2,5)八m(3,4,6,7)0 0 1 01 0 1 1F1(A, B,C)二AC BCF'A, B,C)二AC BC =(A C)(B C)F2(A, B,C,D)八m(0,1,2,3,6,7,11,15)参考评分说明：每小题结果完全正确给6分，每小题卡诺图正确给3分，结果错误但部分正确的，每对一步给一分。
三、利用卡诺图法将下列函数化简为最简与或式。
(每小题6分，共12分)F, (A, B, C, D) = ABC BCD AD AB CDF；(A,B,C, D)二ABC BCD AD AB CD= ABC BCD AD AB ACD画F,(A, B,C,D)的卡诺图如下:F,(代B,C,D =AC ABD A BD F,(A, B,C,D =AC ABD ABDF2(A,B,C,D)八m(3,5,6,7,10) 、d 0,1,2,4,8F2(A, B,C,D) =A BD参考评分说明：每小题结果正确给6分，每小题卡诺图正确给3分，结果错误但部分正确的，每对一步给一分。
四、用与非门设计一个四变量的多数表决电路，当输入变量有3个或3个以上为1时输出为1,输入为其它状态时输出为0。
( 15分)解：设A,B,C,D表示输入逻辑变量，丫表示投票结果输出，其真值表如下：根据真值表画出卡诺图，如下:由卡诺图，得Y = ABC + ABD + ACD + BCD二ABC ABD ACD BCD=ABC A BD ACD BCD根据逻辑表达式，画逻辑电路图如下参考评分说明：结果正确给15分，真值表正确给5分，卡诺图正确给2分，逻辑表达式正确给3分，逻辑电路图正确给5分，结果错误但部分正确的，每对一步酌情给分，但不超出各部分给定的分值。
集成电路应用工程师招聘笔试题及解答2024年
2024年招聘集成电路应用工程师笔试题及解答(答案在后面)一、单项选择题（本大题有10小题，每小题2分，共20分）1.（数字）集成电路中，逻辑门电路是构成各种逻辑功能的基本单元。
2.（数字）数字电路设计中，集成电路芯片的功耗主要由电压决定，与电流无关。
3.（数字）模拟信号与数字信号在集成电路中的转换，一般需要通过模数转换器（ADC）或数模转换器（DAC）。
4.（数字）集成电路制造工艺中，光刻技术主要用于制作电路图案。
3.集成电路中，哪种类型的晶体管具有高速、低噪声和良好的频率响应特性？A. 二极管B. 晶体管（BJT）C. 场效应晶体管（FET）D. 变压器4.在集成电路设计中，哪种封装形式最适合用于大批量生产和应用？A. 插件式B. 芯片级封装C. 陶瓷封装D. 环氧树脂封装5.在集成电路设计中，以下哪个选项是常用的数字信号处理算法？A.傅里叶变换B.卷积运算C.快速傅里叶变换D.以上都是6.集成电路的哪种封装形式主要用于高性能、高频率的芯片？A.针脚式B.表面贴装式（SMD）C.插件式D.以上都是7.在集成电路设计中，以下哪个因素对电路的性能影响最大？A. 电源电压B. 地线布局C. 热设计D. 噪声干扰8.以下哪种封装形式适用于高集成度的集成电路芯片？A. 芯片上引线封装B. 插件式封装C. 塑料封装D. 模块化封装9.在集成电路设计中，以下哪个步骤不属于常见的工艺步骤？A. 物理验证B. 逻辑综合C. 器件建模D. 芯片封装 10. 在CMOS工艺中，以下哪种器件主要用于实现电流放大？A. 晶体管B. 反相器C. 二极管D. 传输门二、多项选择题（本大题有10小题，每小题4分，共40分）1.关于集成电路的基本构成，以下哪些说法是正确的？A. 集成电路主要由晶体管构成B. 集成电路的集成度越高，电路性能越好C. 集成电路中不包括电容器和电阻器D. 集成电路由多个电子元器件集成在一起形成微型化电路2.在集成电路设计中，以下哪些因素是必须考虑的？A. 工艺制造能力B. 市场需求和趋势C. 硬件资源的成本D. 操作系统的兼容性3.在集成电路设计中，以下哪个选项是用来描述电路性能的主要参数？A. 电阻B. 电容C. 速度D. 功率E. 电流4.集成电路的制造工艺通常包括哪些步骤？A. 设计B. 制版C. 制造D. 装配E. 测试5.关于集成电路的应用，以下哪些说法是正确的？A. 集成电路主要应用在计算机硬件领域。
集成电路设计原理考核试卷
4.描述模拟集成电路与数字集成电路在设计原则和实现技术上的主要区别，并给出一个实际应用中模拟集成电路的例子。
标准答案
一、单项选择题
1. B
2. B
3. D
4. D
5. B
6. D
7. C
8. C
9. B
10. D
17.在集成电路设计中，以下哪些方法可以提高电路的抗干扰能力？( )
A.采用差分信号传输
B.使用屏蔽技术
C.增加电源滤波器
D.提高工作频率
18.以下哪些类型的触发器在数字电路中常见？( )
A. D触发器
B. JK触发器
C. T触发器
D. SR触发器
19.以下哪些技术可以用于提高集成电路的数据处理速度？( )
3.以下哪些是数字集成电路的基本组成部分？( )
A.逻辑门
B.触发器
C.寄生电容
D.晶体管
4.以下哪些技术可以用于提高集成电路的频率？( )
A.减小晶体管尺寸
B.采用高介电常数材料
C.增加电源电压
D.优化互连线设计
5.在CMOS工艺中，以下哪些结构可以用来实现反相器？( )
A. PMOS晶体管
B. NMOS晶体管
11. C
12A
16. B
17. A
18. A
19. C
20. B
二、多选题
1. ABD
2. AB
3. AD
4. AB
5. AB
6. AB
7. ABCD
8. AB
9. ABCD
10. AC
11. ABC
数字集成电路分析与设计 第三章答案
CHAPTER 3P3.1. The general approach for the first two parameters is to figure out which variables shouldremain constant, so that when you have two currents, you can divide them, and every variable but the ones you want to calculate remain. In this case, since the long-channel transistor is in saturation for all values of V GS and V DS , only one equation needs to be considered:()()2112DS N OX GS T DS W I C V V V Lμλ=-+ For the last two parameters, now that you have enough values, you can just choose oneset of numbers to compute their final values.a. The threshold voltage, V T0, can be found by choosing two sets of numbers with the same V DS ’s but with different V GS ’s. In this case, the first two values in the table can be used.()()()()()()211122222201022001121121.2 1.210000.82800.8DS N OX GS T DS DS N OX GS T DS T DS T DS T T W I C V V V L W I C V V V LV I V I V V μλμλ=-+=-+-⎛⎫-===⎪--⎝⎭ 00.35V T V ∴=b. The channel modulation parameter, λ, can be found by choosing two sets of numberswith the same V GS ’s but with different V DS ’s. In this case, the second and third values in the table can be used.()()221 1.225010.8247DS DS I I λλ+==+ -10.04V λ∴=c. The electron mobility, µn , can now be calculated by looking at any of the first three sets of numbers, but first, let’s calculate C OX .631062-31m 10μm22?.210μm1m 10 0.0351 1.610/2.210OX OX t C F cm--=⨯⨯===⨯Now calculate the mobility by using the first set of numbers.()()()()()()()()()()()()22111021262101111 1.21 1.222210002cm 348V-s 1.610(4.75)1.20.3510.04 1.21DS N OX GS T DS N OX T DS N OX GS T DS W W I C V V V C V L LA I W C V V V L μλμλμμλ-=-+=-+===⨯-+-+d. The body effect coefficient gamma, γ, can be calculated by using the last set of numbers since it is the only one that has a V SB greater than 0V.()()()()244124414411221 1.20.468VDS N OX GS T DS DS GS T N OX DS GS T T GS W I C V V V LI V V W C V LV V V V μλμλ=-+-=+-==-==12000.6VT T T T V V V V γγγ=+-====P3.2. The key to this question is to identify the transistor’s region of operation so that gatecapacitance may be assigned appropriately, and the primary capacitor that will dischargedat a rate of V It C ∂∂= by the current source may be identified. Then, because the nodes arechanging, the next region of operation must be identified. This process continues until the transistor reaches steady state behavior. Region 1:Since 0V GS V = the transistor is in the cutoff region. The gate capacitance is allocated to GB C . Since no current will flow through the transistor, all current will come from the source capacitor and the drain node remains unchanged.68-151010V V 6.67100.6671510s nsSB V I I t C C -∆⨯====⨯=∆⨯ The source capacitor will discharge until 1.1V GS T V V == when the transistor enters thesaturation region. This would require that the source node would be at 3.3 1.1 2.2V S G GS V V V =-=-=.()15961510 3.3 2.2 1.6510s 1.65ns 1010C t V I ---⨯∆=∆=-=⨯=⨯ Region 2:The transistor turns on and is in saturation. The current is provided from the capacitor atthe drain node, while the source node remains fairly constant. The capacitance at the drain node is the same as the source node so the rate of change is given by:68-151010V V 6.67100.6671510s nsSB V I I t C C -∆⨯====⨯=∆⨯ Since the transistor is now in the saturation region, GS V can be computed based on thecurrent flowing through the device.()22 1.1 1.37V 3.3 1.37 1.93VGS T GST S G GS kW I V V LV V V V V =-==+==-=-=This is where the source node settles. This means that most of the current is discharged through the transistor until the drain voltage reaches a value that puts the transistor at the edge of saturation.3.3 1.1 2.2VDS GS TD G T V V V V V V =-=-=-=If we assume that all the current comes from the transistor, and the source node remains fixed, the drain node will then discharge at a rate equal to that of the source node in the first region. Region 3:The transistor is now in the linear region the gate capacitance is distributed equally to both GS C and GD C . and both capacitors will discharge at approximately the same rate.-151510V0.28621510510nsV I A t C μ-∆===∆⨯⨯+⨯The graph is shown below.00.511.522.533.5024681012Time (ns)V o l t a g e (V )P3.3. The gate and drain are connected together so that DS GS V V = which will cause thetransistor to remain in saturation. This is a dc measurement so capacitances are not required. Connect the bulk to ground and run SPICE. P3.4. Run SPICE. P3.5. Run SPICE. P3.6. Run SPICE. P3.7. Run SPICE.P3.8. First, let’s look at the various parameters and identify how they affect V T .∙ L – Shorter lengths result in a lower threshold voltage due to DIBL. ∙ W – Narrow width can increase the threshold voltage.∙ V SB – Larger source-bulk voltages (in magnitude) result in a higher threshold voltage. ∙ V DS –Larger drain-source voltages (in magnitude) result in a lower threshold voltage due to DIBL. The transistor with the lowest threshold voltage has the shortest channel, larger width, smallest source-bulk voltage and largest drain-source voltage. This would be the first transistor listed.The transistor with the highest threshold voltage has the longest channel, smallest width,largest source-bulk voltage and smallest drain-source voltage. This would be the last transistor listed. P3.9. Run SPICE.P3.10. Run SPICE. The mobility degradation at high temperatures reduces I on and the increasemobile carriers at high temperatures increase I off . P3.11. The issues that prompted the switch from Al to Cu are resistance and electromigration.Copper wires have lower resistances and are less susceptible to electromigration problems. Copper on the other hand, reacts with the oxygen in SiO 2 and requires cladding around the wires to prevent this reaction.For low-k dielectrics, the target value future technologies is 2.High-k dielectrics are being developed as the gate-insulator material of MOSFET’s. This is because the current insulator material, SiO 2, can not be scaled any longer due to tunneling effects.P3.12. Self-aligned poly gates are fabricated by depositing oxide and poly before the source anddrain regions are implanted. Self-aligned silicides (salicides) are deposited on top of the source and drain regions using the spacers on the sides of the poly gate. P3.13. To compute the length, simply use the wire resistance equation and solve for L .LR TWRTWL ρρ==First convert the units of ρ to terms of μm. Aluminum:2.7μΩρ=cm 6Ω10μΩ⨯610μm100cm ⨯()()()0.027Ωμm1000.812963μm 2.96mm0.027RTWL ρ=====Copper:1.7μΩρ=cm 6Ω10μΩ⨯610μm100cm ⨯()()()0.017Ωμm1000.814706μm 4.71mm0.017RTWL ρ=====P3.14. Generally, the capacitance equation in terms of permittivity constants and spacing is:k C WL tε=a. 4k = ()()()()230048.8510 3.541100SiO k k C WL TL t S S Sεε-====b. 2k = ()()()()30028.8510 1.771100k k C WL TL t S SSεε-====The plots are shown below.Capacitance vs. Spacing01234567800.511.522.533.544.555.5Spacing (um)C a p a c i t a n c e (f F)。
广州中医药大学《数字电路》考试试卷A.
《数字电路》试卷第1页共4页广州中医药大学20-20学年第学期期末考试《数字电路》试卷（A 卷）（适用于信息技术学院20级计算机科学与技术专业）考试时间：120分钟满分：100分学院级专业姓名：学号：：一、单项选择题（本题共8小题，每小题3分，共24分）答题说明：下列四个备选答案中只有一个是最佳或最恰当的答案，请用钢笔或圆珠笔把正确答案的字母填写在括号里。
1、[1011]2对应的余3码为（）。
A ）1110B ）1101C ）1010D ）10112、若输入变量A，B 取之相同时，输出F=1；否则输出F＝0，则其输出与输入的关系是（）。
A ）或非运算B ）异或运算C ）同或运算D ）与运算3、下列各进制数中，值最小的是（）。
A ）[00110101]2B ）[3A]16C ）[56]10D ）[01010111]8421BCD 4、电路如图所示，不能实现n 1n Q Q =+的电路是（）。
5、能够实现线与功能的是（）。
A ）TTL 与非门B ）三态逻辑门C ）集电极开路门D ）CMOS 逻辑门6、下列所示TTL 门电路输出与输入之间逻辑关系正确的是（）7、[755]10对应的8421BCD 码为（）。
A ）(111010*********BCDB ）(0111010101018421BCD题型一二三四总分得分评卷人1CPCPQ Q QAB1K1J1K1J 1.1D 1DCPCPQQ C D《数字电路》试卷第2页共4页C ）(011101011018421BCD D ）(0011110101018421BCD 二、填空题（本题共10题，每小题3分，共30分）1、只考虑本位两个二进制数相加，而不考虑来自低位进位数相加的运算电路称为。
2、在逻辑函数中，如果一个与项包含该逻辑函数的全部变量，且每个变量或以或以只出现一次，则该与项称为最小项。
3、组合逻辑电路功能上的特点是：在任一时刻的输出状态只取决于的输入状态，与电路的原来状态没有关系。
数字集成电路设计与系统分析答案
懂得1、Please illustrate the meaning of its voltage transfer characteristic to a logic gate, and describe the static behaviors showed in the voltage transfer characteristic curves.The electrical function of a gate is best expressed by its voltage transfer characteristic (VTC),which plots the output voltage as a function of the input voltage Vout=f(Vin).The high and low nominal voltage Voh and Vol;The gate or switching threshold voltage Vm,that is define as Vm=f(Vm)(The gate threshold voltage presents the midpoint of the switching characteristics,which is obtained when the output of a gate is short circuited to the input);The high and low input voltage Vih and Vil are defined by the point where the gain (=dVout/dVin)of the VTC equals -12、Please draw the voltage transfer characteristic curve of the inverter and label the static operation points in the VTC.3、Please describe the definition of noise margin and its physical significance(物理意义), then draw the figure of definition of noise margins.The noise margins represent the levels of noise that can be sustained(所允许的) when gates are cascaded. A measure of the sensitivity of a gate to noise is given by the noise margins NML(noise margin low) and NMH(noise margin high), which quantize the size of the legal “0” and “1”, respectively, and set a fixed maximum threshold on the noise value4、Please describe the meaning of the regenerative property and the conditions of a gate with regenerative property.A gate with regenerative property ensures that a disturbed signal converges back to a nominal voltage level after passing through a number of logical stages. The VTC should have a transient region (or undefined region) with a gain greater than 1 in absolute value, bordered by the two legal zones, where the gain should be less than 1 in absolute value5、What are the definitions of the fan-out and fan-in properties?The number that can be driven is termed the fan-out of circuit, that denotes the number of load gates N that are connected to the output of the driving gate. The fan-in of a gate is defined as the number of independent input nodes to the gate.6、How to describe the performance of a digital IC? Please illustrate the parameters used to characterize the transient performance of a logic family, and draw the associated figure of the definition of these parP ropagation delay time and rise/fall time can be used to characterize the transient performance of a logic family .Propagation delay time of a gate expresses the delay experienced by a signal when passing through a gate,which represent how quickly the gate responds to the changes at its inputs.Rise/fall time express how fast a signal transits between the different levels. Propagation delay time is defined as the period between the 50%transition points of the input and output signals.Rise/fall time is defined as the period between the 10% and 90% points of the total voltage transition at the output waveforms.1、Illustrate the basic structure and simple operation principle of MOS transistor.Four terminals:source, drain, gate, body; Vertical Structure: gate electrode, insulator, semiconductor substrate; Horizontal Structure: source region, channel region, drain region2、Illustrate the basic function of each terminal of MOS device, and describe the general terminal connections of NMOS and PMOS transistor, respectively.The source and the drain are the electrodes conducting the current. The gate electrode is thecontrolling terminal. The function of the body is secondaryIn NMOS devices, the source is defined as the n+ region which has a lower potential(电势) than the other n+ region, the drain. The source is the terminal with the higher potential in PMOS devices, The body is generally connected to a DC supply that is identical for all devices of the same type (GND for NMOS, VDD for PMOS).3、What does the transition (or input) characteristic of MOS transistor mean? And what conclusions we can find from the characteristic curve?It describes the relationship between the gate-source voltage and the drain-source current with the certain drain-source voltage .When the gate-source voltage is less than the threshold voltage, the conducting current is zero, that is, the NMOS transistor is in cutoff operation. When is larger than, the NMOS transistor is on.4、What does the current-voltage (or output) characteristic of MOS transistor mean? And what conclusions we can find from the I-V characteristic curve?.It describes the relationship between the drain-source voltage and the drain-source current with a certain gate-source voltageVgs > Vt , 0<VDS <VGS -VT : Linear modeThe inversion layer forms a continuous current path between the source and the drain.A drain current proportional to Vds will flow from the drain to the source through the conducting channel. The channel region acts as a voltage-controlled linear resister.5、Describe the operation modes of NMOS and PMOS transistors respectively, and define the corresponding ideal current equations.1、Explain the channel-length modulation, sub-threshold conduction, short-channel effect and narrow-channel effect. And illustrate their corresponding chief impacts on the device.This simple current equation prescribes a linear drain-bias dependence for the current in MOS transistors, determined by the empirical model parameter λ, called the channel-length modulation coefficientOne typical condition, which is due to the two-dimensional nature of channel current flow, is the sub-threshold conduction in small-geometry MOS transistors.As a working definition, a MOS transistor is called a short-channel device if its channel length is on the same order of magnitude as the depletion region thicknesses of the source and drain junctions.The short-channel effects that arise in this case are attributed to two physical phenomena: the limitations imposed on electron drift characteristics in the channel; the modification of the threshold voltage due to the shortening channel lengthMOS transistor that have channel widths on the same order of magnitude as the maxium depletion region thickness are defined as narrow channel devices.For MOSFET with small channel widths,the actual threshold voltage increases as a result of this extra depletion charge of the fringe depletion region.This fact is called narrow channel effect.2、Describe the three main components of the load capacitanceCL, when a logic gate is driving other fan-out gates. And sketch the capacitance model of NMOS transistor.Gate capacitances (of other inputs connected to out)Diffusion(or junction) capacitances (of drain/source regions)Routing capacitances (output to other inputs)1,Describe the basic structure and operation of a static CMOS inverter. Then draw theassociated transistor schematicThis structure consists of an enhancement-type NMOS transistor and an enhancement-type PMOS transistor, operating in complementary mode. So this configuration is called Complementary MOS (CMOS). The gate terminals of the PMOS and NMOS transistors are connected to form the inverter input. The drain terminals of the PMOS and NMOS transistors are connected to form the inverter output. The source and the substrate of the NMOS transistor are connected to the ground, while the source and body of PMOS transistor are connected to VDD The circuit topology is complementary push-pull in the sense that: For high input the NMOS transistor drives (pulls down) the output node while the PMOS transistor acts as the load, and for low input the PMOS transistor drives (pulls up) the output node while the NMOS transistor acts as the load.When the input is at VDD: The NMOS is on (conducting) while the PMOS is off (cut-off). A direct path exists between Vout and the ground node, resulting in a steady-state value of 0V at the output. When the input is at ground:The NMOS is off while the PMOS is on. A direct path exists between VDD and Vout, yielding a high output voltage (equal to VDD).Static CMOS logic:structure:The static CMOS style is really an extension of the static CMOS inverter to multiple inputs. A logic function in static CMOS must be implemented in both NMOS and PMOS transistors. It is the combination of the pull-up network(PUN) and the pull-down network(PDN). Each input always connects to PUN and PDN simultaneously. The function of the PUN is to provide a connection between the output and VDD anytime the output of the logic gate is meant to be 1 (based on the inputs). The function of the PDN is to connect the output to VSS when the output of the logic gate is meant to be 0.Opreation: The pull-down net should be “on” when the pull-up net is “off” and vice versa. For any given input combination, the output is connected either to VDD or to ground via a low-resistance path. A DC current path between the VDD and ground is not established for any of the input combinations. With the complementary nature of NMOS and PMOS, the pull-up or the pull-down is “on” alternately to implement the logic operation.Discuss the main problems for high fan-in static CMOS gates and the associated techniques for fast complex gates.tpHL = 0.69 Reqn(C1+2C2+3C3+4CL); Propagation delay deteriorates(恶化) rapidly as a function of fan-in quadratically in the worst case, Gates with a fan-in greater than 4 become excessively slow and must be avoided.tPLH increases linearly due to the linearly increasing value of the diffusion capacitance;tPHL increase quadratically due to the simultaneous increase the resistance and internal capacitance in serial part.Transistor sizing: as long as fan-out capacitance dominatesProgressive transistor sizing: This approach reduces the dominant resistance, while keeping the increase in capacitance within boundsTransfer gate:Configuration:The source and drain nodes serve as inputs and outputs, while the gate node serves as the control input, the body node is connected to the power/ground Operation: For NMOS transfer gate,it turns on while the gate control terminal goes high, and the input signal will be delivered to the output node; it turns off while the gate control terminal goes low, and the output node will be impedance.CMOS transmission gate:Configuration: The CMOS transmission gate consists of one NMOS and one PMOS transistor, with the source and drain connected in parallel; The gate voltages appliedto these two transistors are also set to be complementary signals. The substrate terminal of the NMOS transistor is connected to ground and the substrate terminal of the PMOS transistor is connected to Vdd.Operation: If the control signal C is logic-high (equal to Vdd), then both transistors are turned on and provide a low-resistance current path between the input and output nodes. If the control signal C is logic-low, then both transistors will be off, and the path between the input and output nodes will be in the high-impedance state. The weakness of one device is overcome by the strength of the other device, whether the output is transmitting a high or low value. This is a clear advantage of the CMOS transfer gate over the single transistor counterpart.DCVLS:Operation: Assume now that, for a given set of inputs, PDN1 conducts while PDN2 does not, and that Out and out are initially high and low, respectively. Turning on PDN1: Causes Out to be pulled down (below VDD−|VTP |); Out is in a high impedance state, as M2 and PDN2 are both turned off. At the point M2 turns on and starts charging out非to VDD — eventually turning off M1; This in turn enables Out to discharge all the way to GND.XOR/XNOR: When the signals A and B have the same values, there is one conducting path either AB or A非B非; Then the output F is pulled down;At the same time, the other pull-down paths connected to the F非are both turned off. When F is pulled down below VDD−|VTP |, M2 t urns on and starts charging F非to VDD —eventually turning off M1 and pulling down F to Gnd. When the signals A and B have the different values, there is one conducting path either AB非or A非B; Then the output F非is pulled down; At the same time, the other pull-down paths connected to the F are both turned off. When F非is pulled down below VDD−|VTP |, M1 turns on and starts charging F to VDD —eventually turning off M2 and pulling down F非to Gnd.Precharge-Evaluate dynamic CMOS:Operation: Precharge (when the clock signal Φ= 0)：The PMOS precharge transistor MP is conducting while the complementary NMOS transistor MN is off. The output load capacitance is precharged to VDD by MP, then VOH=VDD；The input voltages have no influence yet upon the output level since the complementary NMOS transistor MN is off. Evaluate (when the clock signal Φ=1)：The precharge transistor MP turns off while the NMOS evaluate transistor MN turns on. The output node voltage may now remain at the logic-high level or drop to a logic low, depending on the input voltage levels: If the input signals create a conducting path between the output node and the ground, PDN is on, and the output capacitance will discharge toward VOL=0;Otherwise, when PDN is off, the output voltage remains at VOH= VDD.Domino dynamic CMOS logic:When Φ=0, during precharge: The output of the n-type dynamic gate is charged up to VDD, and the output of the inverter is set to 0. When Φ=1, during evaluation: The dynamic gate conditionally discharges, and there are two possibilities: The output node of the dynamic CMOS stage is either discharged to a low level through the NMOS circuitry (1 to 0 transition), or it remains high. Consequently, the inverter output voltage can also make at most one transition during the evaluation phase, from 0 to 1.TSPC dynamic CMOS logic:Configuration:If one constrains a NORA stage to have only n-precharge gates, and not static gates, then a p-channel transistor can be eliminated from the clocked latch; The dynamic circuit technique to be presented in that it uses only one-phase clock signal, so no clock skew problem exists. The NORA design style can be simplified so that a single clock is sufficient. For the doubled n-C2MOS latch, when φ= 1, the latch is in the transparent evaluate mode and corresponds to 2 cascaded inverters (non-inverting); For the doubled n-C2MOS latch, when φ= 0, both inverters are disabled (hold mode) -- only the pull-up network is still active.Pipelined NORA dynamic CMOS system:Configuration: Consists of an np-CMOS logic sequence and a clocked CMOS output buffer; A pipelined system can be constructed by simply cascading alternating φ-section and φ -section, meaning that evaluation occurs during active φ and φ respectively;Operation:φ=0, during hold mode :N block performs the precharge operation and pulls node Out1 up to VDD through the p-type device Mp1, while p block performs the discharge operation and pulls the node Out2 down to zero through the n-type device Mn2; The clocked CMOS latch will not be in operation and the previous output voltage will be stored on the output load capacitor CL. φ=1, during evaluate mode:All cascaded NMOS and PMOS blocks evaluate output levels one after the other, and then the signal Out2 will be inversed to the output node by the clocked CMOS latch in operation;Operation Mode: Evaluate―Hold: All logic stages perform the precharge-discharge operation when the clock is high, and all stages evaluate output levels when the clock is low. Therefore, wewill call this circuit a section, meaning that evaluation occurs during active .Clocked CMOS dynamic circuit:Basic Structure:A pair of PMOS and NMOS transistors controlled by the complementary clock signals are cascaded in the pullup and pulldown paths of the static CMOS gate, respectively, then a CMOS logic gate can be synchronized with a clock. Operation: φ=1, during evaluation mode：The transistors Mp1 and Mp2 are both turned on, then this gate can evaluate normally as a CMOS inverter to generate the logic output In非; φ=0 , during hold mode: Both transistors Mp1 and Mp2 are off, decoupling the output from the input. The CMOS circuit cannot conduct and evaluate, then the output Q retains its previous value stored on the output capacitor CL.Sequential logic:Virtually all useful systems require storage of state information, leading to another class of circuits called sequential logic circuits. In these circuits, the output not only depends upon the current values of the inputs, but also upon preceding output values. In other words, a sequential circuit remembers some of the past history of the system; A sequential circuit consists of a combinational circuit and a memory block in the feedback loop.Combination logic:In all logic circuits described so far, the output is directly related to the input. Typically, there are no feedback loops between the output and the input in these circuits (also classified as non-regenerative circuits), so the outputs are always a logical combination of the inputs. As a class, these circuits are known as combinational logic circuits. Combinational logic circuits, described earlier, have the property that the output of a logic block is only a function of the current input values, assuming that enough time has elapsed for the logic gates to settle. Static storage:preserve state as long as the power is on;are built using positive feedback or regeneration with an intentional connection between the output and the input;useful when updates are infrequent (clock gating)Dynamic storage:store state on parasitic capacitors;only hold state for short periods of time (milliseconds);require periodic refresh to annihilate charge leakage;usually simpler, so higher speed and lower power;useful in datapath circuits that require high performance levels and are periodically clockedLatch: level sensitive circuit that passes inputs to Q when the clock is high (or low);input sampledon the falling edge of the clock is held stable when clock is low (or high)Register or Flip-flops (edge-triggered): edge sensitive circuits that only sample the inputs on a clock transitionpositive edge-triggered: 0- 1negative edge-triggered: 1 -0built using latches (e.g., master-slave flip-flops)。
数字集成电路设计与分析
数字集成电路设计与分析数字集成电路（Digital Integrated Circuit，简称DIC）是一种用于处理和传输数字信号的电路。
它由许多晶体管、二极管和其他电子元件组成，通过将信号转换为离散的数字形式来进行处理。
在现代科技和信息技术的推动下，数字集成电路已经广泛应用于计算机、通信、嵌入式系统等领域。
一、数字集成电路的设计原理数字集成电路的设计原理源于二进制逻辑电路的概念。
二进制逻辑电路利用布尔代数的运算规律，通过逻辑门的组合和连接来实现各种逻辑功能。
数字集成电路是在此基础上进一步发展而来。
数字集成电路的设计需要考虑以下几个方面：1. 逻辑功能：根据需求确定数字电路所需实现的逻辑功能，如加法器、乘法器、状态机等。
2. 硬件资源：根据逻辑功能确定所需的晶体管、电阻、电容等硬件资源，并进行布局和布线设计。
3. 时序与时钟：考虑电路中各元件的时序关系，确定时钟频率和时序控制策略。
4. 电源和接口：设计电源供应和与外部系统的接口电路，确保数字集成电路的正常工作和与外界的通信。
二、数字集成电路的分析方法数字集成电路的分析是为了验证其设计是否符合预期功能、时序要求和性能指标。
以下是常用的数字集成电路分析方法：1. 逻辑仿真：通过电路仿真软件，将输入信号应用到数字集成电路模型中，观察输出信号是否满足预期逻辑功能。
逻辑仿真可以帮助发现设计中的逻辑错误和时序问题。
2. 时序分析：通过时序分析工具，分析数字集成电路中各个时序路径的延迟和时钟频率。
时序分析可以帮助确定电路是否满足时序要求，避免出现时序冲突或时序违规的问题。
3. 功耗分析：通过电路仿真和电路特性提取工具，分析数字集成电路的功耗消耗和功耗分布。
功耗分析可以帮助优化电路的功耗性能，减少能源消耗。
4. 供电噪声分析：通过电磁仿真和噪声分析工具，分析数字集成电路中的供电噪声问题。
供电噪声分析可以帮助解决电路中的电源干扰和信号完整性问题。
5. 仿真验证：通过数字集成电路芯片级仿真和电路板级仿真，验证数字集成电路的功能和性能。
CMOS数字集成电路：分析与设计（第三版）（中文版）
CMOS数字集成电路：分析与设计（第三版）（中文版）佚名
【期刊名称】《电气电子教学学报》
【年(卷),期】2006(28)3
【摘要】内容简介：本书集中讲述CMOS数字集成电路，反映现代技术的发展水平，提供电路设计的最新资料。
本书共有15章。
前半部分详细讨论MOS晶体管相关特性和工作原理、基本反相器电路设计、组合逻辑电路及时序逻辑电路的结构与工作原理。
后半部分介绍应用于先进VLSI芯片设计的动态逻辑电路，先进的半导体存储电路，低功耗MCMOS逻辑电路，双极性晶体管基本原理和BiCMOS数字电路设计，芯片的I／O设计，电路的可制造性设计和可测试性设计等问题。
【总页数】1页(P44-44)
【关键词】CMOS数字集成电路;分析与设计;中文版;第三版;数字电路设计;CMOS 逻辑电路;时序逻辑电路;工作原理;MOS晶体管;组合逻辑电路
【正文语种】中文
【中图分类】TN79;TM44
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2.基于CMOS工艺的中小规模数字集成电路设计浅析 [J], 孙玲;陈海进
3.高温CMOS数字集成电路的瞬态特性分析 [J], 柯导明;柯晓黎
4.《CMOS数字集成电路:分析与设计》课程教学探索 [J], 陈伟中;贺利军;黄义;周
前能;杨虹
5.CMOS数字集成电路的低功耗设计 [J], 陈光胜;张旭;沈力为
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广工08EDA试卷B
广东工业大学试卷用纸，共6 页，第 页1广东工业大学试卷用纸，共6 页，第 页2图23 广东工业大学试卷用纸，共6 页，第页广东工业大学试卷用纸，共6 页，第 页4广东工业大学试卷用纸，共6 页，第 页5广东工业大学试卷用纸，共6 页，第 页6 端的波形，设两个触发器的起始状态都为0。
nQ 1=+；CP 下降沿触发广东工业大学试卷用纸，共6 页，第 页7 《数字电子技术》试卷姓名：__ _______ 班级：__________ 考号：___________ 成绩：____________ 本试卷共 6 页，满分100 分；考试时间：90 分钟；考试方式：闭卷1. 有一数码10010011，作为自然二进制数时，它相当于十进制数（ ），作为8421BCD 码时，它相当于十进制数（ ）。
2.三态门电路的输出有高电平、低电平和（ ）3种状态。
3．TTL 与非门多余的输入端应接（ ）。
4．TTL 集成JK 触发器正常工作时，其d R 和d S 端应接（ ）电平。
5. 已知某函数⎪⎭⎫ ⎝⎛+⎪⎭⎫ ⎝⎛++=D C AB D C A B F ，该函数的反函数F =（ ）。
6. 如果对键盘上108个符号进行二进制编码，则至少要（ ）位二进制数码。
7. 典型的TTL 与非门电路使用的电路为电源电压为（ ）V ，其输出高电平为（ ）V ，输出低电平为（ ）V ， CMOS 电路的电源电压为（ ） V 。
8．74LS138是3线—8线译码器，译码为输出低电平有效，若输入为A 2A 1A 0=110时，输出 01234567Y Y Y Y Y Y Y Y 应为（ ）。
9．将一个包含有32768个基本存储单元的存储电路设计16位为一个字节的ROM 。
该ROM 有（ ）根地址线，有（ ）根数据读出线。
10. 两片中规模集成电路10进制计数器串联后，最大计数容量为（）位。
11. ）；Y 3 ＝（ ）。
12. 某计数器的输出波形如图1所示，该计数器是（ ）进制计数器。
数字集成电路考试重点
集成电路设计考点1.填空题1.NM L和NM H的概念，热电势，D触发器，D锁存器，施密特触发器。
低电平噪声容限：VIL-VOL高电平噪声容限：VOH-VIH这一容限值应该大于零热电势：两种不同的金属相互接触时，其接触端与非接触端的温度若不相等，则在两种金属之间产生电位差称为热电势。
2.MOS晶体管动态响应与什么有关？（本征电容P77）MOS晶体管的动态响应值取决于它充放电这个期间的本征寄生电容和由互连线及负载引起的额外电容所需要的时间。
本征电容的来源：基本的MOS结构、沟道电荷以及漏和源反向偏置PN结的耗尽区。
3.设计技术（其他考点与这种知识点类似）P147怎样减小一个门的传播延时：减小CL：负载电容主要由以下三个主要部分组成：门本身的内部扩散电容、互连线电容和扇出电容。
增加晶体管的宽长比提高VDD4.有比逻辑和无比逻辑。
有比逻辑：有比逻辑试图减少实现有一个给定逻辑功能所需要的晶体管数目，但它经常以降低稳定性和付出额外功耗为代价。
这样的门不是采用有源的下拉和上拉网络的组合，而是由一个实现逻辑功能的NMOS 下拉网络和一个简单的负载器件组成。
无比逻辑：逻辑电平与器件的相对尺寸无关的门叫做无比逻辑。
有比逻辑：逻辑电平是由组成逻辑的晶体管的相对尺寸决定的。
5.时序电路的特点：记忆功能的原理：（a）基本反馈；（b）电容存储电荷。
6.信号完整性。
（电荷分享，泄露）信号完整性问题：电荷泄露电荷分享电容耦合时钟馈通7.存储器与存储的分类按存储方式分随机存储器：任何存储单元的内容都能被随机存取，且存取时间和存储单元的物理位置无关。
顺序存储器：只能按某种顺序来存取，存取时间和存储单元的物理位置有关。
按存储器的读写功能分只读存储器(ROM)：存储的内容是固定不变的，只能读出而不能写入的半导体存储器。
随机读写存储器(RAM)：既能读出又能写入的半导体存储器。
按信息的可保存性分非永久记忆的存储器：断电后信息即消失的存储器。
1+X集成电路理论考试题(附答案)
1+X集成电路理论考试题（附答案）一、单选题（共39题，每题1分，共39分）1.重力式分选机进行芯片检测时，测试机对芯片测试完毕后，将检测结果通过（）把结果传回分选机。
A、GPIBB、数据线C、串口D、VGA正确答案：A2.化学机械抛光中, 抛光液的作用是()。
A、与硅片表面材料反应,变成可溶物质或将一些硬度过高的物质软化B、向抛光垫施加压力C、将反应生成物从硅片表面却除D、清洗硅片正确答案：A答案解析：硅片固定在抛光盘上后，抛光盘和装有抛光垫的旋转盘开始旋转，同时喷淋抛光液；然后抛光盘向抛光垫施加压力，此时抛光液在硅片和抛光垫之间流动，抛光液中的物质与硅片表面材料反应，变为可溶物质或将一些硬度过高的物质软化；通过研磨作用将反应生成物从硅片表面去除，进入流动的液体排出。
3.当芯片移动到气轨( )时，旋转台吸嘴吸取芯片。
A、首端B、中端C、末端D、任意位置正确答案：C答案解析：当芯片移动到气轨末端时，旋转台吸嘴的升降电机到达芯片正上方，吸嘴产生一定负压将该芯片吸起，升降电机上移并后退进入旋转台，上料完成。
4.在使用J-link驱动连接单片机是需在魔法棒按钮的（）中设置（）。
A、Debug；地址范围B、Debug；工作频率C、Output；地址范围D、Output；工作频率正确答案：A5.封装工艺中，激光打标的文本内容和格式设置完成后，需要（）。
A、点击开始打标按钮B、选择打标文档C、调整光具位置D、点击保存按钮保存设置情况正确答案：D6.在制备完好的单晶衬底上，沿其原来晶向，生长一层厚度、导电类型、电阻率及晶格结构都符合要求的新单晶层，该薄膜制备方法是（）。
A、外延B、热氧化C、PVDD、CVD正确答案：A答案解析：外延是在制备完好的单晶衬底上，沿其原来晶向，生长一层厚度、导电类型、电阻率及晶格结构都符合要求的新单晶层。
7.芯片粘接过程中点银浆之后进入（）步骤。
A、框架上料B、芯片拾取C、框架收料D、银浆固化正确答案：B答案解析：芯片粘接流程为：放置引线框架和晶圆→参数设置→框架上料→点银浆→芯片拾取→框架收料→银浆固化（烘烤箱内进行）。
(完整word版)模拟集成电路设计期末试卷
《模拟集成电路设计原理》期末考试一．填空题（每空1分，共14分)1、与其它类型的晶体管相比,MOS器件的尺寸很容易按____比例____缩小，CMOS电路被证明具有_较低__的制造成本。
2、放大应用时，通常使MOS管工作在_ 饱和_区,电流受栅源过驱动电压控制,我们定义_跨导_来表示电压转换电流的能力。
3、λ为沟长调制效应系数，对于较长的沟道，λ值____较小___（较大、较小）。
4、源跟随器主要应用是起到___电压缓冲器___的作用。
5、共源共栅放大器结构的一个重要特性就是_输出阻抗_很高,因此可以做成___恒定电流源_.6、由于_尾电流源输出阻抗为有限值_或_电路不完全对称_等因素，共模输入电平的变化会引起差动输出的改变。
7、理想情况下，_电流镜_结构可以精确地复制电流而不受工艺和温度的影响，实际应用中，为了抑制沟长调制效应带来的误差，可以进一步将其改进为__共源共栅电流镜__结构。
8、为方便求解，在一定条件下可用___极点—结点关联_法估算系统的极点频率。
9、与差动对结合使用的有源电流镜结构如下图所示,电路的输入电容C in为__ C F（1－A）__。
10、λ为沟长调制效应系数，λ值与沟道长度成___反比__（正比、反比）。
二．名词解释（每题3分，共15分)1、阱解:在CMOS工艺中，PMOS管与NMOS管必须做在同一衬底上,其中某一类器件要做在一个“局部衬底”上，这块与衬底掺杂类型相反的“局部衬底”叫做阱。
2、亚阈值导电效应解:实际上，V GS =V TH 时，一个“弱”的反型层仍然存在,并有一些源漏电流，甚至当V GS <V TH 时,I D 也并非是无限小，而是与V GS 呈指数关系,这种效应叫亚阈值导电效应。
3、沟道长度调制解：当栅与漏之间的电压增大时,实际的反型沟道长度逐渐减小，也就是说,L 实际上是V DS 的函数，这种效应称为沟道长度调制。
4、等效跨导Gm解:对于某种具体的电路结构，定义inDV I ∂∂为电路的等效跨导，来表示输入电压转换成输出电流的能力 5、米勒定理解:如果将图（a ）的电路转换成图（b ）的电路，则Z 1=Z/(1-A V )，Z 2=Z/（1—A V -1），其中A V =V Y /V X .这种现象可总结为米勒定理。
GDOU 广东海洋大学 数字电路试题集.
广东海洋大学 -- 学年第 学期《数字电子技术基础》课程试题课程号： 16632205 ■ 考试 ■ A 卷■ 闭卷□ 考查□ B 卷□ 开卷题 号 一 二 三 四 五 六 七 八 九 十 总分 阅卷教师各题分数10 25 15 30 20 100实得分数一． 填空题。
(每题2分，共10分) 1．将二进制数化为等值的十进制和十六进制：(1100101)2=()10 =()162．写出下列二进制数的原码和补码：(-1011)2=()原=()补3．输出低电平有效的3线 – 8线译码器的输入为110时,其8个输出端07~Y Y 的电平依次为 。
4．写出J 、K 触发器的特性方程： ； 5. TTL 集电极开路门必须外接________才能正常工作。
二．单项选择题。
（1～15每题1分，16～20每题2分，共25分） 1．余3码10001000对应的8421码为（ ）。
A ．01010101 B.10000101 C.10111011 D.11101011 2.使逻辑函数)')(')(''(C A CB B A F +++=为0的逻辑变量组合为( ) A. ABC=000 B. ABC=010 C. ABC=011 D. ABC=110 3．标准或-与式是由（ ）构成的逻辑表达式。
A ．与项相或 B. 最小项相或 C. 最大项相与 D.或项相与班级：姓名：学号：试题共 10页加白纸 1张密封线4. 由或非门构成的基本R、Ｓ触发器，则其输入端R、S应满足的约束条件为（）。
Ａ. R+S=０Ｂ. RS=０Ｃ. R+S=１Ｄ.RS=１5．一个8选一数据选择器的地址输入端有（）个。
A.1B.2C.3D.86．RAM的地址线为16条，字长为32，则此RAM的容量为（）。
A．16×32 位 B. 16K×32位 C. 32K×32位 D.64K×32位7．要使JK触发器在时钟作用下的次态与现态相反，JK端取值应为（）。
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广东工业大学考试2010级
<<数字集成电路分析与设计>>考试
一、计算题（16分）
在一个PMOS 硅栅晶体管中，阱掺杂为3
17cm 107.3−×=D N 。
栅掺杂为320cm 103−×=A N ，栅氧化层厚度为nm ox 2.2t =，二氧化硅表面单位面积正电荷为211cm 106−×个。
（a ）计算无注入零偏置下（0=SB V ）器件的阈值电压。
（10分）
（b ）若希望调节PMOS 的阈值电压至-0.4V ，计算其阈值注入量。
（3分）（c ）为什么PMOS 采用P+多晶硅而不采用N+多晶硅？（3分）
二、计算题（20分）
在CMOS 反相器中：
（a ）与其它反相器相比，CMOS 反相器具有哪些优缺点。
（4分）
（b ）画出其电压传输曲线，并且分析随着输入电压in V 改变，PMOS 和NMOS 工作区
间的转换过程，标注重要临界点。
（8分）
（c ）推导IL V 的表达式。
（8分）
试根据版图画出电路原理图，并写出逻辑表达式。
四、计算题（20分）
采用0.13um工艺，用与非门设计一个SR锁存器的晶体管电路（拓扑结构图）及器件尺寸（逻辑如图2所示），使其从S到Q非和R到Q的延时为200ps，假设Q和Q非驱动的总负载为200fF.
图2
在图3中，计算其最佳路径延时和晶体管尺寸（所有器件都是标准CMOS 门且所有晶体管都有最小长度L=0.1um ）。
使用0.13um 工艺参数，inv C 为最小尺寸反相器的输入电容。
图3
六、画图与读图题（14分）
根据逻辑表达式，画出CMOS 门电路的原理图，并设计其沟道宽度使其与反相器延时相匹配（假设反相器中NMOS 沟道宽度为W ）
（a ）F E D C B A F ⋅+⋅⋅+=)(。
（7分）
（b ）根据图4，写出输入与输出之间的逻辑表达式。
（7分）
图4。