7050SMD HCSL Crystal Oscillator

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Craystal 工作原理介绍

Annealing
Freq. adjustment
Curing
Sealing
Aging
F.Q.C.
O.Q.C.
台灣晶技股份有限公司
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X’TAL Process
SMD X’TAL
Blank cleaning
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(2)
Alignment Curing
Base Plating Blank auto mount Aging Gross leak test Taping
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，A↑，R↓
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Measuring the Crystal Parameters
Pi NetWork Method S&A 250B
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台灣晶技股份有限公司
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Measuring the Crystal Parameters
Pi NetWork Method S&A 250B
台灣晶技股份有限公司
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PiezoElectricity
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(1)
Y
-Si
+4
++
Si +4
X
Si +4
O
-2
O
-2
O -2
++
O -2
O -2
--
O -2
The SiO2 is always in the static state of electric neutrial .
@1atm @1atm @25 ℃ @25 ℃
MECHANICAL AXIS OPTICAL AXIS

直读光谱法测定7050铝合金中锌的不确定度评定

２０１８年第４期194直读光谱法测定７０５０铝合金中锌的不确定度评定覃金珠，陆科呈，兰标景摘　要：介绍了使用火花直读发射光谱法测定７０５０铝合金中锌的测量不确定度评定方法，建立数学模型，分析了检测过程中的不确定度重要来源，包括样品测量过程随机性、类型校准、分析方法、标样定值、数值修约等，根据不确定度传递公式的特点，采用标准不确定度评定各个分量，重点对不确定度Ｂ类评定进行了阐述，并对各个不确定度来源对不确定度的贡献进行评价。

关键词：火花直读光谱法；铝合金；锌；不确定度(广西南南铝加工有限公司，广西南宁 530031)作者简介：覃金珠（１９８７－），女，广西南宁人，助理工程师，研究方向：化学检测研究工作。

直读光谱仪由于操作简单、分析速度快、精度高、检出限低，在冶金、化工、机械等领域都有其重要的地位。

测量不确定度是现代误差理论的重要内容，用不确定度表示测量结果的质量有着重要意义。

JJF1059-2012《测量不确定度的评定与表示》明确指出以不确定度作为量的准确程度的判断，广义来讲测量不确定度即测量结果正确性的可疑程度或不肯定程度，因此测量的水平和质量可以用“测量不确定度”来评价，不确定度较相对误差更能客观体现结果的准确性，测量不确定度也是实验室检测能力最直接的体现，本文以7050铝合金中锌的直读光谱法测定为例，对其锌含量进行了不确定度评定。

１　实验部分１．１　主要仪器与试剂ARL3460火花直读光谱仪，赛默飞世尔科技有限公司；CDS6132卧式车床，大连机床集团有限公司；SS7050铝合金光谱标样，美国铝业公司；无水乙醇，分析纯。

１．２　实验方法试验前使用车床分别将SS7050铝合金光谱标样和7050铝合金样品表面车去一定厚度，加工过程使用无水乙醇进行冷却润滑，以获得光滑表面。

依据GB/T 7999-2015《铝及铝合金光电直读发射光谱分析方法》进行类型校准和样品检测。

２　数学模型按下式计算检测结果：y=x+bx—被测样品Zn 含量的平均值y—被测样品Zn 含量的测定结果b—校正值３　不确定分量及其来源直读光谱分析法测定7050铝合金中锌的不确定度来源主要有：测量过程随机性、类型校准、分析方法本身、环境的温度，湿度以及氩气的纯度和流量的稳定性、光谱标样定值、数值修约等。

深圳市晶科鑫实业有限公司 Crystal Oscillator Series 6N 型号 7.0X5

深圳市晶科鑫实业有限公司样品承认书客户代码：物料名称：贴片钟振规格型号：7050 OSC 50.000MHZ 1.8~3.3V ±30PPM CMOSP N/ SJK：6N50000G33YC承认签章供应商承认（）公司承认制定审核核准工程师审核批准林雁杨霞黄灏东盖章签署盖章签署日期日期批示：□接受□有条件接受备注：公司地址:深圳市龙岗区天安云谷产业园一期3栋C座12楼1204～1206室电话：传真：Approved by: 黄灏东Checked by: 杨霞Issued by: 玉静霞产品规格书SPECIFICATIONPN / SJK: 6N50000G33YC深圳市晶科鑫实业有限公司SHENZHEN CRYSTAL TECHNOLOGY INDUSTRIAL CO., LTD.公司地址:深圳市龙岗区天安云谷产业园一期3栋C座12楼1204～1206室电话：*************-837传真：*************修改记录版次修改日项目改定内容改定者确认者A1 2015-6-5 初版林雁杨霞1. ELECTRICAL SPECIFICATIONSStandard atmospheric conditionsUnless otherwise specified, the standard range of atmospheric conditions for making measurement and tests are as follow:Ambient temperature : 25±5℃Relative humidity : 40%~70%If there is any doubt about the results, measurement shall be made within the following limits: Ambient temperature : 25±3℃Relative humidity : 40%~70%Measure equipmentElectrical characteristics measured by MD 37WX-05M or equivalen t.Crystal cutting typeThe crystal is using AT CUT (thickness shear mode).Parameters SYMElectrical Spec. Notes MIN TYPE MAX UNITS1 Nominal Frequency 50.000000 MHZ2 FrequencyStabilityAT 25℃±10 PPM Over OperatingTemperature range±20 PPM3 Operating Temperature Topr -40 25 85 ℃4 Storage Temperature Tstg -55 ~ 125 ℃5 Supply Voltage VDD 1.8~3.3 ±10% V6 Input Current Icc 15 mA7 Enable Control Yes Pad18 Output Load : CMOS CL 15 pF9 Output Voltage High VoH 90%VddV10 Output Voltage Low VoL 10%VddV11 Rise Time Tr 5 ns 10%→90%VDDLevel12 Fall Time Tf 5 ns 90%→10%VDDLevel13 Symmetry (Duty ratio) TH/T 45 ~ 55 %14 Start-up Time Tosc 10 ms15 Enable Voltage High Vhi 70%VddV16 Disable Voltage Low Vlo 30%VddV17 Aging ±3 ppm/yr. 1st. Year at 25℃18 Output Disable Delay Time T off 150 us19 Output Enable Delay Time T on 150 us20 Phase Jitter （12KHZ~20MHZ）0.5 1.0 ps2. DIMENSIONS (Units :mm)MARKING3. TEST CIRCUITControl input (output enable/disable)Logic 1 or open on pad 1: Oscillator outputLogic 0 on pad 1 : Disable output to high impedance4. PART NUMBER GUIDESJK -6N— 50000 Frequency 50.000MHz — GFrequency tolerance—33Supply voltage — Y Fan out type X:TTL/CMOS — C Temperatur e5. WAVEFORM CONDITIONSWaveform measurement system shouldhave a min. bandwidth of 5 times thefrequency being tested.6. OUTPUT ENABLE / DISABLE DELAYThe following figure shows the oscillator timing during normal operation . Note that when the device is in standby,the oscillator stops. When standby is released, the oscillator starts and stable oscillator output occurs after a short delay7. SUGGESTED REFLOW PROFILE8. STRUCTURE ILLUSTRATIONNO COMPONENTSMATERIALS FINISH/SPECIFICATIONS1 LID Kovar (Fe/Co/Ni)2 Base(Package)Ceramic (AI2O3) + Kovar (Fe/Co/Ni)+ Ag/CuColor black 3 PAD Au Tungsten metalize+ Ni plating + Au plating4 Crystal blank SiO25 Conductive adhesiveAg Silicon resin6 Electrode Noble Metal7 IC chip8 Bonding wire Au Pad 1 options : NC is 5wires , EN is 6 wires.9. PACKING10. RELIABILITY TEST SPECIFICATION1.Mechanical EnduranceNo.Test Item Test Methods REF. DOC 1 Drop Test75 cm height,3 times on concrete floor .JIS C67012 Mechanical Shock Device are shocked to half sine wave ( 1000G ) three mutuallyperpendicular axes each 3 times. 0.5m sec.duration timeMIL-STD-202F3 VibrationFrequency range 10 ~ 2000 HzAmplitude 1.52 mm/20GSweep time 20 minutesPerpendicular axes each test time 4 Hrs(Total test time 12 Hrs)MIL-STD-883E4 Gross Leak Standard Sample For Automatic Gross LeakDetector, Test Pressure: 2kg / cm2MIL-STD-883E5 Fine Leak Helium Bomging 4.5 kgf / cm 2 for 2 Hrs6 SolderabilityTemperature 245 ℃ ± 5℃Immersing depth 0.5 mm minimumImmersion time 5 ± 1 secondsFlux Rosin resin methyl alcoholsolvent ( 1 : 4 )MIL-STD-883E2.Environmental EnduranceNo. Test Item Test Methods REF. DOC1 Resistance To SolderingHeatPre-heat temperature 125 ℃Pre-heat time 60 ~ 120 sec.Test temperature 260 ± 5 ℃Test time 10 ± 1 sec.MIL-STD-202F2 High Temp. Storage + 125 ℃ ±3 ℃ for 1000 ± 12 HrsMIL-STD-883E 3 Low Temp. Storage - 40 ℃ ± 3 ℃ for 1000 ± 12 Hrs4 Thermal Shock Total 100 cycles of the following temperaturecycleMIL-STD-883E5 Pressure CookerStorage121 ± 3℃ , RH100% , 2 bar , 240 Hrs JIS C67016 High Temp＆Humidity 85℃ ± 3℃, RH 85% , 1000 Hrs JIS C5023。

ICS557-03 PCI-Express Gen1时钟源说明书

DATASHEET2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE IDT® 2 OUTPUT PCI-EXPRESS GEN1 CLOCK SOURCE 1ICS557-03REV U 112111DescriptionThe ICS557-03 is a spread spectrum clock generator that supports PCI-Express Gen 1 and Ethernet requirements. The device is used for PC or embedded systems tosubstantially reduce electromagnetic interference (EMI). The device provides two differential (HCSL) spread spectrum outputs. The spread type and amount are configured via select pin. Using IDT’s patentedPhase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies for HCSL, and 25 MHz or 100 MHz for LVDS.Features•Packaged in 16-pin TSSOP•RoHS 5 (green) or RoHS 6 (green and lead free)compliant packaging•Supports HCSL or LVDS output levels •Operating voltage of 3.3 V •Input frequency of 25 MHz •Jitter 60 ps (cycle-to-cycle)•Spread Spectrum capability•Industrial and commercial temperature ranges •For PCIe Gen2 applications, see the 5V41065•For PCIe Gen3 applications, see the 5V41235Block DiagramPin AssignmentOutput Select Table 1 (MHz)Spread Selection Table 2Pin DescriptionsS1S0CLK(1:0), CLK(1:0)0025M 01100M 10125M 11200MSS1SS0Spread%00No Spread01Down -0.510Down -0.7511No SpreadPinNumberPin NamePin TypePin Description1S0Input Select pin 0. See Table1. Internal pull-up resistor.2S1Input Select pin 1. See Table 1. Internal pull-up resistor.3SS0Input Spread Select pin 0. See Table 2. Internal pull-up resistor.4X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.5X2Output Crystal connection. Leave unconnected for clock input.6OE Input Output enable. Tri-states outputs and device is not shut down. Internal pull-up resistor.7GNDXD Power Connect to ground.8SS1InputSpread Select pin 1. See Table 2. Internal pull-up resistor.9IREF Output Precision resistor attached to this pin is connected to the internal currentreference.10CLK1Output HCSL complimentary clock output 1.11CLK1Output HCSL true clock output 1.12VDDODA Power Connect to voltage supply +3.3 V for output driver and analog circuits 13GNDODA PowerConnect to ground.14CLK0Output HCSL complimentary clock output 0.15CLK0Output HCSL true clock output 0.16VDDXDPowerConnect to voltage supply +3.3 V for crystal oscillator and digital circuit.Applications Information External ComponentsA minimum number of external components are required for proper operation.Decoupling CapacitorsDecoupling capacitors of 0.01 μF should be connected between each VDD pin and the ground plane, as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin.CrystalA 25 MHz fundamental mode parallel resonant crystal should be used. This crystal must have less than 300 ppm of error across temperature in order for the ICS557-03 to meet PCI Express specifications.Crystal CapacitorsCrystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency.C L= Crystal’s load capacitance in pFCrystal Capacitors (pF) = (C L- 8) * 2For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16.Current Source (Iref) Reference Resistor - R RIf board target trace impedance (Z) is 50Ω, then R R = 475Ω(1%), providing IREF of 2.32 mA. The output current (I OH) is equal to 6*IREF.Output TerminationThe PCI-Express differential clock outputs of the ICS557-03 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in thePCI-Express Layout Guidelines section.The ICS557-03 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section.General PCB Layout RecommendationsFor optimum device performance and lowest output phase noise, the following guidelines should be observed.1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible.2. No vias should be used between decoupling capacitor and VDD pin.3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical.4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-03.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.PCI-Express Layout GuidelinesPCI-Express Device RoutingTypical PCI-Express (HCSL) WaveformLVDS Compatible Layout GuidelinesLVDS Device RoutingTypical LVDS WaveformAbsolute Maximum RatingsStresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.DC Electrical CharacteristicsUnless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85°C1. Single edge is monotonic when transitioning through region.2. Inputs with pull-ups/-downs are not included.ItemRatingSupply Voltage, VDDXD, VDDODA 7 VAll Inputs and Outputs-0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial)0 to +70°C Ambient Operating Temperature (industrial)-40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°CESD Protection (Input)2000 V min. (HBM)ParameterSymbolConditions Min.Typ.Max.UnitsSupply Voltage V 2.973.33.63V Input High Voltage 1V IH S0, S1, OE, ICLK, SS0, SS1 2.0VDD +0.3V Input Low Voltage 1V IL S0, S1, OE, ICLK, SS0, SS1VSS-0.30.8V Input Leakage Current 2I IL 0 < Vin < VDD -55μA Operating Supply Current I DD 50Ω, 2 pF 78mA I DDOE OE =Low44mA Input Capacitance C IN Input pin capacitance 7pF Output Capacitance C OUT Output pin capacitance 6pF Pin Inductance L PIN 5nH Output Resistance R OUT CLK outputs3.0k ΩPull-up ResistorR PUS0, S1, OE, SS0, SS1100k ΩAC Electrical Characteristics - CLKOUT, HCSLUnless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85°C1T est setup is R L =50 ohms with 2 pF , Rr = 475Ω (1%).2Measurement taken from a single-ended waveform.3 Measurement taken from a differential waveform.4Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.5CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low.ParameterSymbol ConditionsMin.Typ.Max.UnitsInput Frequency 25MHz Output Frequency HCSL termination200MHz Output High Voltage 1,2V OH 660700850mV Output Low Voltage 1,2V OL-150027mV Crossing Point Voltage 1,2Absolute250350550mV Crossing Point Voltage 1,2,4Variation over all edges140mV Jitter, Cycle-to-Cycle 1,380ps Modulation Frequency Spread spectrum3031.533kHz Rise Time 1,2t OR From 0.175 V to 0.525 V 175332700ps Fall Time 1,2t OFFrom 0.525 V to 0.175 V 175344700ps Skew between outputs At crossing point Voltage50ps Duty Cycle 1,34555%Output Enable Time 5All outputs 12us Output Disable Time 5All outputs12us Power-up Time t ST ABLE From power-up VDD=3.3 V 3.0 3.5ms Spread Change Timet SPREADSettling period after spread change3.03.5msAC Electrical Characteristics - CLKOUT, LVDSUnless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85°C1 T est setup is R L =50 ohms with2 pF , Rr = 475Ω (1%).2Measurement taken from a single-ended waveform.3 Measurement taken from a differential waveform.4Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.5CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD= low.Electrical Characteristics - Differential Phase JitterNote 1: Guaranteed by design and characterization, not 100% tested in production.Note 2: See for complete specs.ParameterSymbol ConditionsMin.Typ.Max.UnitsInput Frequency 25MHz Output Frequency LVDS termination100MHz Differential Output Voltage V OD 247454mV Offset VoltageV OS1.1251.375V ∆V OD |Change to V OD |50mV ∆V OS|Change to V OS |50mV Jitter, Cycle-to-Cycle 1,380ps Modulation Frequency Spread spectrum3031.533kHz Slew Rate, Rise 1,3t SLR Measured from ±150 mV from crossing point voltage 14V/ns Slew Rate, Fall 1,3t SLFMeasured from ±150 mV from crossing point voltage 14V/ns Skew between outputs At crossing point Voltage50ps Duty Cycle 1,34555%Output Enable Time 5All outputs 12µs Output Disable Time 5All outputs12µs Power-up Time t STABLE From power-up VDD=3.3 V 3 3.5ms Spread Change Timet SPREADSettling period after spread change33.5msParameterSymbolConditionsMinTypMaxUnitsNotesJitter, Phaset jphasePLLPCIe Gen 1--86ps (p-p)1, 2Thermal CharacteristicsMarking Diagram (ICS557G-03LF)Marking Diagram (ICS557GI-03LF)Notes:1. ###### is the lot code.2. YYWW is the last two digits of the year, and the week number that the part was assembled.3. “LF” designates Pb (lead) free package.4. “I” designates industrial temperature range.5. Bottom marking: (origin). Origin = country of origin of not USA.ParameterSymbolConditionsMin.Typ.Max.UnitsThermal Resistance Junction to AmbientθJA Still air78°C/W θJA 1 m/s air flow 70°C/W θJA 3 m/s air flow68°C/W Thermal Resistance Junction to CaseθJC37°C/WPackage Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)Package dimensions are kept current with JEDEC Publication No. 95Ordering InformationPart / Order Number Marking Shipping Packaging Package Temperature 557G-03LF See Page 8Tubes16-pin TSSOP0 to +70° C557G-03LFT T ape and Reel16-pin TSSOP0 to +70° C557GI-03LF See Page 8Tubes16-pin TSSOP-40 to +85° C557GI-03LFT T ape and Reel16-pin TSSOP-40 to +85° C“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of IntegratedDevice Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks orregistered trademarks used to identify products or services of their respective owners.Printed in USACorporate HeadquartersIntegrated Device Technology, For Sales800-345-7015408-284-8200Fax: 408-284-2775For Tech Support www.idt/go/clockhelpInnovate with IDT and accelerate your future networks. Contact:www.IDT .comCorporate HeadquartersTOYOSU FORESIA, 3-2-24 Toyosu,Koto-ku, Tokyo 135-0061, Japan Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit:/contact/TrademarksRenesas and the Renesas logo are trademarks of RenesasElectronics Corporation. All trademarks and registeredtrademarks are the property of their respective owners.IMPORTANT NOTICE AND DISCLAIMERRENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDINGREFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.(Rev.1.0 Mar 2020)© 2020 Renesas Electronics Corporation. All rights reserved.。

SRe石英晶体振汤器介绍-Y100520

石英晶體振盪器介紹Prepared by :Alan YangIndex1)石英晶片(Quartz)振盪原理2)Crystal & Oscillator 種類與構造3)基本波與倍頻(Fundamental & 3rd Overtone)4)Crystal / Oscillator 種類與應用5)Crystal & Oscillator 參數解析6)振盪迴路搭配分析7)Q & APage.21) 石英晶片(Quartz)振盪原理Page.3Page.4Crystallized quartzmaterial •石英是由矽原子和氧原子組合而成的二氧化矽（Silicon Dioxide, SiO2），以六角柱形式的單結晶結構存在。

(如附圖)•由於石英本身具有壓電效應特性，石英晶體振盪器就是利用此特性製成。

•運用壓電效應可使石英產生振盪，廣泛的運用在電腦、手機等通訊產品及時鐘等等產品上。

石英晶體•正壓電效應•當機械應力加入於一壓電材料時，材料的兩端會伴隨著產生一個與應力大小成比例的電荷(或電壓) ; 當應力方向相反時，電荷的極性(亦即壓電的極性)也隨之逆反。

Page.5•逆壓電效應•當一電位加在晶片表面時, 它就會產生變形或振動現象，掌握這種振動現象，並控制其發生頻率的快慢，以及精確程度，就是水晶震盪器的設計與應用原理。

Page.6石英的切割角度•根據不同的應用及工作溫度需求，搭配不同的石英切割角度種類。

例如AT-, BT-, CT-, DT-, NT, GT…..等Cutting Method & AnglePage.7Page.8•不同的石英切割角度種類，將得到不同的溫度曲線。

•目前最常用的為AT 切割。

(下圖圈選為AT 切割溫度特性)Cutting method & angle V.S. Temp. characteristics•AT切割其頻率對溫度變化為一元三次方曲線(如圖)，在相當寬廣的溫度範圍下, 其頻率對正、負溫度的變化最為對稱。

NDK晶振NP3225SC晶体振荡器规格书

Output Voltage (mV) Rise Time / Fall Time (ns) Symmetry (%) Output Load [RL] (Ω) Start-up Time (ms) Phase Jitter (ps) Specification Number
*1 : The frequency stability includes initial frequency tolerance, temperature variation, and supply variation.
1.6
0.7±0.1
1.1
#6
0.6±0.1
#5
#4 0.5±0.1
0.9
0.8
Please specify the model name, frequency, and specification number when you order products. For further questions regarding specifications, please feel free to contact us.
1606A_NP3225SC_e
■ Specifications
Item Output Type Nominal Frequency Range (MHz) Overall Frequency Tolerance *1 Operating Temperature Range (°C) Supply Voltage [VCC] (V) Current Consumption Enable (mA) Stand-by (μA) +2.5 ± 5 % Max. 15 (STAND-BY=GND) VOL : –150 to +150 (DC characteristics) VOH : +660 to +850 (DC characteristics) Max. 0.5 (0.175 to 0.525V) 45 to 55 (at 50% Waveform) 50 Max. 10 Max. 1 (Offset Frequency : 12kHz to 20MHz) NSC5082A NSC5082B Model NP3225SC HCSL 100 to 170 Max. ±50 ×10-6 −40 to +85 +3.3 ± 10 % Max. 50 (STAND-BY=VCC or OPEN, RL=50Ω)

NDK晶振NP7050S晶体振荡器规格书

■ Specifications
Item Model NP7050S[ ] Single (No selection function) Dual (Select from 2 frequencies) Quad (Select from 4 frequencies) Any Rate (Setable desired frequency by I2C) 15 ≤ f ≤ 2100 15 ≤ f ≤ 2100 LVPECL Max. 95 50Ω(VCC-2.0V) 15 ≤ f ≤ 2100 LVDS Max. 85 100Ω 15 ≤ f ≤ 2100 CML Max. 80 50Ω(VCC) +1.8V±5% +2.5V±5% +3.3V±10% Enable Low Enable High None –40 to +85 –55 to +125 Narrow stability Max. ±10×10-6 Max. ±20×10-6 Narrow stability Typ. 177 Standard stability Max. ±50×10-6 Standard stability Typ. 148 15 ≤ f ≤ 700 HCSL Max. 100 50Ω 15 ≤ f ≤ 200 CMOS Max. 85 15pF
(SPXO)
■ Features
● Supports a wide frequency range. (15 to 2100MHz (Frequency tuning resolution 2×10-9)) ● Frequency selection function (Dual,Quad,Any Rate) ● Low jitter : Typ. 130fs rms (@622.08MHz) ● Five types of output levels : CMOS, LVPECL, LVDS, CML, HCSL ● Supports low power supply voltage : +1.8V, +2.5V, +3.3V

斯帕克斯 Si567 超级系列晶体振荡器数据手册说明书

Ultra Series™ Crystal Oscillator (VCXO) Si567 Data SheetUltra Low Jitter Quad Any-Frequency VCXO (100 fs), 0.2 to3000 MHzThe Si567 Ultra Series™ voltage-controlled crystal oscillator utilizes Skyworks Solutions’ advanced 4th generation DSPLL® technology to provide an ultra-low jitter, low phase noise clock at four selectable frequencies. The device is factory-programmed to provide any four selectable frequencies from 0.2 to 3000 MHz with <1 ppb resolution and maintains exceptionally low jitter for both integer and fractional frequencies across its operating range. On-chip power supply filtering provides industry-leading power supply noise rejection, simplifying the task of generating low jitter clocks in noisy systems that use switched-mode power supplies. Offered in industry-standard footprints, the Si567 has a dramatically simplified supply chain that enables Skyworks to ship custom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si567 uses one simple crystal anda DSPLL IC-based approach to provide the desired output frequencies. TheSi567 is factory-configurable for a wide variety of user specifications, including frequency, output format, and OE pin location/polarity. Specific configurations are factory-programmed at time of shipment, eliminating the long lead times associ-ated with custom oscillators.KEY FEATURES•Available with any four selectable frequencies from 200 kHz to 3000 MHz•Ultra low jitter: 100 fs RMS typical(12 kHz – 20 MHz)•Excellent PSNR and supply noise immunity:–80 dBc Typ•3.3 V, 2.5 V and 1.8 V V DD supply operationfrom the same part number•LVPECL, LVDS, CML, HCSL, CMOS, and DualCMOS output options•2.5x3.2, 3.2x5, 5x7 mm package options•Samples available with 1-2 week lead timesAPPLICATIONS•100G/200G/400G OTN, coherent optics•10G/25G/40G/100G Ethernet•56G/112G PAM4 clocking•3G-SDI/12G-SDI/24G-SDI broadcast video•Servers, switches, storage, NICs, searchacceleration•Test and measurement•FPGA/ASIC clocking5 x 7 mm and 3.2 x 5 mm 2.5 x 3.2 mmPin AssignmentsGNDOEVDDCLK+CLK–VCFS1FS0(Top View)Fixed FrequencyLowNoiseDriverNoise Rejection(Pin Control)VcSi567 Data Sheet • Ordering Guide1. Ordering GuideThe Si567 VCXO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Sky-works Solutions provides an online part number configuration utility to simplify this process. Refer to https:///en/ Products/Timing-Oscillators to access this tool and for further ordering instructions.Notes:1.Contact Skyworks for non-standard configurations.2.Create custom part numbers at https:///en/Products/Timing-Oscillators.3.Min Absolute Pull Range (APR) includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.a.For best jitter and phase noise performance, always choose the smallest Kv that meets the application’s minimum APR re-quirements. Unlike SAW-based solutions which require higher Kv values to account for their higher temperature dependence, the Si56x series provides lower Kv options to minimize noise coupling and jitter in real-world PLL designs.b.APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an APR of ±20 ppm is able to lock to aclock with a ±20 ppm stability over 20 years over all operating conditions.c.APR (±) = (0.5 x VDD x tuning slope) - (initial accuracy + temp stability + load pulling + VDD variation + aging).d.Minimum APR values noted above include absolute worst case values for all parameters.e.See application note, "AN266: VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR)" for more information.1.1 Technical SupportOscillator Phase Noise Lookup Utility https:///tools/oscillator-phase-noiseQuality and Reliability https:///qualityDevelopment Kits https:///en/Products/Timing2. Electrical SpecificationsTable 2.1. Electrical Specifications V DD = 1.8 V, 2.5 or 3.3 V ± 5%, T A = –40 to 85 ºCFigure 2.1. Typical Clock Output Swing Amplitudes vs. FrequencyTable 2.2. V C Control Voltage InputV DD = 1.8, 2.5 or 3.3 V ± 5%, T A = –40 to 85 ºCTable 2.3. Clock Output Phase Jitter and PSNR V DD = 1.8 V, 2.5 or 3.3 V ± 5%, T A = –40 to 85 ºCTable 2.4. 3.2 x 5 mm Clock Output Phase Noise (Typical)Figure 2.2. Phase Jitter vs. Output FrequencyPhase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for >700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase NoiseLookup Tool at https:///en/Products/Timing-Oscillators.Table 2.5. Environmental Compliance and Package InformationTable 2.6. Thermal Conditions1Max Junction Temperature = 125° CTable 2.7. Absolute Maximum Ratings13. Dual CMOS BufferDual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This feature enables replacement of multiple VCXOs with a single Si567 device.ComplementaryOutputsIn-Phase OutputsFigure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase OutputsSi567 Data Sheet • Dual CMOS Buffer4. Recommended Output TerminationsThe output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.AC-Coupled LVPECL – Thevenin TerminationDC-Coupled LVPECL – Thevenin TerminationReceiverAC-Coupled LVPECL - 50 Ω w/VTT Bias DC-Coupled LVPECL - 50 Ω w/VTT BiasFigure 4.1. LVPECL Output TerminationsDC-Coupled LVDSSource Terminated HCSLAC-Coupled LVDS Destination Terminated HCSLReceiverReceiverFigure 4.2. LVDS and HCSL Output TerminationsCML Termination without VCMSingle CMOS TerminationCML Termination with VCMDual CMOS TerminationReceiverReceiverReceivers Si56xSi56x Figure 4.3. CML and CMOS Output Terminations5. Package Outline5.1 Package Outline (5x7 mm)The figure below illustrates the package details for the 5x7 mm Si567. The table below lists the values for the dimensions shown in the illustration.Figure 5.1. Si567 (5x7 mm) Outline DiagramTable 5.1. Package Diagram Dimensions (mm)Table 5.2. Package Diagram Dimensions (mm)Table 5.3. Package Diagram Dimensions (mm)6. PCB Land Pattern6.1 PCB Land Pattern (5x7 mm)The figure below illustrates the 5x7 mm PCB land pattern for the Si567. The table below lists the values for the dimensions shown in the illustration.Figure 6.1. Si567 (5x7 mm) PCB Land PatternTable 6.1. PCB Land Pattern Dimensions (mm)Table 6.2. PCB Land Pattern Dimensions (mm)Table 6.3. PCB Land Pattern Dimensions (mm)7. Top Markings7.1 Top Marking (5x7 and 3.2x5 Packages)The figure below illustrates the mark specification for the Si567 5x7 and 3.2x5 package sizes. The table below lists the line information.Figure 7.1. Mark SpecificationTable 7.1. Si567 Top Mark Description7.2 Top Marking (2.5x3.2 Package)The figure below illustrates the mark specification for the Si567 2.5x3.2 package sizes. The table below lists the line information.Figure 7.2. Mark SpecificationTable 7.2. Si567 Top Mark Description8. Revision HistoryRevision 206624AMay, 2023•Updated Min and Nom package diagram dimensions specs in 5.3 Package Outline (2.5x3.2 mm). Revision 1.3June, 2021•Updated Ordering Guide and Top Mark for Rev C silicon.•Added HCSL-Fast (faster t R/t F) ordering option.•Updated Table 2.1, Powerup VDD Ramp Rate.Revision 1.2September, 2020•Added 2.5 x 3.2 mm package option.•Updated Table 2.1, Powerup VDD Ramp Rate and LVDS Swing.Revision 1.0June, 2018•Initial draftCopyright © 2022 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSL Y DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESUL T FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, ClockBuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at , are incorporated by reference.SkyworksSolutions,Inc.|Nasdaq:SWKS|*********************| Portfolio Quality /quality SW/HW /CBPro Support & Resources/support。

SiT9366数据手册-1-220MHz任意频率SiTime低抖动差分晶振

Output Characteristics VOD ΔVOD VOS ΔVOS Tr, Tf 250 – 1.125 – – – – – – 400 450 50 1.375 50 470 mV mV V mV ps See Figure 4 See Figure 4 See Figure 4 See Figure 4 Measured with 2 pF capacitive loading to GND, 20% to 80%, see Figure 5 f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -40 to 85ºC f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC and -40 to 105ºC f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask integration bandwidth = 1.875 MHz to 20 MHz, includes spurs, all Vdd levels. f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC and -40 to 85ºC f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC and -40 to 105ºC f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter mask integration bandwidth = 1.875 MHz to 20 MHz, includes spurs, all Vdd levels.

Silicon Lab Si5395 12路超低抖动时钟倍频器解决方案

Silicon Lab公司的Si5395/94/92抖动衰减器组合了第四代DSPLL™和Multi-Synth™技术,提供了超低抖动(69fs),可用于高性能的应用如56G SerDes.所有的PLL元件集成在单片上,从而消除和分立解决方案有关的噪音耦合问题.器件级别J/K/L/M/E集成了基准以节省板的空间,提高系统可靠性,降低由温度梯度所引起的声发射噪声效应,而级别A/B/C/D/P则采用外接晶体(XTAL)或晶体振荡器(XO)基准.级别P的抖动为69fs RMS,级别E的抖动为71fs RMS.输入频率范围,差分为8 kHz 到 750 MHz, LVCMOS为8 kHz 到 250 MHz;而输出频率范围,差分为100Hz 到 1028 MHz, LVCMOS为100Hz 到 250 MHz.器件满足G.8262, E.8262.1 EEC标准.主要用在56G/112G PAM4 SerDes时钟,OTN多发探测仪和转发器,10/40/100/200/400G网络线路卡, 10/40/100/400 GbE同步以太网(ITU-TG.8262),医疗图像和测试测量.本文介绍了Si5395/94/92主要特性,简化框图和框图,典型56G SerDes应用电路和同步线路卡SyncE电路图以及评估板Si5394 EVB主要特性,功能框图和电路图与材料清单.The Si5395/94/92 Jitter attenuators combine fourth-generation DSPLL™ and Multi-Synth™ technologies to deliver ultra-low jitter (69 fs) for highperformance applications like 56G SerDes. They are used in applicationsthat demand the highest levelof integration and jitter performance. All PLL components are integrated on-chip,eliminating the risk of noise coupling associated with discrete solutions. Devicegrades J/K/L/M/E have anintegrated reference to save board space, improve systemreliability andreduces the effect of acoustic emissions noise caused bytemperatureramps. Grades A/B/C/D/P use an external crystal (XTAL) orcrystal oscillator(XO) reference.The Si5395/94/92 support free-run, synchronous and holdover modes as well as enhancedhitless switching, minimizing the phase transientsassociated when switching between input clocks. These devices areprogrammable via a serial interface with incircuit programmable non-volatile memory (NVM) so they always power up withaknown frequency configuration. Programming the Si5395/94/92 is easy with SiliconLabs’ ClockBuilderTM Pro software. Factory preprogrammed devices are also available.Si5395/94/92主要特性:• Generates any combination of outputfrequencies from any inputfrequency• Ultra low phase jitter:• 69 fs RMS (Grade P)• 71 fs RMS (Grade E)• 85 fs RMS (integer mode)• 100 fs RMS (fractional mode)• Enhanced hitless switching minimizes outputphase transients (0.2 ns typ)Silicon Lab Si5395 12路超低抖动时钟倍频器解决方案• Input frequency range• Differential: 8 kHz to 750 MHz• LVCMOS: 8 kHz to 250 MHz• Output frequency range• Differential: 100 Hz to 1028 MHz• LVCMOS: 100 Hz to 250 MHz• Meets G.8262, E.8262.1 EEC Standards• Status monitoring• Si5395: 4 input, 12 output• Si5394: 4 input, 4 output• Si5392: 4 input, 2 output• External reference: Grades A/B/C/D/P• Integrated reference: Grades J/K/L/M/E• Drop-in compatible with Si5345/44/42Si5395/94/92应用:• 56G/112G PAM4 SerDes clocking• OTN muxponders and transponders• 10/40/100/200/400G networking line cards• 10/40/100/400 GbE Synchronous Ethernet (ITU-T G.8262)• Medical imaging• Test and measurement 图1:Si5395/94/92框图图2:Si5395/94/92简化框图Si5395/94/92详细特性如下:• Generates any output frequency in any format from any inputfrequency • External XTAL or XO reference (A/B/C/D/P)• Integrated reference (J/K/L/M/E)• Ultra-low phase jitter of 69 fs (P-Grade)• Dynamic phase adjust• Input frequency range• Differential: 8 kHz–750 MHz• LVCMOS: 8 kHz–250 MHz• Output frequency range• Differential: 100 Hz to 1028 MHz• LVCMOS: 100 Hz to 250 MHz• Programmable jitter attenuation bandwidth: 0.1 Hz to 4 kHz • Meets requirements of:• ITU-T G.8262 (SyncE) EEC Options 1 and 2• ITU-T G.8262.1 (Enhanced SyncE) eEEC• Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable signal amplitude• Status monitoring (LOS, OOF, LOL)• Enhanced hitless switching for 8 kHz, 19.44 MHz, 25 MHz inputsand other frequencies• Locks to gapped clock inputs• Free-run and holdover modes• Drop-in compatible with Si5345/44/42• Optional zero delay mode• Fast-lock acquisition for low nominal bandwidths• Independent Frequency-on-the fly for each MultiSynth• DCO mode: as low as 0.001 ppb step size• Core voltage• VDD: 1.8 V ±5%• VDDA: 3.3 V ±5%• Independent output clock supply pins• 3.3 V, 2.5 V, or 1.8 V• Serial interface: I2C or SPI• In-circuit programmable with non-volatile OTP memory• ClockBuilder Pro software simplifies device configuration • Si5395: 4 input, 12 output• Grade A/B/C/D/P: 64-QFN 9×9 mm• Grade J/K/L/M/E: 64-LGA 9x9 mm• Si5394: 4 input, 4 output• Grade A/B/C/D/P: 44-QFN 7×7 mm• Grade J/K/L/M/E: 44-LGA 7x7 mm• Si5392: 4 input, 2 output• Grade A/B/C/D/P: 44-QFN 7×7 mm• Grade J/K/L/M/E: 44-LGA 7x7 mm• Temperature range: –40 to +85 ℃• Pb-free, RoHS-6 compliant图3:典型56G SerDes应用电路图4:同步线路卡SyncE电路图。

Si52258-EVB 自动汽车级PCIe参考时钟生成器评估板用户指南说明书

UG399: Si52258-EVB User's Guide (Using Si52258-D01-AM-QFN40-EVB)The Si52258-EVB is used for evaluating the eight output Si52258A-D01AM Auto-motive grade PCIe Reference Clock Generator. The Si52258A-D01AM device usesthe on-board 25 MHz crystal as reference clock source and generates 8 copies of a100 MHz HCSL format output clock compliant to PCIe Gen 1/2/3/4/5 common clockand separate reference clock specifications.EVB FEATURES •Powered from either USB port or external +5Vpower supply.•On-board 25 MHz crystal reference.•Programmable device core VDD supply foroperation at 3.3 V, 2.5 V, or 1.8 V.•Programmable VDDO (output driver) suppliesallow each of the clock output banks to have itsown power supply voltage selectable from 3.3V, 2.5 V, or 1.8 V.•SMA connectors for all output clocks.•PCIe compliant spread spectrum enabled/disabled via on-board switch.•Internal output termination switch selectable for100 Ω or 85 Ω operation.•Output enable (OE) control switch per output.•All output trace lengths matched to 10 inches.•Loss of Signal (LOS) indication LED.Table of Contents1. Functional Block Diagram (3)2. Si52258-EVB Operation (4)2.1 EVB Configuration: Switches & Jumpers (4)3. LEDs (6)4. Output Clocks (7)5. Si52258-EVB Rev 1.0 Schematics (8)UG399: Si52258-EVB User's Guide (Using Si52258-D01-AM-QFN40-EVB) • LEDs3. LEDsThe Si52258-EVB has 2 LEDs defined below.D2: Blue LED indicating +5V presence.D3: Red LED indicating Loss of Signal (LOS). When lit, this LED indicates a problem was detected with the crystal or crystal oscillator circuit which is preventing proper oscillation, resulting in a loss or degradation of the input reference for the Clock Generator.4. Output ClocksThe Si52258-EVB supports all 8 differential pair output clocks, each terminated as shown in the figure below. The EVB has locations to install 2 pf parallel termination capacitors if desired, which are tagged with “NI” in schematic to indicate they are not installed by default.The outputs are otherwise direct DC coupled to the SMA connectors. Convenient connection pads are also provided for measuring the output with a differential probe, in which case removal of the 0 Ω resistors to isolate the SMA “stub” from the transmission line issuggested.Figure 4.1. Si52258-EVB Output Clock Differential Pair Termination CircuitUG399: Si52258-EVB User's Guide (Using Si52258-D01-AM-QFN40-EVB) • Output Clocks。

晶振SMD7050

Input
Current Consumption
Temperature Output
Supply Voltage
Operating
Storage
Waveform
Load
Symmetry
Rise Time
TR
Fall Time
TF
Current
VoH Voltage
VoL
Enable/Disable Function (Pin 1)
● Pulling Range Codes (ppm)
A = + 50
B = + 70
C = + 100
E = + 60
F = + 90
N = N/A
● Marking
Frequency + C (Holder: CXO) + Date code ( Year Code + Month Code ) NEWXTAL (Company brand)
1 = 0 to +70 7 = 0 to +100
2 = -10 to +70 8 = 0 to +60
3 = -20 to +70 9 = -30 to +65
4 = -40 to +85 A = -55 to +125
5 = -10 to +60 B = -30 to +80
6 = -20 to +60 C = -10 to +50
Packing
C= CXO S=SMD
1=7.0x5.0
See tables
1=3.3 2=5.0

CF5009CN2中文资料

SM5009 seriesCrystal Oscillator Module ICsOVERVIEWThe SM5009 series are crystal oscillator module ICs that incorporate low crystal current type oscillating circuit to limit oscillator-stage current, so that they can reduce crystal current lower than the existing products. Since the oscillating circuit has oscillator capacitors with excellent frequency response and feedback resistor built-in,just connecting crystal realizes stable fundamental oscillation responding up to 40MHz. The SM5009 series are ideal for SMD type crystal oscillator using a strip-shaped crystal blank.FEATURESI Low crystal current oscillatorI Up to 40MHz operating frequency range (funda-mental oscillation)IOperating supply voltage range •3V operation: 2.7 to 3.6V •5V operation: 4.5 to 5.5VI –40 to 85 ° C operating temperature range I Oscillation capacitors C G , C D built-inI Inverter ampliﬁer feedback resistor built-in IStandby function•Oscillator stops (AL series), high impedance in standby mode ILow standby current•Power-save pull-up resistor built-in (AL series) I Frequency divider built-in (f O , f O /2, f O /4, f O /8,f O /16, f O /32 determined by internal connection) IOutput drive capability•AL × , AN × , AK × , CN × : 16mA (V DD = 4.5V)•AH × : 4mA (V DD = 4.5V) I Output load: C L = 50pF max. IOutput duty level•CMOS level (1/2 VDD): AL × , AN × , AH × , CN × •TTL level (1.4V): AK ×I Molybdenum-gate CMOS process I 8-pin SOP (SM5009 ××× S) IChip form (CF5009 ××× )SERIES CONFIGURATIONAPPLICATIONSISMD type crystal oscillator moduleORDERING INFORMATIONVersion 1 1. Package devices (8-pin SOP) have designation SM5009 ××× S.3V operation 5V operationOutputduty level Output frequency INH Input levelStandby modeRecommended operating frequency range 2 [MHz]2. The recommended operating frequency is a yardstick value derived from the crystal used for NPC characteristics authentication. However, the oscil-lator frequency band is not guaranteed. Speciﬁcally, the characteristics can vary greatly due to crystal characteristics and mounting conditions, so the oscillation characteristics of components must be carefully evaluated. Output load 3 (max) [pF]3. Output load value is the maximum load capacitance that allows drive.Recommended operating frequency range 2 [MHz]Output load 3 (max) [pF]Oscillator stop functionOutput stateCF5009AL1Up to 4050Up to 4050CMOS f O CMOS Yes Hi-ZCF5009AL2f O /2CF5009AL3f O /4CF5009AL4f O /8CF5009AL5f O /16CF5009AL6f O /32CF5009AN1Up to 4030Up to 4050CMOSf O TTL No Hi-ZCF5009AN2f O /2CF5009AN3CMOS/TTLf O /4CF5009AN4f O /8CF5009AN5f O /16CF5009AN6f O /32CF5009CN1Up to 3015Up to 3050CMOS f O TTL No Hi-Z CF5009CN2f O /2CF5009AK1––Up to 4015TTLf O TTLNoHi-ZCF5009AK2f O /2CF5009AH1Up to 1615Up to 3015CMOS f O TTL No Hi-ZCF5009AH2f O /2CF5009AH3f O /4CF5009AH4f O /8Device Package SM5009 ××× S 8-pin SOP CF5009 ×××–1Chip formSM5009 seriesPAD LAYOUT(Unit: µ m)PINOUT(Top view)PIN DESCRIPTION and PAD DIMENSIONS1XT VSSQVDD 423NC NC 8765XTINH NumberNameI/ODescriptionPad dimensions [µm]X Y 1INH I Output state control input. Standby mode when LOW, pull-up resistor built-in. In the case of the CF5009AL ×, the oscillator stops and power-save pull-up resistor built in to reduce current consumption at standby mode.1952122XT I Ampliﬁer input.Crystal oscillator connection pins.Crystal oscillator connected between XT and XT3852123XT O Ampliﬁer output.5752124VSS –Ground7662125Q O Output. Output frequency (f O , f O /2, f O /4, f O /8, f O /16, f O/32) determined by internal connection 76510626NC –No connection ––7NC –No connection ––8VDD–Supply voltage1621062SM5009 seriesPACKAGE DIMENSIONS(Unit: mm)• 8-pin SOPBLOCK DIAGRAMNotes.The SM5009 series reduce crystal current by limiting driving current of oscillating-stage inverter and inhibiting oscillating amplitude. Depending on the characteristics of using crystal or the mounting condition, they may not oscillate normally. Please evaluate the oscillation start-up characteris-tics adequately with your actual device.SM5009 seriesFUNCTIONAL DESCRIPTIONStandby Function5009 AL × seriesWhen INH goes LOW, the oscillator stops and the oscillator output on Q becomes high impedance.5009AH ×, AK ×, AN ×, CN × seriesWhen INH goes LOW, the output on Q becomes high impedance, but internally the oscillator does not stop.Power-save Pull-up Resistance (AL × series only)The INH pull-up resistance changes in response to the input level (HIGH or LOW). When INH goes LOW (standby state), the pull-up resistance becomes large to reduce the current consumption during standby.Current consumption and Output waveform with NPC’s standard crystalVersion INH QOscillator AL × seriesHIGH (or open)Any f O , f O /2, f O /4, fO /8, f O /16 or f O/32 output frequency Normal operationLOW High impedanceStopped AH ×, AK ×, AN ×, CN × seriesHIGH (or open)Any f O , f O /2, f O /4, f O /8, f O /16 or f O/32 output frequency Normal operation LOWHigh impedanceNormal operationf [MHz]R [Ω]L [mH]Ca [fF]Cb [pF]3017.2 4.36 6.46 2.264016.82.905.472.08SM5009 seriesSPECIFICATIONSAbsolute Maximum RatingsV SS = 0V unless otherwise noted.Recommended Operating ConditionsV SS = 0V unless otherwise noted.ParameterSymbol ConditionRating Unit Supply voltage range V DD − 0.5 to +7.0V Input voltage range V IN − 0.5 to V DD + 0.5V Output voltage range V OUT−0.5 to V DD + 0.5V Operating temperature range T opr −40 to +85°C Storage temperature range T stg Chip form −65 to +150°C 8-pin SOP−55 to +125Output current I OUT 25mA Power dissipationP D8-pin SOP 500mWParameterSymbolVersion ConditionRatingUnit min typ max Supply voltageV DDAH × f ≤ 30MHz 4.5– 5.5V f ≤ 16MHz 2.7– 3.3AK × f ≤ 40MHz 4.5– 5.5V AN ×f ≤ 40MHz 2.7– 5.5V CN ×f ≤ 30MHz2.7– 5.5VAL ×Chip formf ≤ 40MHz2.7– 5.5V f ≤ 30MHz 2.3– 2.7f ≤ 20MHz 2.25– 2.758-pin SOPf ≤ 40MHz 2.7– 5.5f ≤ 14.4MHz2.4– 2.7Input voltageV INAll version V SS –V DD V Operating temperatureT OPRAH × f ≤ 30MHz, 4.5V ≤ V DD ≤ 5.5V − 40–+ 85°C f ≤ 16MHz, 2.7V ≤ V DD ≤ 3.6V − 20–+ 80AK ×f ≤ 30MHz − 40–+ 85°C 30MHz < f ≤ 40MHz − 20–+ 80AN ×Chip formf ≤ 40MHz, 2.7V ≤ V DD < 4.5V − 20–+ 80°C f ≤ 40MHz, 4.5V ≤ V DD ≤ 5.5V − 40–+ 858-pin SOPf ≤ 40MHz, 2.7V ≤ V DD < 4.5V − 20–+ 80f ≤ 40MHz, 4.5V ≤ V DD ≤ 5.5V − 20–+ 80f ≤ 30MHz, 4.5V ≤ V DD ≤ 5.5V− 40–+ 85CN ×f ≤ 30MHz, 2.7V ≤ V DD < 4.5V − 10–+ 70°C f ≤ 30MHz, 4.5V ≤ V DD ≤ 5.5V− 40–+ 85AL ×Chip formf ≤ 40MHz, 2.7V ≤ V DD ≤ 5.5V− 40–+ 85°C f ≤ 30MHz, 2.3V ≤ V DD ≤ 2.7V − 20–+ 80f ≤ 20MHz, 2.25V ≤ V DD ≤ 2.75V − 20–+ 808-pin SOPf ≤ 40MHz, 2.7V ≤ V DD ≤ 5.5V − 20–+ 80f ≤ 30MHz, 2.7V ≤ V DD ≤ 5.5V − 40–+ 85f ≤ 14.4MHz, 2.4V ≤ V DD ≤ 2.7V − 20–+ 80Electrical Characteristics5009AL× series3V operation: V DD = 2.7 to 3.3V, V SS = 0V, Ta = −40 to 85°C unless otherwise noted.Parameter Symbol ConditionRatingUnit min typ maxHIGH-level output voltage V OH Q: Measurement cct 1, I OH = 8mA 2.2––V LOW-level output voltage V OL Q: Measurement cct 1, I OL = 8mA––0.4V HIGH-level input voltage V IH INH0.7V DD––V LOW-level input voltage V IL INH––0.3V DD VOutput leakage current I Z Q: Measurement cct 2, INH = LOW, V OH = V DD––10µA Q: Measurement cct 2, INH = LOW, V OL = V SS––10Current consumption I DD INH = open, Measurement cct 3,load cct 2, C L = 15pF,40MHz crystal oscillatorCF5009AL1–817mACF5009AL2–511CF5009AL3–49CF5009AL4–37CF5009AL5–36CF5009AL6–25INH = open, Measurement cct 3,load cct 2, C L = 15pF,40MHz crystal oscillator,Ta = –20 to +80°CSM5009AL1S–817SM5009AL2S–511SM5009AL3S–49SM5009AL4S–37SM5009AL5S–36SM5009AL6S–25Standby current I ST INH = V SS, Measurement cct 3–25µAINH pull-up resistance R UP1Measurement cct 4, V DD = 3V, INH = V SS0.6–12MΩR UP2Measurement cct 4, V DD = 3V, INH = 2.1V40–200kΩNegative resistance−R L V DD = 3V, Ta = 25°C, 40MHz––200–ΩFeedback resistance R f Measurement cct 50.4– 1.1MΩBuilt-in capacitance C GDesign value. A monitor pattern on a wafer is tested.5.5866.42pFC D9.31010.7pF5V operation: V DD = 4.5 to 5.5V, V SS = 0V, Ta = −40 to 85°C unless otherwise noted.Parameter Symbol ConditionRatingUnit min typ maxHIGH-level output voltage V OH Q: Measurement cct 1, I OH = 16mA 4.0––V LOW-level output voltage V OL Q: Measurement cct 1, I OL = 16mA––0.4V HIGH-level input voltage V IH INH0.7V DD––V LOW-level input voltage V IL INH––0.3V DD VOutput leakage current I Z Q: Measurement cct 2, INH = LOW, V OH = V DD––10µA Q: Measurement cct 2, INH = LOW, V OL = V SS––10Current consumption I DD INH = open, Measurement cct 3,load cct 2, C L = 15pF,40MHz crystal oscillatorCF5009AL1–1226mACF5009AL2–817CF5009AL3–613CF5009AL4–511CF5009AL5–510CF5009AL6–49INH = open, Measurement cct 3,load cct 2, C L = 15pF,40MHz crystal oscillator,Ta = –20 to +80°CSM5009AL1S–1226SM5009AL2S–817SM5009AL3S–613SM5009AL4S–511SM5009AL5S–510SM5009AL6S–49Standby current I ST INH = V SS, Measurement cct 3–615µAINH pull-up resistance R UP1Measurement cct 4, V DD = 5V, INH = V SS0.3–6MΩR UP2Measurement cct 4, V DD = 5V, INH = 3.5V40–200kΩNegative resistance−R L V DD = 5V, Ta = 25°C, 40MHz––400–ΩFeedback resistance R f Measurement cct 50.4– 1.1MΩBuilt-in capacitance C GDesign value. A monitor pattern on a wafer is tested.5.5866.42pFC D9.31010.7pF5009AN×/CN× series3V operation: V DD = 2.7 to 3.3V, V SS = 0V, Ta = −20 to 80°C unless otherwise noted.Parameter Symbol ConditionRatingUnit min typ maxHIGH-level output voltage V OH Q: Measurement cct 1, I OH = 8mA SM5009AN1S, CF5009AN1SM5009AN2S, CF5009AN22.2––V SM5009AN3S, CF5009AN3SM5009AN4S, CF5009AN4SM5009AN5S, CF5009AN5SM5009AN6S, CF5009AN6SM5009CN1S, CF5009CN1SM5009CN2S, CF5009CN22.1––LOW-level output voltage V OL Q: Measurement cct 1, I OL = 8mA––0.4V HIGH-level input voltage V IH INH 2.0––V LOW-level input voltage V IL INH––0.3VOutput leakage current I Z Q: Measurement cct 2, INH = LOW, V OH = V DD––10µA Q: Measurement cct 2, INH = LOW, V OL = V SS––10Current consumption I DD INH = open, Measurement cct 3,load cct 2, C L = 15pF,40MHz crystal oscillatorSM5009AN1S, CF5009AN1–817mASM5009AN2S, CF5009AN2–511SM5009AN3S, CF5009AN3–49SM5009AN4S, CF5009AN4–37SM5009AN5S, CF5009AN5–36SM5009AN6S, CF5009AN6–25INH = open, Measurement cct 3,load cct 2, C L = 15pF,30MHz crystal oscillator,Ta = –10 to +70°CSM5009CN1S, CF5009CN1–715SM5009CN2S, CF5009CN2–49INH pull-up resistance R UP Measurement cct 4, V DD = 3V, INH = V SS40–200kΩNegative resistance−R L V DD = 3V, Ta = 25°C, 40MHz––100–ΩFeedback resistance R f Measurement cct 50.4– 1.1MΩBuilt-in capacitance C GDesign value. A monitor pattern on a wafer is tested.5.5866.42pFC D9.31010.7pF5V operation: V DD = 4.5 to 5.5V, V SS = 0V, Ta = −40 to 85°C unless otherwise noted.Parameter Symbol ConditionRatingUnit min typ maxHIGH-level output voltage V OH Q: Measurement cct 1, I OH = 16mA SM5009AN1S, CF5009AN1SM5009AN2S, CF5009AN24.0––V SM5009AN3S, CF5009AN3SM5009AN4S, CF5009AN4SM5009AN5S, CF5009AN5SM5009AN6S, CF5009AN6SM5009CN1S, CF5009CN1SM5009CN2S, CF5009CN23.9––LOW-level output voltage V OL Q: Measurement cct 1, I OL = 16mA––0.4V HIGH-level input voltage V IH INH 2.0––V LOW-level input voltage V IL INH––0.8VOutput leakage current I Z Q: Measurement cct 2, INH = LOW, V OH = V DD––10µA Q: Measurement cct 2, INH = LOW, V OL = V SS––10Current consumption I DD INH = open, Measurement cct 3,load cct 2, C L = 15pF,40MHz crystal oscillatorCF5009AN1–1226mACF5009AN2–817CF5009AN3–613CF5009AN4–511CF5009AN5–510CF5009AN6–49INH = open, Measurement cct 3,load cct 2, C L = 15pF,40MHz crystal oscillator,Ta = –20 to +80°CSM5009AN1S–1226SM5009AN2S–817SM5009AN3S–613SM5009AN4S–511SM5009AN5S–510SM5009AN6S–49INH = open, Measurement cct 3,load cct 2, C L = 15pF,30MHz crystal oscillatorSM5009CN1S, CF5009CN1–1022SM5009CN2S, CF5009CN2–715INH pull-up resistance R UP Measurement cct 4, V DD = 5V, INH = V SS40–200kΩNegative resistance−R L V DD = 5V, Ta = 25°C, 40MHz––210–ΩFeedback resistance R f Measurement cct 50.4– 1.1MΩBuilt-in capacitance C GDesign value. A monitor pattern on a wafer is tested.5.5866.42pFC D9.31010.7pF5009AK× seriesV DD = 4.5 to 5.5V, V SS = 0V, Ta = −40 to 85°C unless otherwise noted.Parameter Symbol ConditionRatingUnit min typ maxHIGH-level output voltage V OH Q: Measurement cct 1, I OH = 16mA 4.0––V LOW-level output voltage V OL Q: Measurement cct 1, I OL = 16mA––0.4V HIGH-level input voltage V IH INH 2.0––V LOW-level input voltage V IL INH––0.8VOutput leakage current I Z Q: Measurement cct 2, INH = LOW, V OH = V DD––10µA Q: Measurement cct 2, INH = LOW, V OL = V SS––10Current consumption I DD INH = open, Measurement cct 3,load cct 1, C L = 15pF,40MHz crystal oscillator,Ta = –20 to +80°CSM5009AK1S–1226mACF5009AK1–1226SM5009AK2S–817CF5009AK2–817INH pull-up resistance R UP Measurement cct 4, V DD = 5V, INH = V SS40–200kΩNegative resistance−R L V DD = 5V, Ta = 25°C, 40MHz––210–ΩFeedback resistance R f Measurement cct 50.4– 1.1MΩBuilt-in capacitance C GDesign value. A monitor pattern on a wafer is tested.5.5866.42pFC D9.31010.7pF5009AH × series3V operation: V DD = 2.7 to 3.3V , V SS = 0V , Ta = −20 to 80°C unless otherwise noted.5V operation: V DD = 4.5 to 5.5V , V SS = 0V , Ta = −40 to 85°C unless otherwise noted.Parameter Symbol ConditionRatingUnit min typ max HIGH-level output voltage V OH Q: Measurement cct 1, I OH = 2mA 2.2––V LOW-level output voltage V OL Q: Measurement cct 1, I OL = 2mA ––0.4V HIGH-level input voltage V IH INH 2.0––V LOW-level input voltage V IL INH––0.3V Output leakage currentI ZQ: Measurement cct 2, INH = LOW, V OH = V DD ––10µAQ: Measurement cct 2, INH = LOW, V OL = V SS––10Current consumptionI DDINH = open, Measurement cct 3, load cct 2, C L = 15pF ,16MHz crystal oscillatorSM5009AH1S CF5009AH1– 4.510mASM5009AH2S CF5009AH2–37SM5009AH3S CF5009AH3SM5009AH4S CF5009AH4–1.53.5INH pull-up resistance R UP Measurement cct 4, V DD = 3V, INH = V SS 40–200k ΩNegative resistance −R L V DD = 3V, Ta = 25°C, 16MHz ––450–ΩFeedback resistance R f Measurement cct 50.4– 1.1M ΩBuilt-in capacitanceC G Design value. A monitor pattern on a wafer is tested.5.5866.42pF C D9.31010.7pFParameter Symbol ConditionRatingUnit min typ max HIGH-level output voltage V OH Q: Measurement cct 1, I OH = 4mA 4.0––V LOW-level output voltage V OL Q: Measurement cct 1, I OL = 4mA ––0.4V HIGH-level input voltage V IH INH 2.0––V LOW-level input voltage V IL INH––0.8V Output leakage currentI ZQ: Measurement cct 2, INH = LOW, V OH = V DD ––10µAQ: Measurement cct 2, INH = LOW, V OL = V SS––10Current consumptionI DDINH = open, Measurement cct 3, load cct 2, C L = 15pF ,30MHz crystal oscillatorSM5009AH1S CF5009AH1–920mASM5009AH2S CF5009AH2–613SM5009AH3S CF5009AH3SM5009AH4S CF5009AH4–49INH pull-up resistance R UP Measurement cct 4, V DD = 5V, INH = V SS 40–200k ΩNegative resistance −R L V DD = 5V, Ta = 25°C, 30MHz ––340–ΩFeedback resistance R f Measurement cct 50.4– 1.1M ΩBuilt-in capacitanceC G Design value. A monitor pattern on a wafer is tested.5.5866.42pF C D9.31010.7pFSwitching Characteristics5009AL × series3V operation: V DD = 2.7 to 3.3V , V SS = 0V , Ta = −40 to 85°C unless otherwise noted.ParameterSymbolConditionRatingUnitmin typ max Output rise timet r1Measurement cct 3, load cct 2, 0.1V DD to 0.9V DD , C L = 15pF– 3.59ns Measurement cct 3, load cct 2, 0.1V DD to 0.9V DD ,V DD = 2.3 to 2.7V, Ta = –20 to +80°C, C L = 15pF–413t r2Measurement cct 3, load cct 2, 0.1V DD to 0.9V DD , C L = 30pF–512Measurement cct 3, load cct 2, 0.1V DD to 0.9V DD ,V DD = 2.4 to 2.7V, Ta = –20 to +80°C, C L = 30pF – 5.516t r3Measurement cct 3, load cct 2, 0.1V DD to 0.9V DD , V DD = 3.0 to 3.6V, f ≤ 30MHz, C L = 50pF –512Measurement cct 3, load cct 2, 0.2V DD to 0.8V DD , V DD = 3.0 to 3.6V, f ≤ 40MHz, C L = 50pF– 3.512Output fall timet f1Measurement cct 3, load cct 2, 0.9V DD to 0.1V DD , C L = 15pF– 3.59ns Measurement cct 3, load cct 2, 0.9V DD to 0.1V DD ,V DD = 2.3 to 2.7V, Ta = –20 to +80°C, C L = 15pF–413t f2Measurement cct 3, load cct 2, 0.9V DD to 0.1V DD , C L = 30pF–512Measurement cct 3, load cct 2, 0.9V DD to 0.1V DD ,V DD = 2.4 to 2.7V, Ta = –20 to +80°C, C L = 30pF – 5.516t f3Measurement cct 3, load cct 2, 0.9V DD to 0.1V DD , V DD = 3.0 to 3.6V, f ≤ 30MHz, C L = 50pF –512Measurement cct 3, load cct 2, 0.8V DD to 0.2V DD , V DD = 3.0 to 3.6V, f ≤ 40MHz, C L = 50pF– 3.512Output duty cycle 11. The duty cycle characteristic is checked the sample chips of each production lot.Duty1Measurement cct 3, load cct 2, V DD = 3V, f ≤ 40MHz, Ta = 25°C, C L = 30pF45–55%Measurement cct 3, load cct 2, V DD = 2.4V, f ≤ 14.4MHz, Ta = 25°C, C L = 30pF40–60CF5009AL × only, Measurement cct 3, load cct 2, V DD = 2.5V, f ≤ 30MHz, Ta = 25°C, C L = 15pF40–60Duty2CF5009AL × only, Measurement cct 3, load cct 2, V DD = 3.3V, f ≤ 30MHz, Ta = 25°C, C L = 50pF45–55CF5009AL × only, Measurement cct 3, load cct 2, V DD = 3.3V, f ≤ 40MHz, Ta = 25°C, C L = 50pF40–60Output disable delay time 22. Oscillator stop function is built-in. When INH goes LOW, normal output stops. When INH goes HIGH, normal output is not resumed until after the oscillator start-up time has elapsed.t PLZ Measurement cct 6, load cct 2, V DD = 3V, Ta = 25°C, C L ≤ 15pF––100ns Output enable delay time 2t PZL––100ns Maximum operating frequencyf maxMeasurement cct 3CF5009AL ×40––MHz SM5009AL ×S 30––Measurement cct 3, Ta = –20 to +80°CSM5009AL ×S 40––Measurement cct 3, Ta = –20 to +80°CV DD = 2.4 to 2.7V, SM5009AL ×S14.4––V DD = 2.3 to 2.7V, CF5009AL ×30––V DD = 2.25 to 2.75V, CF5009AL ×20––5V operation: V DD = 4.5 to 5.5V , V SS = 0V , Ta = −40 to 85°C unless otherwise noted.ParameterSymbol ConditionRatingUnitmin typ max Output rise timet r1Measurement cct 3, load cct 2,0.1V DD to 0.9V DDC L = 15pF –24ns t r2C L = 30pF – 3.57t r3C L = 50pF –48Output fall timet f1Measurement cct 3, load cct 2,0.9V DD to 0.1V DDC L = 15pF –24ns t f2C L = 30pF – 3.57t f3C L = 50pF–48Output duty cycle 11. The duty cycle characteristic is checked the sample chips of each production lot.Duty Measurement cct 3, load cct 2, V DD = 5V, Ta = 25°C, C L = 50pF 45–55%Output disable delay time 22. Oscillator stop function is built-in. When INH goes LOW, normal output stops. When INH goes HIGH, normal output is not resumed until after the oscillator start-up time has elapsed.t PLZ Measurement cct 6, load cct 2, V DD = 5V, Ta = 25°C, C L ≤ 15pF––100ns Output enable delay time 2t PZL––100ns Maximum operating frequencyf maxMeasurement cct 3CF5009AL ×40––MHz SM5009AL ×S 30––Measurement cct 3, Ta = –20 to +80°CSM5009AL ×S40––5009AN ×/CN × series3V operation: V DD = 2.7 to 3.3V , V SS = 0V , Ta = −20 to 80°C unless otherwise noted.ParameterSymbolConditionRatingUnitmin typ max Output rise time t r1Measurement cct 3, load cct 2,0.1V DD to 0.9V DD ,C L = 15pFSM5009AN1S, CF5009AN1SM5009AN2S, CF5009AN2–3.59nsSM5009AN3S, CF5009AN3SM5009AN4S, CF5009AN4SM5009AN5S, CF5009AN5SM5009AN6S, CF5009AN6SM5009CN1S, CF5009CN1SM5009CN2S, CF5009CN2–513t r2Measurement cct 3, load cct 2,0.1V DD to 0.9V DD ,C L = 30pFSM5009AN1S, CF5009AN1SM5009AN2S, CF5009AN2–512SM5009AN3S, CF5009AN3SM5009AN4S, CF5009AN4SM5009AN5S, CF5009AN5SM5009AN6S, CF5009AN6SM5009CN1S, CF5009CN1SM5009CN2S, CF5009CN2–716Output fall time t f1Measurement cct 3, load cct 2,0.9V DD to 0.1V DD ,C L = 15pFSM5009AN1S, CF5009AN1SM5009AN2S, CF5009AN2– 3.59nsSM5009AN3S, CF5009AN3SM5009AN4S, CF5009AN4SM5009AN5S, CF5009AN5SM5009AN6S, CF5009AN6SM5009CN1S, CF5009CN1SM5009CN2S, CF5009CN2–513t f2Measurement cct 3, load cct 2,0.9V DD to 0.1V DD ,C L = 30pFSM5009AN1S, CF5009AN1SM5009AN2S, CF5009AN2–512SM5009AN3S, CF5009AN3SM5009AN4S, CF5009AN4SM5009AN5S, CF5009AN5SM5009AN6S, CF5009AN6SM5009CN1S, CF5009CN1SM5009CN2S, CF5009CN2–716Output duty cycle 11. The duty cycle characteristic is checked the sample chips of each production lot.DutyMeasurement cct 3, load cct 2,V DD = 3V, Ta = 25°CC L = 30 pF ,SM5009AN ×S, CF5009AN ×45–55%C L = 15 pF ,SM5009CN ×S, CF5009CN ×40–60Output disable delay time t PLZ Measurement cct 6, load cct 2, V DD = 3V, Ta = 25°C, C L ≤ 15pF––100ns Output enable delay time t PZL ––100nsMaximum operating frequencyf maxMeasurement cct 3SM5009AN ×S, CF5009AN ×40––MHz Ta = –10 to +70°C,SM5009CN ×S, CF5009CN ×30––5V operation: V DD = 4.5 to 5.5V , V SS = 0V , Ta = −40 to 85°C unless otherwise noted.5009AK × seriesV DD = 4.5 to 5.5V , V SS = 0V , Ta = −40 to 85°C unless otherwise noted.ParameterSymbol ConditionRatingUnitmin typ max Output rise timet r1Measurement cct 3, load cct 2,0.1V DD to 0.9V DDC L = 15pF –24ns t r2C L = 30pF – 3.57t r3C L = 50pF –48Output fall timet f1Measurement cct 3, load cct 2,0.9V DD to 0.1V DDC L = 15pF –24ns t f2C L = 30pF – 3.57t f3C L = 50pF–48Output duty cycle 11. The duty cycle characteristic is checked the sample chips of each production lot.Duty Measurement cct 3, load cct 2, V DD = 5V, Ta = 25°C, C L = 50pF 45–55%Output disable delay time t PLZ Measurement cct 6, load cct 2, V DD = 5V, Ta = 25°C, C L ≤ 15pF––100ns Output enable delay time t PZL ––100ns Maximum operating frequencyf maxMeasurement cct 3SM5009AN ×S, CF5009AN ×40––MHz SM5009CN ×S, CF5009CN ×30––Parameter Symbol ConditionRatingUnit min typ max Output rise time t r Measurement cct 3, load cct 1, 0.4V to 2.4V, C L = 15pF –26ns Output fall time t f Measurement cct 3, load cct 1, 2.4V to 0.4V, C L = 15pF –26ns Output duty cycle 11. The duty cycle characteristic is checked the sample chips of each production lot.Duty Measurement cct 3, load cct 1, V DD = 5V, Ta = 25°C, C L = 15pF 45–55%Output disable delay time t PLZ Measurement cct 6, load cct 1, V DD = 5V, Ta = 25°C, C L ≤ 15pF––100ns Output enable delay time t PZL ––100ns Maximum operating frequencyf maxMeasurement cct 3Ta = –20 to +80°C 40––MHzTa = –40 to +85°C30––5009AH × series3V operation: V DD = 2.7 to 3.3V , V SS = 0V , Ta = −20 to 80°C unless otherwise noted.5V operation: V DD = 4.5 to 5.5V , V SS = 0V , Ta = −40 to 85°C unless otherwise noted.Parameter Symbol ConditionRatingUnit min typ max Output rise time t r1Measurement cct 3, load cct 2, 0.1V DD to 0.9V DD , C L = 15pF –618ns Output fall time t f1Measurement cct 3, load cct 2, 0.9V DD to 0.1V DD , C L = 15pF –618ns Output duty cycle 11. The duty cycle characteristic is checked the sample chips of each production lot.Duty Measurement cct 3, load cct 2, V DD = 3V, Ta = 25°C, C L = 15pF 45–55%Output disable delay time t PLZ Measurement cct 6, load cct 2, V DD = 3V, Ta = 25°C, C L ≤ 15pF ––100ns Output enable delay time t PZL ––100ns Maximum operating frequencyf maxMeasurement cct 316––MHzParameter Symbol ConditionRatingUnit min typ max Output rise time t r1Measurement cct 3, load cct 2, 0.1V DD to 0.9V DD , C L = 15pF –412ns Output fall time t f1Measurement cct 3, load cct 2, 0.9V DD to 0.1V DD , C L = 15pF –412ns Output duty cycle 11. The duty cycle characteristic is checked the sample chips of each production lot.Duty Measurement cct 3, load cct 2, V DD = 5V, Ta = 25°C, C L = 15pF 45–55%Output disable delay time t PLZ Measurement cct 6, load cct 2, V DD = 5V, Ta = 25°C, C L ≤ 15pF ––100ns Output enable delay time t PZL ––100ns Maximum operating frequencyf maxMeasurement cct 330––MHzMEASUREMENT CIRCUITSMeasurement cct 1• 5009AK ×, AL ×, AN1, AN2R1: 50ΩR2: 250Ω(V DD = 4.5V), 275Ω(V DD = 2.7V)R3: 256Ω(V DD = 4.5V), 288Ω(V DD = 2.7V)• 5009AN3 to AN6, CN ×R1: 50ΩR2: 245Ω(V DD = 4.5V), 262Ω(V DD = 2.7V)R3: 256Ω(V DD = 4.5V), 288Ω(V DD = 2.7V)• 5009AH ×R1: 50ΩR2: 1000Ω(V DD = 4.5V), 1100Ω(V DD = 2.7V)R3: 1025Ω(V DD = 4.5V), 1150Ω(V DD = 2.7V)Measurement cct 2DD 0V XT input waveform(10MHz)V OH 0V Q outputV DD V DD V OL Q output0VMeasurement cct 4Measurement cct 5Measurement cct 6R1: 50ΩPRV DD I PR(V IL = 0V)R UP2 =I PRV IH : 2.1V(V DD = 3.0V)V IH : 3.5V(V DD = 5.0V)V DD V IHR UP R UP1=R f =V DD I RfLoad cct 1Load cct 2Switching Time Measurement WaveformOutput duty level (CMOS)Output duty level (TTL)Output duty cycle (CMOS)Output duty cycle (TTL)C L = 15pF: DUTY, I DD , t r , t f R = 400ΩC L = 15pF: DUTY, I DD , t r1, tf1C L = 30pF: t r2, t f2C L = 50pF: t r3, t f3Output Enable/Disable DelayNote (AL × series only):when the device is in standby, the oscillator stops. When standby is released, the oscil-lator starts and stable oscillator output occurs after a short delay.Q outputINH input waveform t r = t f 10nsNC9801GE2003.07。

HT7050A中文资料

HT70XXVoltage DetectorSelection TablePart No.Detectable VoltageHysteresis WidthTolerance HT7022A 2.2V 0.11V ±5%HT7024A 2.4V 0.12V ±5%HT7027A 2.7V 0.135V ±5%HT7033A 3.3V 0.165V ±5%HT7039A 3.9V 0.195V ±5%HT7044A 4.4V 0.22V ±5%HT7050A 5.0V 0.25V ±5%HT7070A 7.0V0.35V±5%Note:The output type selection codes are:NMOS open drain normal open,active lowFor example:The HT7070A is a 7.0V,NMOS open drain active low outputOutput type selection tableV DDV DD >V DET (+)V DD £V DET (-)TypeV OUT AHi-ZVSSRev.1.601January 14,2003General DescriptionThe HT70XX series is a set of three-terminal low power voltage detectors implemented in CMOS technology.Each voltage detector in the series detects a particular fixed voltage ranging from 2.2V to 7V.The voltage de-tectors consist of a high-precision and low power con-sumption standard voltage source,a comparator,hysteresis circuit,and an output driver.CMOS technol-ogy ensures low power consumption.Although designed primarily as fixed voltage detectors,these devices can be used with external components to detect user specified threshold voltages (NMOS open drain type only).Features·Low power consumption ·Low temperature coefficient·Built-in high-stability reference source·Built-in hysteresis characteristic ·TO-92&SOT-89packageApplications·Battery checkers ·Level selectors ·Power failure detectors·Microcomputer reset ·Battery memory backup·Non-volatile RAM signal storage protectorsBlock DiagramN channel open drain output(normal open;active low)A typePin AssignmentRev.1.602January14,2003Pad AssignmentHT70XX (except HT7022A)Chip size:1317´1158(m m)2*The IC substrate should be connected to VDD in the PCB layout artwork.HT7022A onlyChip size:2032´1321(m m)2*The IC substrate should be connected to VDD in the PCB layout artwork.Absolute Maximum RatingsSupply Voltage,except HT7022A..................................................................................................V SS -0.3V to V SS +26V Supply Voltage,HT7022A only....................................................................................................................-0.3V to13V Output Voltage...........................V SS -0.3V to V DD +0.3V Output Current......................................................50mA Storage Temperature............................-50°C to 125°C Power Consumption..........................................200mWOperating Temperature 0°C to 70°CNote:These are stress ratings only.Stresses exceeding the range specified under ²Absolute Maximum Ratings ²maycause substantial damage to the device.Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-ity.Rev.1.603January 14,2003Pad CoordinatesHT70XX (except HT7022A)Unit:m m Pad No.X Y 1-483.30-379.502-234.60-399.503443.90-386.00HT7022A onlyUnit:m mPad No.X Y1-434.34394.972120.65461.013774.70412.75Electrical CharacteristicsHT7022A Ta=25°CHT7024A Ta=25°CHT7027A Ta=25°CRev.1.604January14,2003HT7039A Ta=25°CHT7044A Ta=25°CRev.1.605January14,2003HT7070A Ta=25°CRev.1.606January 14,2003Functional DescriptionThe HT70XX series is a set of voltage detectors equipped with a high stability voltage reference which is connected to the negative input of a comparator ¾de-noted as V REF in the following figure for NMOS output voltage detector.When the voltage drop to the positive input of the com-parator (i,e,V B )is higher than V REF ,VOUT goes high,M1turns off,and V B is expressed as V BH =V DD ´(R B +R C )/(R A +R B +R C ).If V DD is decreased so that V B falls to a value less than V REF ,the comparator output in-verts from high to low,V OUT goes low,V C is high,M1turns on,RC is bypassed,and V B becomes:V BL =V DD ´R B /(R A +R B ),which is less than V BH.By so doing,the comparator output will stay low to prevent the circuit from oscillating when V B »V REF.If V DD falls below the minimum operating voltage,the output becomes undefined.When VDD goes from low to V DD ´R B /(R A +R B )>V REF ,the comparator output and V OUT goes high.The detectable voltage is defined as:V DET (-)=R R R R R A B CB C +++´V REFThe release voltage is defined as:V DET (+)=R R R A BB+´V REFThe hysteresis width is:V HYS=V DET(+)-V DET(-)The figure demonstrates the NMOS output type withpositive output polarity(V OUT is normally open,activelow).The HT70XX series also supplies options for otheroutput types with active high outputs.Application cir-cuits shown are examples of positive output polarity(normally open,active low)unless otherwise specified.NMOS output voltage detector(HT70XXA) Application CircuitsMicrocomputer reset circuitNormally a reset circuit is required to protect the micro-computer system from malfunctions due to power line interruptions.The following examples show how differ-ent output configurations perform a reset function in var-ious systems.·NMOS open drain output application for separate power supply·NMOS open drain output application with R-C delayPower-on reset circuitWith several external components,the NMOS open drain type of the HT70XX series can be used to perform a power-on reset function as shown:Rev.1.607January14,20035V power line monitoring circuitGenerally,a minimum operating voltage of4.5V is guar-anteed in a5V power line system.The HT7044A is rec-ommended for use as5V power line monitoring circuit.·5V power line monitor with power-on reset·with5V voltage regulatorChange of detectable voltageIf the required voltage is not found in the standard prod-uct selection table,it is possible to change it by using ex-ternal resistance dividers or diodes.·Varying the detectable voltage with a resistance di-viderDetectable voltage=R RRA BB+´V DETHysteresis width=R RRA BB+´V HYS·Varying the detectable voltage with a diodeDetectable Voltage=V f1+V f2+V DETMalfunction analysisThe following circuit demonstrates the way a circuit ana-lyzes malfunctions by monitoring the variation or spikenoise of power supply voltage.Charge monitoring circuitThe following circuit shows a charged monitor for pro-tection against battery deterioration by overcharging.When the voltage of the battery is higher than the set de-tectable voltage,the transistor turns on to bypass thecharge current,protecting the battery from overcharg-ing.Rev.1.608January14,2003Level selectorThe following diagram illustrates a logic level selector.Rev.1.609January14,2003Package Information3-pin TO-92outline dimensionsSymbolDimensions in milMin.Nom.Max.A170¾200B170¾200C500¾¾D11¾20E90¾110F45¾55G45¾65H130¾160I8¾18a4°¾6°Rev.1.6010January14,20033-pin SOT-89outline dimensionsSymbolDimensions in milMin.Nom.Max.A173¾181B64¾72C90¾102D35¾47E155¾167F14¾19G17¾22H¾59¾I55¾63J14¾17Rev.1.6011January14,2003Product Tape and Reel SpecificationsTO-92reel dimensions(Unit:mm)Rev.1.6012January14,2003SOT-89reel dimensionsSOT-89Symbol Description Dimensions in mmA Reel Outer Diameter180±1.0B Reel Inner Diameter62±1.5C Spindle Hole Diameter12.75+0.15D Key Slit Width 1.9±0.15T1Space Between Flange12.4+0.2T2Reel Thickness17-0.4Rev.1.6013January14,2003TO-92Symbol Description Dimensions in mm I1Taped Lead Length(2.5)P Component Pitch12.7±1.0P0Perforation Pitch12.7±0.3P2Component to Perforation(Length Direction) 6.35±0.4F1Lead Spread 2.5+0.4-0.1F2Lead Spread 2.5+0.4-0.1D h Component Alignment0±0.1W Carrier Tape Width 18.0+1.0-0.5W0Hold-down Tape Width 6.0±0.5W1Perforation Position9.0±0.5W2Hold-down Tape Position(0.5)H0Lead Clinch Height16.0±0.5H1Component Height Less than24.7D0Perforation Diameter 4.0±0.2t Taped Lead Thickness0.7±0.2H Component Base Height19.0±0.5Note:Thickness less than0.38±0.05mm~0.5mmP0Accumulated pitch tolerance:±1mm/20pitches.()Bracketed figures are for consultation onlyRev.1.6014January14,2003SOT-89Symbol Description Dimensions in mmW Carrier Tape Width 12.0+0.3-0.1P Cavity Pitch8.0±0.1E Perforation Position 1.75±0.1F Cavity to Perforation(Width Direction) 5.5±0.05D Perforation Diameter 1.5+0.1D1Cavity Hole Diameter 1.5+0.1P0Perforation Pitch 4.0±0.1P1Cavity to Perforation(Length Direction) 2.0±0.10A0Cavity Length 4.8±0.1B0Cavity Width 4.5±0.1K0Cavity Depth 1.8±0.1t Carrier Tape Thickness0.30±0.013C Cover Tape Width9.3Rev.1.6015January14,2003Holtek Semiconductor Inc.(Headquarters)No.3,Creation Rd.II,Science-based Industrial Park,Hsinchu,TaiwanTel:886-3-563-1999Fax:886-3-563-1189Holtek Semiconductor Inc.(Sales Office)11F,No.576,Sec.7Chung Hsiao E.Rd.,Taipei,TaiwanTel:886-2-2782-9635Fax:886-2-2782-9636Fax:886-2-2782-7128(International sales hotline)Holtek Semiconductor(Shanghai)Inc.7th Floor,Building2,No.889,Yi Shan Rd.,Shanghai,ChinaTel:021-6485-5560Fax:021-6485-0313Holtek Semiconductor(Hong Kong)Ltd.RM.711,Tower2,Cheung Sha Wan Plaza,833Cheung Sha Wan Rd.,Kowloon,Hong KongTel:852-2-745-8288Fax:852-2-742-8657Holmate Semiconductor,Inc.48531Warm Springs Boulevard,Suite413,Fremont,CA94539Tel:510-252-9880Fax:510-252-9885CopyrightÓ2003by HOLTEK SEMICONDUCTOR INC.The information appearing in this Data Sheet is believed to be accurate at the time of publication.However,Holtek as-sumes no responsibility arising from the use of the specifications described.The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification,nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise.Holtek reserves the right to alter its products without prior notification.For the most up-to-date information,please visit our web site at .Rev.1.6016January14,2003。

ICS557G-03中文资料

ICS557-03 PCI-E XPRESS C LOCK S OURCEDescriptionThe ICS557-03 is a spread spectrum clock generator supporting PCI-Express and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce electromagnetic interference (EMI). The device provides two differential (HCSL) spread spectrum outputs. This device is pin configured to select spread and clock selection. Using ICS’ patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces two pairs of differential outputs (HCSL) at 25 MHz, 100 MHz, 125 MHz and 200 MHz clock frequencies. It also provides spread selection of ±0.25%, -0.5%, -0.75%, and no spread. Features•Packaged in 16-pin TSSOP•Available in Pb (lead) free package•Supports LVDS Output Levels•Operating voltage of 3.3 V•Input frequency of 25 MHz•Outputs (HCSL, 0.7 V Current mode differential pair)•Jitter 100 ps (peak-to-peak)•Spread of ±0.25%, -0.5%, -0.75%, and no spread.•Industrial and commercial temperature rangesBlock DiagramPin AssignmentOutput Select Table 1(MHz)Spread Selection Table 2Pin DescriptionsS1S0CLK(1:0), CLK(1:0)0025M 01100M 10125M 11200MSS1SS0Spread %00Center ±0.2501Down-0.510Down -0.7511NoSpreadPin NumberPin NamePin TypePin Description1S0Input Select pin 0. See Table1. Internal pull-up resistor.2S1Input Select pin 1. See Table 1. Internal pull-up resistor.3SS0Input Spread Select pin 0. See Table 2. Internal pull-up resistor.4X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.5X2Output Crystal connection. Leave unconnected for clock input.6OE Input Output enable tri-states outputs and device is not shut down. Internal pull-up resistor.7GNDXD Power Connect to ground.8SS1InputSpread Select pin 1. See Table 2. Internal pull-up resistor.9IREF Output Precision resistor attached to this pin is connected to the internal currentreference.10CLK1Output HCSL compliment clock output.11CLK1Output HCSL clock output.12VDDODA Power Connect to voltage supply +3.3 V for output driver and analog circuits 13GNDODA PowerConnect to ground.14CLK0Output HCSL compliment clock output.15CLK0Output HCSL clock output.16VDDXDPowerConnect to voltage supply +3.3 V for crystal oscillator and digital circuit.Applications Information External ComponentsA minimum number of external components are required for proper operation.Decoupling CapacitorsDecoupling capacitors of 0.01 µF should be connected between each VDD pin and the ground plane, as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin. CrystalA 25 MHz fundamental mode parallel resonant crystal should be used. This crystal must have less than 300 ppm of error across temperature in order for theICS557-03 to meet PCI Express specifications.Crystal CapacitorsCrystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency.C L= Crystal’s load capacitance in pFCrystal Capacitors (pF) = (C L- 8) * 2For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16. Current Source (Iref) Reference Resistor - R R If board target trace impedance (Z) is 50Ω, then R R = 475Ω (1%), providing IREF of 2.32 mA. The output current (I OH) is equal to 6*IREF.Output TerminationThe PCI-Express differential clock outputs of theICS557-03 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section.The ICS557-03 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section.General PCB Layout RecommendationsFor optimum device performance and lowest output phase noise, the following guidelines should be observed.1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible.2. No vias should be used between decoupling capacitor and VDD pin.3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical.4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-03.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.PCI-Express Layout GuidelinesPCI-Express Device RoutingTypical PCI-Express (HCSL) WaveformLVDS Compatible Layout GuidelinesLVDS Device RoutingTypical LVDS WaveformAbsolute Maximum RatingsStresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above thoseindicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.DC Electrical CharacteristicsUnless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85°C1 Single edge is monotonic when transitioning through region.2 Inputs with pull-ups/-downs are not included.ItemRatingSupply Voltage, VDD, VDDA 5.5 VAll Inputs and Outputs-0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial)0 to +70°C Ambient Operating Temperature (industrial)-40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°CESD Protection (Input)2000 V min. (HBM)ParameterSymbol ConditionsMin.Typ.Max.UnitsSupply Voltage V 2.97 3.33.63Input High Voltage 1V IH S0, S1, OE, CLK, SS0, SS1 2.0VDD +0.3V Input Low Voltage 1V IL S0, S1, OE, CLK, SS0, SS1VSS-0.30.8V Input Leakage Current 2I IL 0 < Vin < VDD -55µA Operating Supply Current I DD 50Ω, 2pF 65mA I DDOE OE =Low35mA Input Capacitance C IN Input pin capacitance 7pF Output Capacitance C OUT Output pin capacitance6pF Pin Inductance L PIN 5nH Output Resistance R OUT CLKOUT3.0k ΩPull-up ResistorR PU100k ΩUnless stated otherwise, VDD=3.3 V ±10%, Ambient Temperature -40 to +85°CNote 1: Test setup is R L =50 ohms with 2 pF , Rr = 475Ω (1%).Note 2: Measurement taken from a single-ended waveform.Note 3: Measurement taken from a differential waveform.Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.Parameter SymbolConditionsMin.Typ.Max.Units Input Frequency 25MHz Output Frequency 25200MHz Output High Voltage 1,2V OH Notes 1, 2660700850mV Output Low Voltage 1,2V OLNotes 1, 2-1500mV Crossing Point Voltage 1,2Absolute, Notes 1, 2250350550mV Crossing Point Voltage 1,2,4Variation over all edges, Notes 1, 2, 4140mV Jitter, Cycle-to-Cycle 1,3Notes 1, 360ps Modulation Frequency Spread spectrum3031.533kHz Rise Time 1,2t OR From 0.175 V to 0.525 V , Notes 1, 2175332700ps Fall Time 1,2t OF From 0.525 V to 0.175 V , Notes 1, 2175344700ps Rise/Fall Time Variation 1,2Notes 1, 2125ps Skew between outputs At VDD/2 50ps Duty Cycle 1,3Notes 1, 34555%Output Enable Time 5All outputs, Note 510us Output Disable Time 5All outputs, Note 510us Stabilization Time t STABLE From power-up VDD=3.3 V3.0ms Spread Change Timet SPREAD Settling period after spread change3.0msThermal CharacteristicsMarking Diagram (ICS557G-03)Marking Diagram (ICS557G-03LF)Marking Diagram (ICS557GI-03)Marking Diagram (ICS557GI-03LF)Notes:1. ###### is the lot code.2. YYWW is the last two digits of the year, and the week number that the part was assembled.3. “LF” designates Pb (lead) free package.4. “I” deisgnates industrial temperature range.5. Bottom marking: (origin). Origin = country of origin of not USA.ParameterSymbolConditionsMin.Typ.Max.UnitsThermal Resistance Junction to AmbientθJA Still air 78°C/WθJA 1 m/s air flow 70°C/W θJA 3 m/s air flow68°C/W Thermal Resistance Junction to CaseθJC37°C/WPackage Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)Package dimensions are kept current with JEDEC Publication No. 95Ordering InformationParts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.Part / Order NumberMarkingShipping PackagingPackageTemperatureICS557G-03See Page 8Tubes 16-pin TSSOP 0 to +70° C ICS557G-03T T ape and Reel16-pin TSSOP 0 to +70° C ICS557G-03LF Tubes 16-pin TSSOP 0 to +70° C ICS557G-03LFT T ape and Reel16-pin TSSOP 0 to +70° C ICS557GI-03See Page 8Tubes 16-pin TSSOP -40 to +85° C ICS557GI-03T T ape and Reel16-pin TSSOP -40 to +85° C ICS557GI-03LF Tubes 16-pin TSSOP -40 to +85° C ICS557GI-03LFTT ape and Reel16-pin TSSOP-40 to +85° C。

压控晶振选型指南大全

YXC丨压控晶振选型指南➢概要压控晶振（VCXO），全称为电压控制石英晶体振荡器（Voltage Controlled Oscillator）,是石英晶体振荡器的一种。

压控晶振主要由石英晶体谐振器、变容二极管和振荡电路组成，其工作原理是通过控制电压来改变变容二极管的电容，从而“牵引”石英谐振器的频率，以达到频率调制的目的。

因此，压控晶振最突出的特点之一是能够通过调整输入电压实现小范围内的输出频率调整，一般频率调制范围为±50PPM~±200PPM。

压控晶振大多用于锁相技术、频率负反馈调制的目的，被广泛应用于音频功放、高清电视系统、无线通信系统、卫星导航及通信系统、高精密仪器仪表等应用中的同步/抖动清除。

➢YXC丨VCXO产品家族➢参数及选型指南压控晶振（VCXO）主要参数包括中心频率、频率稳定度、牵引范围、工作电压、输出方式、工作温度和封装尺寸等，在选购YXC压控晶振时建议按照以下方法进行筛选：（1）选择您所需要的中心频率/频点中心频率是晶振最关键的参数之一，表示晶振在单位时间内完成振动的次数。

晶振的中心频率实际上指的就是晶振的标称频率，即我们所说的频点。

常用的单位包括Hz（赫兹，1Hz表示每秒振荡1次）、kHz（千赫兹，1kHz=1000Hz）、MHz（兆赫兹，1MHz=1000kHz）、GHz(吉赫兹，1GHz=1000MHz)。

目前YXC的VCXO支持10MHz~2100MHz频率范围内的任意频点，且可精确至小数点后6位。

（2）选择您所需要的精度/频率稳定度频率稳定度是晶振的另一项关键参数，表示实际输出频率与标称频率之间的误差，通常用ppm（百万分之一）表示。

压控晶振通过调节电压来改变输出频率会一定程度上牺牲晶振的频率稳定度，因此建议在满足设计要求的前提下尽量选择频率稳定度较小的产品。

YXC的VCXO产品提供±25ppm、±50ppm、±100ppm等不同的频率稳定度（总偏差）选项。

Cadence元件设计及命名规范

武汉中元华电科技股份有限公司
备注例如： c0805；r0603；l1206；d1206；
例如： c7343‐31 7.3*4.3*3.1mm 或 cta、ctb…… 例如： ce43x43x52 4.3*4.3*5.2mm 例如： ck120x120x78 12*12*7.8mm ck132x99x64 13.2*9.9*6.4mm 例如： 8p4r_0603 8pin 包含 4 个电阻，单个封装为 0603 10p8r_0402 10pin 包含 8 个电阻，单个封装为 0402 例如： xtl2_49smd 49smd 无源晶体 osc4_7050 7*5mm 有源晶振
例如：
bga780‐100_28X28 28*28 行，间距 1mm，780 个焊点 BGA 封装
3.3、连接器元件（存放于 CONNECTOR 文件夹）
1
header 类连接器命名：
hs(X)x(Y)_(pitch) _[shield]_[direction]_[n?]_[补充]
hd(X)x(Y)_(pitch)_[shield]_[direction]_[n?]_[补充]
ssop
EP：exposed thermal pad
(pitch 一般 0.5 或 0.65mm，height 一
*TSOP 的引脚在芯片的短边，而 TSOP II 的引脚在芯片的般 1.55mm)
长边
tssop86_050_1016
(pitch 一般 0.5 或 0.65mm，height 一
般 1.00mm)
ck(长 x 宽 x 高)或(_器件厂家命名)
5
SMD 排阻命名方式：
(类型)_(封装大小)
6
SMD 频率元件命名方式：

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