华为EMC设计指导书(一)
EMC设计详细讲解教程
从企业产品需要进行设计、整改认证的过程看，EMC工程师必须具备以下八大技能：1、EMC的基本测试项目以及测试过程掌握；2、产品对应EMC的标准掌握；3、产品的EMC整改定位思路掌握；4、产品的各种认证流程掌握；5、产品的硬件硬件知识，对电路（主控、接口）了解；6、EMC设计整改元器件（电容、磁珠、滤波器、电感、瞬态抑制器件等）使用掌握；7、产品结构屏蔽设计技能掌握；8、对EMC设计如何介入产品各个研发阶段流程掌握。
二、EMC常用元件介绍共模电感共模电感是一个以铁氧体为磁芯的共模干扰抑制器件，它由两个尺寸相同，匝数相同的线圈对称地绕制在同一个铁氧体环形磁芯上，形成一个四端器件，要对于共模信号呈现出大电感具有抑制作用，而对于差模信号呈现出很小的漏电感几乎不起作用。
原理是流过共模电流时磁环中的磁通相互叠加，从而具有相当大的电感量，对共模电流起到抑制作用，而当两线圈流过差模电流时，磁环中的磁通相互抵消，几乎没有电感量，所以差模电流可以无衰减地通过。
因此共模电感在平衡线路中能有效地抑制共模干扰信号，而对线路正常传输的差模信号无影响。
共模电感在制作时应满足以下要求：1）绕制在线圈磁芯上的导线要相互绝缘，以保证在瞬时过电压作用下线圈的匝间不发生击穿短路。
2）当线圈流过瞬时大电流时，磁芯不要出现饱和。
3）线圈中的磁芯应与线圈绝缘，以防止在瞬时过电压作用下两者之间发生击穿。
4）线圈应尽可能绕制单层，这样做可减小线圈的寄生电容，增强线圈对瞬时过电压的而授能力。
通常情况下，同时注意选择所需滤波的频段，共模阻抗越大越好，因此我们在选择共模电感时需要看器件资料，主要根据阻抗频率曲线选择。
另外选择时注意考虑差模阻抗对信号的影响，主要关注差模阻抗，特别注意高速端口。
磁珠铁氧体材料是铁镁合金或铁镍合金，这种材料具有很高的导磁率，他可以是电感的线圈绕组之间在高频高阻的情况下产生的电容最小。
铁氧体材料通常在高频情况下应用，因为在低频时他们主要程电感特性，使得线上的损耗很小。
PCB走线之安全间距到底是多少？
PCB走线之安全间距到底是多少？华为《PCB的EMC设计指南》1.3 爬电距离与电气间隙PCB板上的布线应该满足对电气间隙和爬电距离的要求，参见下面的表1和表2。
表1 输入150V-300V电源最小电气间隙及爬电距离Infineon<ICE3A2065ELJ>8 Schematic for recommended PCB layout2.High voltage traces clearance:High voltage traces should keep enough spacing to the nearby traces.Otherwise,arcing would incur.a.400V traces (positive rail of bulk capacitor C11) to nearby trace:＞2.0mmb.600V traces (drain voltage of CoolSET IC11) to nearby trace:＞2.5mm飞瑞集团PHOENIXTEC GROUP《PCB LAYOUT绘制规范》14.2安規安全間距的限制:14.2.1美規系統:UL、CUL、CSA請見下面TABLE----UL1778[PARAGRAPH 23.1.1 / EXCEPTION NO.2～4]14.2.2 歐規系統:TUV請見下面之TABLE-----EN60950[IEC 950，PARAGRAPH 2.9.3]注:本公司所依之規格為Pollution degree 2 Level 之Material group IIIa+IIIb.14.2.4 安規基本通則(1) L-N之間距須保持TUV:2.5mm,UL:1.6mm以上(2) L-GROUND，N-GROUND之間距須保持TUV:2.5mm,UL:1.6mm以上(3) 一次側與二次側之線路之間距須保持5mm以上。
华为EMC设计指导书
前言
本技术规范根据国家标准GJB72-85 和原邮电部标准以及国际标准系列标准 编制而成。
本规范于 月日首次发布。 本规范起草单位： 本规范主要起草人： 本规范批准人： 本规范修改记录：
前言
电磁兼容性(EMC-Electromagnetic Compatibility)，根据国家军用标准GJB72-85《电磁干扰和电磁兼容 性名词术语》第5.10条，定义为：“设备(分系统、系统)在共同的电磁环境中能一起执行各自功能的共存 状态。即：该设备不会由于受到处于同一电磁环境中其他设备的电磁发射导致或遭受不允许的降级；它 也不会使同一电磁环境中其他设备(分系统、系统)，因受其电磁发射而导致或遭受不编辑，指导书定位为PCB的EMC设计参考，谨供硬件工程师进行PCB设计时参 考，可以充分借鉴现有的工作经验，在多种因素中进行折衷考虑，成功地完成原理图的物理实现。
文中的有些观点、建议仅仅是现有工作经验的总结，由于EMC领域的诸多未知因素，加上编者的水 平有限，错误、疏漏之处在所难免，还望大家不断批评、指正。
对于本文的任何不明白之处，以及任何有益建议请与CAD研究部（兼EMC特工组）的 联系 ），共 同探讨PCB的EMC设计过程中的任何实际问题。
编者
目次
1 目的 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 范围 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 定义 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 引用标准和参考资料 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 第一部分 布局 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 层的设置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
华为电磁兼容性结构设计规范_第三版
华为技术有限公司企业技术规范DKBA0.400.0022 REV.3.0 电磁兼容性结构设计规范2003-11-30发布2003-11-30实施华为技术有限公司内部公开前言本规范于1999年12月25日首次发布。
本规范于2001年7月30日第一次修订。
本规范于2003年10月30日第二次修订。
本规范起草单位：华为技术有限公司结构造型设计部本规范授予解释单位：华为技术有限公司结构造型设计部本华为机密，未经许可不得扩散第1页，共1页内部公开目录1 范围 ... ....................................................................................................................................................... ..42 引用标准 ... . (4)3 术语 ... ....................................................................................................................................................... ..44 电磁兼容基本概念... (5)4.1 电磁兼容定义 ... .............................................................................................................................. ..5 4.2 电磁兼容三要素 ... ........................................................................................................................... .54.3 通讯产品电磁兼容一般要求 ... ..................................................................................................... ..65 电磁屏蔽基本理论... (7)5.1 屏蔽效能 ... ....................................................................................................................................... .7 5.2 屏蔽体的缺陷 ... .............................................................................................................................. ..75.2.1缝隙屏蔽 ... (7)5.2.2开孔屏蔽 ... (8)5.2.3电缆穿透 ... . (10)6 屏蔽设计 ... .. (12)6.1 结构屏蔽效能 ... .......................................................................................................................... (12)6.2 屏蔽方案与成本 ... ....................................................................................................................... ..12 6.3 缝隙屏蔽设计 ... .......................................................................................................................... (13)6.3.1紧固点连接缝隙 ... . (13)A. 减小缝隙的最大尺寸 ... ........................................................................................................................... .. 13B. 增加缝隙深度 ... ........................................................................................................................................ .. 14C. 紧固点间距 ... ........................................................................................................................................... (15)6.3.2安装屏蔽材料 ... ....................................................................................................................... ..176.3.3屏蔽材料的选用 ... . (18)A. 常用屏蔽材料................................................................... .. 18B. 常用屏蔽材料性能参数 ... ........................................................................................................................ . 246.4 开孔屏蔽设计 ... .......................................................................................................................... (25)6.4.1通风孔屏蔽 ... .......................................................................................................................... (25)6.4.2局部开孔屏蔽 ... ....................................................................................................................... ..26 6.5 塑胶件屏蔽 ... . (27)6.6 单板局部屏蔽 ... .......................................................................................................................... (28)6.6.1盒体式屏蔽盒 ... ....................................................................................................................... ..28内部公开6.6.2围框式屏蔽盒 ... ....................................................................................................................... ..29 6.7 电缆屏蔽设计 ... .......................................................................................................................... (29)6.7.1屏蔽电缆夹线结构 ... .............................................................................................................. (29)6.7.2屏蔽连接器转接 ... . (33)6.7.3非屏蔽电缆 ... .......................................................................................................................... (34)7 典型结构屏蔽方案... . (35)7.1 2000机柜屏蔽方案 ... . (35)7.2 2000插箱屏蔽方案 ... . (37)7.3 S3026C钣金盒式结构屏蔽方案 ... (42)7.4 R413PAVO塑胶盒式结构屏蔽方案 ... ..................................................................................... (44)7.5 型材面板屏蔽 ... .......................................................................................................................... (47)7.6 钣金面板屏蔽 ... .......................................................................................................................... (49)7.7 扣板面板屏蔽 ... .......................................................................................................................... (52)7.8 防水&屏蔽结构 ... ....................................................................................................................... (54)内部公开电磁兼容性结构设计规范1范围本规范规定了电磁兼容性结构屏蔽设计的主要原理、设计原则和详细设计方法。
EMC磁盘阵列配置指导书
#!/bin/sh for i in ‘cfgadm |grep fc-fabric|awk ’{print $1}’‘;do dev="‘cfgadm -lv $i|grep devices |awk ’{print $NF}’‘" wwn=grep ’Host Bus’|awk’{print $4}’‘" echo "$i: $wwn" done
1.2 组成
电源
EMC CX 3-20 磁盘阵列由电源、控制器、磁盘柜三大模块组成。
电源模块的前视图如图 1-1 所示，有 A0、A1、B0、B1 四个部分。 图1-1 电源模块前视图
控制器
EMC CX 3-20 磁盘阵列有 2 个控制器，控制器后视图如图 1-2 所示。
文档版本 03 (2006-03-01)
屏幕显示信息中第 1 列的 c1、c3、c4 表示 HBA 控制器。 步骤 4 配置 HBA。
文档版本 03 (2006-03-01)
华为技术有限公司
2-1
插图目录
# cfgadm -c configure c1
# cfgadm -c configure c3
# cfgadm -c configure c4 步骤 5 注册 HBA。
SmartAX MA5100 故障处理
目录
目录
1 产品介绍.......................................................................................................................................1-1
以太网电接口EMC设计指导书
以太网电接口EMC设计指导书1000字以太网是一种常用的局域网技术，用于连接网络上的设备，例如计算机、服务器、路由器、交换机等等。
以太网电接口的设计在EMC方面较为重要，下面是一份以太网电接口EMC设计指导书，总长1000字左右。
1. PCB设计在PCB设计方面，需要关注的主要是地线的分布和走线。
在走线上，要避免在信号线和电源线或地线上交错走线，应采用分层走线或穿孔解决。
此外，尽量缩短信号线与地线或电源线之间的距离，使其形成一个尽可能小的环路。
2. PCB布局以太网电接口在PCB上的布局也十分重要。
布局应考虑分离敏感信号和不敏感信号，将不同信号类别的器件分布在不同区域。
同时，要避免信号层与电源层（或地层）太过接近，应间隔至少一层其他层。
3. 地线在以太网电接口中，地线的规划和布线是十分重要的。
在PCB上，应保持地面干净和光滑，避免短路和信号串扰。
此外，应在地铺设好装置引脚的直接连接，避免共振现象的发生，保持电抗联源。
同时，要尽量减少地线的共同部分，以避免漏泄电流在不同层之间的传播。
4. 滤波电容为减少电磁干扰，在接口两端应布置抗搅扰滤波电容。
在这里，应选择滤波电容容值、材料以及其布线位置做好设计，以满足电磁兼容要求。
应将滤波电容放置在距离器件尽可能近的位置上，使其具有最大的采样效果。
5. 接地端口在接口的连接形式上，一般可以选用以太网连串和RJ45插座两种方案。
在接地端口的连接上，应选取好质量较高的接地砂纸，确保连接良好。
6. 电源供给在以太网接口的设计中，应考虑并满足器件的电源供给要求。
应选用超低噪声稳压器，以保证电源纹波的较低水平。
在电源供给的接口布线上，要避免与信号线并行，对于高频分立器件，应将滤波电容布置在它们的电源引脚附近。
以上是以太网电接口EMC设计指导书，设计人员在设计过程中需要避免一些错误，使其更符合EMC要求。
华为高可靠性设计指导(手抄本)
1图 1Consistency Grounp《软件公司地理容灾设计指导书》基于EMC 磁盘陈列的硬件数据复制也能实现数据层面的容灾。
TELLIN 容灾系统对信令的切换控制根据网络配置的不同，主要支持备用信令点模式和GT 翻译路由模式。
备用信令点模式由SCCP 检测信令点的状态自动实现信令业务的转接；GT 翻译路由模式通过修改STP 上的GT 翻译数据实现信令的切换。
图 2TELLIN的CDR容灾和GDR容灾组网示意图设计参考：支持动态资源管理的BOSS双中心系统双中心配置，业务负荷分担设计，每个中心同时承载对方中心的备份业务，实现了基于虚拟化的动态资源调整技术，即一台物理主机划分成假如干个分区，每个分区有独立的操作系统，系统管理员可以自由添加、删除或分区间移动系统资源.例如CPU、内存、I/O适配器的分配，而不需要重新启动系统。
在主机、分区和业务的分配上，设计为：1)物理主机分为多个分区；2)将同一业务中一个中心主用端和另一个中心备用端部署到同一台物理主机；3)同一主机所在分区承载业务为关键与非关键搭配；4)将主机剩余的资源和局部备用资源统一放在预留资源中；5)同一主机的预留资源可以灵活在生产局部和备份局部之间动态调整。
对于突发的资源需求或者定期的资源需求，可以动态调整资源，以保证系统运行稳定。
1.3 网络冗余容错要求单条链路存在故障时，整个网络系统不失效。
网络提供的业务仍是根本可用或者网络可以降级运行。
设计上，要求在组网上对网络节点之间的链路提供冗余。
冗余方式可以通过网元之间的直接并行连接，也可以通过其也网络节点迂回实现，并要求主备用链路经过不同的物理连接。
设计参考：设备冗余组网路由器、防火墙、负载均衡器、局域网交换机、光纤交换机等网络设备全部采用冗余设计。
主机上，所有业务主机采用冗余，非关键服务器使用单机。
网络连接冗余设计主要保证单个网络连接异常或接口卡故障时，设备之间仍有备用通道可以正常访问。
EMC设计实例教程
3
二.何时解决EMC问题
在产品设计的早期阶段，解决电磁干扰的途径多，将花费较少的成本；到产品生产后 期再采取解决电磁干扰的技术措施，将受到各种情况的制约。并且，采用同样的技术 措施，在生产后期采用时，将大大增加成本费用，使费效比增大，使生产进程拖长， 对工程带来不利影响。
三.EMC三要素
EMC设计均可以从EMC三要素着手 EMC三要素包括：干扰源、耦合途径、敏感设备
若系统各线路或装备所产生或需要 的能量变化太大，则不适用串联单 点接地，因为高能量的线路或装备 所产生大量的地电位会严重地影响 低能量线路或装备的正常运作
并联单点接地最大的缺点 是耗时费料，由于接地线 太多太长，以至增加各地 阻抗，尤其在高频范围中 更加严重。
b.多点接地 在频率低于10MHz时，较适于单点接地。若在高频(>10MHz)情况下，由于 接地线的长度及接地电路的影响，单点接地无法达到去除干扰的效果，此时 就得使用多点接地。此时接地线的长度亦应尽量缩短。右图中各接地点可视 为机壳或接地板：
14
1.接地
同轴电缆因具有较均匀的特性阻抗和较低的损耗，使得它从直流到甚高频都有较好的性能。 大多数的屏蔽电缆都是用金属编织层来屏蔽的，编织层的优点是柔软和耐用，但编织层的不致 密会使屏蔽效果变差，而且编织方式使屏蔽电流的均匀性变差，因此防磁场效率要比金属箔屏 蔽电缆低5～30dB。另外，在高频下，编织层的孔隙与波长之比变大，使得屏蔽性能下降。 对有薄铝屏蔽层的电缆，则屏蔽层对芯线的覆盖率达到100％，所以有着较好的电场屏蔽效果。 它在强度上不如用编织层的屏蔽电缆，而且端接情况也较差。 更好的屏蔽电缆是由箔层与编织层组合的，编织层可解决360°的连续端接，而金属箔层则可覆 盖编织层的孔隙。
EMC测试指导书
EMC测试指导书编写人员:杨继明工号:0807252M修订记录目录（报告完成后请更新）1概述 (5)1.1 试件名称、型号、版本及工作电压和电流 (5)1.2 测试性质 (5)1.3 采用标准、采用依据及测试项目列表 (5)1.4 辅助设备列表 (6)1.5 测试人员、参试人员 (6)1.6 测试部门、地点、时间 (6)2受试设备配置 (6)2.1 实物配置框图 (6)2.2 工作状态 (7)2.3 测试组网 (7)2.4 结构描述 (7)2.5 单板配置 (7)2.6 接口及接口电缆配置 (7)2.7 抗扰度说明 (8)2.7.1 监控信息 (8)2.7.2 抗扰度判据 (8)3总结和评价 (8)3.1 测试充分性评价 (8)3.2 测试差异说明 (8)3.3 测试项目通过清单 (9)3.4 问题及相关对策 (9)3.4.1 问题描述 (9)3.4.2 对策描述 (10)4测试内容 (10)4.1 电磁骚扰测试 (10)4.1.1 测试任务1——辐射骚扰测试（RE） (10)4.1.2 测试任务2—传导骚扰测试（CE） (13)4.1.3 测试任务3——谐波电流骚扰测试(Harmonic) (16)4.1.4 测试任务4 ——电压波动与闪烁测试(Fluctuations and flicker) (17)4.2 电磁抗扰度测试 (18)4.2.1 测试任务1——射频电磁场辐射抗扰度测试(RS) (18)4.2.2 测试任务2——传导骚扰抗扰度测试(CS) (19)4.2.3 测试任务3——电快速瞬变脉冲群抗扰度测试(EFT/B) (21)4.2.4 测试任务4——静电放电抗扰度测试(ESD) (22)4.2.5 测试任务5——电压跌落、短时中断与电压缓变抗扰度测试（DIP/interruption 〕 (24)4.2.6 测试任务6——浪涌抗扰度测试(SURGE) (25)4.2.7 测试任务7——工频磁场抗扰度测试(PMS) (29)附录一：相关测试仪器信息 (32)附录二：测试仪器不确定度： (34)附录三：骚扰测试曲线和数据： (35)附录四：测试布置照片： .............................................................................. 错误！未定义书签。
EMC Design Guide
EMCProduct Design GuidePrepared by: Victor H. Kee, P.Eng VP Marketing & Business DevelopmentUltratech Group of labs 3000 Bristol Circle Oakville, Ontario Canada. L6H 6G4Phone: (905) 829-1570 Fax: (905) 829-8050Table of ContentsEMC COMPLIANCE BY DESIGN (1)The Cost of Non-Compliance (2)THE PCB (PRINTED CIRCUIT BOARD) (3)Single or Multilayer (3)Choosing the right logic family (3)The Current Loop (4)Reducing Current Loops (4)Spread-spectrum clocking (6)Power Grids (7)De-coupling Capacitor Values (8)Matching the high speed clock lines (9)Isolating PCB Areas (10)Interface and Connector Ports (11)Component Placement and Layout on the PCB (12)PCB Plane Topography and edge effects (13)The PCB area under I/O Connectors (14)The Power Supply (15)Filtering of AC power line (15)I/O Cables and Connectors (16)Internal Cables (17)The Chassis Enclosure (17)Grounding (18)Preparing a sample for EMC tests (18)FINDING A COST-EFFECTIVE SOLUTION TO NON-COMPLIANCE (21)PCB Layout (21)Cable, Cables, Cables (21)Chassis Construction (22)EMC Design Guide Summary (23)EMC COMPLIANCE BY DESIGNEMC compliance can be approached in several ways. The most common approach taken is to design the product for functionality and price and then to test the product to obtain final product certification prior to the marketing of the product. This approach is still the most common used and often results in band-aid and add-on fixes at the production stage to resolve emissions and immunity problems not taken into account in the initial product procurement specifications. In the majority of situations, a product stands ready to ship pending the final acquisition of the product certifications. The time spent in bringing a product into compliance after it has been designed and prototyped usually impacts the whole sales and marketing process and in some special cases, has been known to put a company under. Our most often made request when this happens is:"Bring the product into compliance without making any changes!!!"Sadly enough, we live in the real world of cause and effect and once the product has been finalized for production, the noise suppression options available to us reduces substantially and even these can be quite costly to implement in mass production runs. Statistically speaking, about 80% of the products we test for compliance need some degree of added suppression for emissions and/or immunity.Since the subject of noise suppression is not taught formally in most universities and colleges, most design engineers will have to go through the school of "hard knocks" to acquire the experience and training in order to produce compliant designs. The design team can only do this through a coordinated effort involving both the mechanical and electrical departments since noise suppression is often three dimensional in nature. The best approach to compliance design is to be able to anticipate at each design stage, potential noise issues and to suppress them early in the design cycle. This is by far the best and most cost-effective approach and is one we highly recommend. Noise suppression in this way, can be taken one step at a time rather than waiting until the product is ready for production. Once this strategy has been adopted, the noise mitigation techniques will often be simple and straightforward to implement because there are less constraints on the techniques available.Over design is part of an engineering trait used to provide a safety margin to take into account deviations of tolerances in components and processes. Bulletproofing a design from the viewpoint of noise suppression can only enhance the performance of the product especially in processing analog signals such as audio and video signals. Experience has shown that designs, which incorporate suppression at each stage, have a 90% chance of meeting the final requirements without the need of additional suppression.Interface and Connector PortsAll intersystem interface and connector ports should have all leads (both signal, dc power, and grounds),Component Placement and Layout on the PCBBefore beginning to layout a PCB, the first step is to identify all critical components that affect the emissions characteristics of the board. These would be:• Crystal oscillators• CPUs, video processors and I/O processors• Clock division and driving circuits• I/O circuitry• Memory blocksThe next step is to locate the interconnecting components as close together to minimize trace run length. This usually means oscillators, processors and clock regeneration and divides down circuits in very close proximity. Placement of these high frequency elements is critical and is usually relegated to the center of the board away from all I/O connectors and internal cable runs and jumper straps. The memory chips should be laid out so that overall loop areas are minimized.After the main component locations have been selected, concentrate next on the ground return paths for each of the high frequency signal traces. For multilayer boards this is usually not an issue but on double sided single layer boards, this step is of paramount importance. Each high-speed signal trace should have a ground return path run next to it or even on both sides of it.Where buses are run along the board or to a back plane, it may not be possible to provide a ground return trace for each signal. The alternative is to provide a ground for every two or three traces. The effect here is to reduce the loop areas in the bus run. This is especially effective if the bus is extended off the board by dip header or ribbon cables.Another must at this stage is to consider what-if scenarios in the event additional suppression is required in the finished product. After all, odds are that there is only a 20% chance that you won't need additional suppression. Provide pads or through-holes for the mounting of suppression components on all signals going to the I/O interfaces. The mounting points must be as close to the I/O connector as physically possible to reduce coupling back onto the I/O signals after the filters. Any unused signals on the I/O interface should be tied to ground directly or through a capacitor. For the oscillators and clock driving points, provide mounting points between clock output and ground for smoothing capacitors. If the clock traces are long and not buried between ground and supply planes, provide mounting points for ferrites and capacitors at one or two points in the trace run.The oscillator cans usually provide voltage swings in excess of 7 volts; in most cases a 3-volt swing is sufficient. Reducing the voltage swing of clock signals by selecting low output oscillator modules will certainly help as will rounding the output of the oscillator using capacitors. This being the case, another way of reducing the voltage swing on the oscillator output is to reduce the supply voltage from 5 volts to say 3 volts using a voltage divider or resistor in the supply lead.Mounting pads for resistors or ferrites can be placed along the trace run and if these become needed, the trace between the pads can be cut very easily. These suppression points may or may not be used depending on theInternal CablesInternal cables are a critical path for emissions propagation from one area of the chassis to another. Care has to be taken with regard to internal cable routings especially with respect to flat ribbon cables. There is a misconception among designers that emissions are restricted to signals of high frequency and therefore DC cables and control leads need not be isolated. This could not be further from the truth. Any ungrounded metal or conductor is a potential path for emissions and should be treated so. Internal cable routings should be carried out with careful placement of the cables away from the PCB board - especially the high frequency are of the board where the oscillators and processors are situated. All cables should be secured with tie-downs to prevent loose cables falling onto or near the PCBs.If ribbon cables are used, employing distributed ground return paths will help to keep the current loop areas to a minimum. Keep these cables as short as possible using the shortest route away from the PCB and I/O connectors.Improper shield terminations are a common source of emissions on connectors. Where the shield does not make contact with the metal shell and the vinyl jacket then serves to create a small gap for emissions leak.If a plastic shell is used for the connector housing, then the shield may be connected to ground by a pigtail onto the chassis ground as near to the connector as possible to keep the pigtail length to a minimum. While this is not an optimal termination, the pigtail can help to reduce emissions significantly if connected to the right point on the chassis. Grounding of the pigtail to signal ground is not a correct approach since the ground path to chassis ground is through the systems power supply.Emissions from poorly shielded cables can further be reduced by application of filtering capacitors on each of the inner conductors to ground. The filter capacitors must be placed as close to the connector to be effective while keeping the capacitor leads as short as possible. Filter capacitors are typically between 100pf and 5600pf values depending on the type of signal present on the line being filtered. Too much capacitance may distort the signal significantly as to effect the functionality of the interface especially if long cable lengths are involved. Again if the capacitor value is limited by the distortion it may cause on the interface signal, in-line inductors may be added to enhance the filtering effect. As another option, ferrite mounts specifically designed for I/O connector mounts may be used to prevent high emissions from ever reaching the I/O cable. T HE C HASSIS E NCLOSUREThe chassis enclosure is preferably metal or metal-coated plastic. If a cover or front panel is used, one has to ensure good electrical bonding along the seam edges. One aspect of a metal chassis housing is that they usually get painted or anodized which prevents the covers from making a good electrical bond with each other. This usually leads to slot antennas being formed along the cover edges and usually results in high frequency problems above 300MHz. The amount of leakage from a seam depends on the following:1. The maximum linear dimension (not area) of the opening.2. The wave impedance.3. The frequency of the source.shield has been terminated. In addition, investigate that the mating connector is directly grounded to the chassis housing.• The EUT chassis should have proven ground continuity on all metal components. Star washers are a common way to ensure that painted metallic covers make good electrical contact with the rest of the chassis. Any metal covers that are not properly grounded will act as a sheet antennas radiating energy to the system cables and the surrounding peripherals.• All opening and slots should be covered with metal panels or metal mesh, which make electrical contact with the chassis housing every few centimeters wherever possible. Shielding of Air vents used forinternal cooling or aesthetic purposes may be carried out using grounded fine wire mesh to reduce the risk of a slot antenna effect from the vents slots. Ventilation slots should be implemented with holes rather than slots.• Filters used on power lines or I/O connectors should be mounted as close to the cable entry point to be effective. Some systems extend the power cord to the front of the chassis for user accessibility to the power switch. In this case the ac power line filter should be placed on the ac cord at the point where it enters the chassis.• Crystals and high frequency oscillators mounted too close to the I/O connectors or any openings in the chassis make obtaining compliance that much more difficult. Placement of high frequency oscillators should be done with the following in mind;1. Keeping the trace leads that carry the high frequency components as short as possible. In multiplayerdesigns, these traces should be sandwiched between the ground and power planes with guard traces run along either side of the trace in the same plane.2. For long high frequency carrying trace leads, Pico-farad coupling capacitors or ferrite beads may beused to bleed off some of the higher frequency components. Matching resistors at the source end of the trace also should be provided.3. High frequency components may be isolated from the rest of the chassis by placing them in a separatemetallic grounded enclosure or by using picket fences.• Internal cabling and routing can have a significant effect on obtaining compliance. Cable routes should be selected to be as far from high frequency components as possible and as close to the chassis housing as possible. Chassis eyelets along cable routes assist in securing the internal cables to selected routes to minimize repeatability issues during the tests. Flat ribbon cables are a common form of interconnecting sub-assemblies. Due to the nature of the ribbon cable, they are very good radiators and susceptors of emission energy and so extra care in ribbon cable routings should be taken. Using shielded cables or metallic ducts for internal cable interconnects significantly adds to the design margin for obtainingcompliance provided the shields could be properly terminated.• For plastic and non-metallic enclosures that contain unshielded high frequency components, metallic coatings such as nickel or copper can be applied to the inside of the units to provide the shieldingnecessary to obtain compliance. Aluminum vacuum coating has been shown to provide consistent anduniform coverage.FINDING A COST-EFFECTIVE SOLUTION TO NON-COMPLIANCEPCB LayoutAny modification to a finished system will add significant costs to the final production unit. It is therefore important to reduce the emissions at a very early stage in a products development cycle since board level fixes during the early stages of development are the most cost-effective solutions to emission problems. Designing for EMI compliance is normally carried during the PCB layout stage where location of the high frequency components and trace layouts are determined. Some design engineers will leave plated through holes or surface mounting pads at strategic places on the PCB, to allow for the addition of filter capacitors or in-line ferrites/inductors on the prototype boards.The prototype PCB may then be probed for hot spots using a high frequency oscilloscope or spectrum analyzer. What design engineers look for is high-speed waveforms with a rich harmonic content. Once the hot spots have been localized, appropriate suppression filters may be added to reduce high harmonic content on the trace while preserving the signal integrity. These is sometimes referred to as the cut and try method whereby various positions on a trace are cut and RF chokes added to determine the most effective location for the filter.Cable, Cables, Cables....Unshielded cables and flat ribbon cables are a primary concern to any EMI engineer because of their potential for becoming wire antennas if the emissions are not properly contained in the EUT chassis. Cables and their associated connectors are usually the first area checked if emissions are found to exceed the limits. Typically, cables will be disconnected one at a time in an attempt to isolate where the emissions are emanating from Once the source has been detected various options are available in reducing the emissions radiating from a cable.• Using a shielded cable• Placing filtering capacitors and ferrites on the I/O connector if the connector is PCB mounted.• Placing a ferrite choke on the cable right at the connector. The number of turns through the choke determines the attenuation of the emissions.Chassis ConstructionConstruction of the chassis is considered when it has been determined that the emissions are not coming from the I/O connectors/cables. Checks are made on the following;• The mating of the enclosure cover with the chassis frame is checked for gaps and slots where emissions could possibly leak.• Electrical continuity between the cover and chassis is checked to ensure that good electrical bonding is occurring.• Emissions from vents or slots are checked by temporarily covering them with copper tape to see if this reduces the level of emissions. If this is the case, modifications with fine wire mesh may be used to prevent emissions leak from the EUT.• Some front covers on EUT are non-metallic resulting in high emissions being measured from the front of the EUT. Conductive coatings such as nickel or copper based may be applied with special attention given to how the cover will be electrically bonded with the chassis frame. The preferred approach is to have the electrical bonding all around the edge of the cover panel so that it provides a good emission seal to the front panel.Any modifications for compliance are a costly consequence. It is more easily achieved and much more cost-effective when conducted at the design stages than to carry out the modifications in the production phase. For companies that do not design with EMI compliance in mind, the risk of failing a qualification test is about 80%. The associated cost and time of getting a non-compliant product to market should be weighed off against the cost of implementing some EMI compliance programs within the organization. Education of product and design engineers into the additional requirements of not only designing for functionality but also for compliance should be carried out at a minimum.Product and design engineers are urged to witness EMI compliance tests to familiarize them with the potential problem areas associated with their product line. It is quite often that fixes made on a single model can be carried over to other models of a production line with great success. In this way, design and product engineers will improve the compliance of their products by incorporating previous suppression techniques at the board level into later models.EMC Design Guide SummaryChassis: A completely enclosed metal chassis is the preferable enclosure. Care should betaken to ensure that along the scam edges, good electrical bonding is made betweenany covers and chassis. This usually means paint masking at overlapping jointareas, use of beryllium-copper fingers or conductive polymer gaskets. If a plasticenclosure is necessary due to marketing pressures, it is recommended that a tinenclosure inside the plastic chassis still be used to house the high frequency PCBsmuch the same way TV and radio circuits are isolated. Failing this, metallizedcoating will be a minimal requirement in the presence of PCBs with high density,high speed logic.PCBs:Multilayer PCBs with ground and supply planes are generally about 10dB quieterthan equivalent double sided PCBs. More suppression can be obtained by buryingthe high frequency traces between, ground and supply planes. The catch withburying too many traces inside the PCB is that it makes trouble-shooting the boardextremely difficult. Ensure that there are no copper planes underneath I/Oconnectors and their filter circuits except chassis ground plane. On the PCB edges,back off all signal traces from the edge by a couple of millimeters.Trace lengths:All high frequency components should be localized near the centre of the PCBaway from jumper, I/O connectors, internal cable routes and main BUS areas. Allhigh frequency traces should be kept as short as possible so that IC placementshould be dictated by the optimal length of hot traces around the PCB.Pads for suppression:When laying out a PCB, it never hurts to design in suppression components for de-coupling capacitors and maybe even in-line ferrites and terminating resistors usedin reducing ringing in clock traces. This especially useful with regard to RS-232,parallel port interfaces and telecommunications interfaces. The PCB need not bepopulated until the suppression components are proved necessary and if this occurs,no re-layout of the PCB needs be carried out to achieve compliance.I/O connectors:Shielded cables are recommended where possible. The shield should be terminated with a 360 degree contact onto the I/O connector shell. The shield should always beground directly to chassis and not to signal ground.Pigtails:Avoid at all cost. Keep it as short as possible if you have to use it. Pigtails cause us no end of trouble – even the 1” variety.Internal cable routes:Route cable as far away from high frequency oscillators and components. Alsoensure that they are neatly bundled and tied down. If flat ribbon cable is used, makeit as short as possible and select the mounting headers on the PCB board away fromhigh frequency components and traces.Grounding:I am convinced that there is no right: way to ground a PCB with regard to EMC. In general, most PCB designs come with four or five grounding points which directlytie the signal ground to chassis across the PCB. We have observed limited successin reducing emissions by removing some of these ground points from certainmotherboards – especially in the areas of the high frequency oscillators. Ourapproach is still trial-and error and we go with whatever works.With respect to ESD, proper grounding of all metal throughout a product must bemade. A resistance of a few ohms is insufficient electrical bonding to prevent largeamount of potential difference in the sub-nano second events of a discharge.Ensuring-that all metal components jump at the same time is one key to meetingESD threats.Grounding braids which are flat and wide should be used over round wires tointerconnect internal metal frames.Separate ground grids should be maintained for analogue, digital, hardware andchassis grounds with one common point at the power supply secondary. It is also agood idea to keep the various circuits isolated from each other on the PCB.Shielded cable in a desktop environment should be grounded to chassis ground atboth ends. In distributed systems, care should taken with the shield since largepotential differences in the earth grounds at different location s will introduce largecurrent loops which are carried on the cable shield. In certain cases, a hybridground may be used by connecting the shield to ground at one location through a0.1uf capacitor.Air vents:Air vents of the multiple hole variety are preferable. Vent slots may used so long as the slot length is kept to less than 1/10th of the highest frequency wavelengthencountered in the product. Since the highest frequency component is usually aharmonic of one of the internal oscillators, the optimal slot length may no easily bedetermined.Power Supplies:Power supply filters and surge suppressors should be lace as close to the point ofentry as possible. Any exposed length of power supply line routed internally shouldbe shielded of isolated from the PCB. The most effective power supply filters areshoes incorporated in the AC receptacle plug. Remember, the ac line filter is toprotect the hydro network from receiving RF noise from your device – not thatother way around.In switches, care should be taken on routing internal cables away from switchingtransistors and the high voltage transformers as harmonics of these are oftenobserved in VDE and CISPR conducted emissions measurements which begin at 10KHz and 150 KHz respectively. All main switching diodes and FETS must havethe ringing reduced using snubber networks usually of the order of100pf/1000ohms. This is also true of the feedback control signal which also mayhave to be treated with ferrites to reduce high frequency content.Overloading or under loading a switching power supply causes more switchingnoise to be generated - especially if an external switcher is used as in the case oflaptops.Minimizing crystals:As the number of crystal oscillators increase, so do your chances of running into a emissions problem. Although this is a broad generalization, we’ve had a lot moresuccess with single oscillator products where all timing is derived off one clock.Personal computer motherboards are trending towards this with single frequencysynthesizer chips for the main processor and video function.。
华为电磁兼容性结构设计规范_第三版
华为技术有限公司企业技术规范DKBA0.400.0022 REV.3.0 电磁兼容性结构设计规范2003-11-30发布2003-11-30实施华为技术有限公司内部公开前言本规范于1999年12月25日首次发布。
本规范于2001年7月30日第一次修订。
本规范于2003年10月30日第二次修订。
本规范起草单位：华为技术有限公司结构造型设计部本规范授予解释单位：华为技术有限公司结构造型设计部本华为机密，未经许可不得扩散第1页，共1页内部公开目录1 范围 ... ....................................................................................................................................................... ..42 引用标准 ... . (4)3 术语 ... ....................................................................................................................................................... ..44 电磁兼容基本概念... (5)4.1 电磁兼容定义 ... .............................................................................................................................. ..5 4.2 电磁兼容三要素 ... ........................................................................................................................... .54.3 通讯产品电磁兼容一般要求 ... ..................................................................................................... ..65 电磁屏蔽基本理论... (7)5.1 屏蔽效能 ... ....................................................................................................................................... .7 5.2 屏蔽体的缺陷 ... .............................................................................................................................. ..75.2.1缝隙屏蔽 ... (7)5.2.2开孔屏蔽 ... (8)5.2.3电缆穿透 ... . (10)6 屏蔽设计 ... .. (12)6.1 结构屏蔽效能 ... .......................................................................................................................... (12)6.2 屏蔽方案与成本 ... ....................................................................................................................... ..12 6.3 缝隙屏蔽设计 ... .......................................................................................................................... (13)6.3.1紧固点连接缝隙 ... . (13)A. 减小缝隙的最大尺寸 ... ........................................................................................................................... .. 13B. 增加缝隙深度 ... ........................................................................................................................................ .. 14C. 紧固点间距 ... ........................................................................................................................................... (15)6.3.2安装屏蔽材料 ... ....................................................................................................................... ..176.3.3屏蔽材料的选用 ... . (18)A. 常用屏蔽材料................................................................... .. 18B. 常用屏蔽材料性能参数 ... ........................................................................................................................ . 246.4 开孔屏蔽设计 ... .......................................................................................................................... (25)6.4.1通风孔屏蔽 ... .......................................................................................................................... (25)6.4.2局部开孔屏蔽 ... ....................................................................................................................... ..26 6.5 塑胶件屏蔽 ... . (27)6.6 单板局部屏蔽 ... .......................................................................................................................... (28)6.6.1盒体式屏蔽盒 ... ....................................................................................................................... ..28内部公开6.6.2围框式屏蔽盒 ... ....................................................................................................................... ..29 6.7 电缆屏蔽设计 ... .......................................................................................................................... (29)6.7.1屏蔽电缆夹线结构 ... .............................................................................................................. (29)6.7.2屏蔽连接器转接 ... . (33)6.7.3非屏蔽电缆 ... .......................................................................................................................... (34)7 典型结构屏蔽方案... . (35)7.1 2000机柜屏蔽方案 ... . (35)7.2 2000插箱屏蔽方案 ... . (37)7.3 S3026C钣金盒式结构屏蔽方案 ... (42)7.4 R413PAVO塑胶盒式结构屏蔽方案 ... ..................................................................................... (44)7.5 型材面板屏蔽 ... .......................................................................................................................... (47)7.6 钣金面板屏蔽 ... .......................................................................................................................... (49)7.7 扣板面板屏蔽 ... .......................................................................................................................... (52)7.8 防水&屏蔽结构 ... ....................................................................................................................... (54)内部公开电磁兼容性结构设计规范1范围本规范规定了电磁兼容性结构屏蔽设计的主要原理、设计原则和详细设计方法。
(完整版)华为传输EMC基础知识
资料编码产品名称使用对象产品版本编写部门资料版本EMC基础知识拟制：日期：审核：日期：审核：日期：批准：日期：华为技术有限公司版权所有侵权必究EMC基础知识文档密级：内部公开修订记录日期修订版本作者描述EMC基础知识文档密级：内部公开目录课程说明 (1)课程介绍 (1)培训目标 (1)参考资料 (1)1序论 (2)1.1电磁兼容概述 (2)1.2电磁兼容性的基本概念 (2)1.2.1电磁骚扰与电磁干扰 (2)1.2.2电磁兼容性(EMC-Electromagnetic Compatibility） (3)1.2.3电磁兼容常用名词术语 (3)1.3电磁干扰 (4)1.3.1电磁干扰三要素 (4)1.3.2电磁兼容研究的主要内容 (4)1.4基本的电磁兼容控制技术 (5)1.5电磁兼容标准 (5)1.5.1电磁兼容标准的制订 (5)1.5.2EMC标准拟订的理论基础 (7)1.5.3电磁兼容标准的分类 (7)1.5.4产品的电磁兼容标准遵循原则 (8)1.6电磁兼容测试技术简介 (9)1.6.1概述 (9)1.6.2EMC测试项目 (9)1.6.3电磁发射 (9)1.6.4抗扰性EMS (9)1.7EMC测试结果的评价 (10)1.8产品EMC设计的重要性 (10)1.9产品的认证 (11)小结： (12)思考题： (12)2EMC基础理论 (13)2.1电磁骚扰的耦合机理 (13)2.1.1引言 (13)2.1.2电磁骚扰的常用单位 (13)2.1.3传导干扰 (15)EMC基础知识文档密级：内部公开2.1.4辐射干扰 (16)2.2电磁干扰的模式 (17)2.2.1共模干扰与差模干扰 (17)2.2.2PCB的辐射与线缆的辐射 (18)2.3电磁屏蔽理论 (20)2.3.1屏蔽效能的感念 (20)2.3.2屏蔽体上孔缝的影响 (20)2.4电缆的屏蔽设计 (20)2.5接地设计 (21)2.5.1接地的概念 (21)2.5.2接地的种类 (22)2.6滤波设计 (23)2.6.1滤波电路的基本概念 (23)2.6.2电源EMI滤波器 (23)小结： (24)思考题： (24)3系统安装和维护 (25)3.1系统安装的EMC要求 (25)3.1.1概述 (25)3.1.2系统环境要求 (25)3.1.3防整机安装 (25)3.1.4电缆布线要求 (26)3.2系统维护 (28)3.2.1防静电要求 (28)3.2.2系统检视 (28)3.2.3系统干扰问题的处理 (28)小结： (29)思考题： (29)EMC基础知识文档密级：内部公开课程说明课程介绍本课程分三个章节，分别从概念，基本理论和系统方面简单介绍了EMC的基本概念、标准、测试内容，产品认证和电磁兼容的基本理论，最后介绍了系统安装和维护中的EMC问题。
华为PCB的EMC设计指南
94PCB EMC( )2000/09/01EMCEMC1.002000/09/01EMCPCB0001PCB EMC303.4.6 ..............................................293.4.5 ...................................283.4.4 ................................................273.4.3 ESL ...................................27 ..................................253.4.2 ...............................................253.4.1 ...............................................253.4 PCB EMC .......................................253.3.2 .........................................243.3.1 ...............................................243.3 ........................................................233.2.5 ....................................................233.2.4 ..................................................233.2.3 .......................................................223.2.2 .......................................................223.2.1 .......................................................223.2 ........................................................213.1 ............................................................21 ...............................................................192.2.5 ...................................................182.2.4 ................................................182.2.3 ...................................................182.2.2 ...................................................172.2.1 ...................................................172.2 ...................................................162.1.4 ...................................................162.1.3 ................................................162 .1.2 .................................................162.1 .1 .................................................162.1 .......................................................16 .............................................111.3.3 ................................111.3.2 Vcc GND ........................111.3.1 Vcc GND EMC (11)1.3 .....................................101.2 .........................................101.1.2 ...................................................101.1.1 Vcc GND .. (10)1.1 (10)1 ...........................................................10 ..........................................................8 .................................................................. EMCPCB0001PCB EMC605.1.2 .........................................595.1 ........................................................595 ...............................................................584 ......................................................563.5 ....................................................553.4.2 ......................................543.4.1 ........................543.4 .............................................533.3.3 25 mil ..............523.3.2 13 mil ..............513.3.1 5mil ................513.3 ....................................................503.2 ........................................483.1.3 ..................................473.1.2 ...................................................473.1.1 ..................................................473.1 ...............................................473 ..........................................................452.2 .................................................432.1.3 .........................................432.1.2 Stripline ............................................422.1.1 Microstrip ...........................................422.1 .............................................422 .........................................................401.3 ...........................................................381.4 ....................................................371.3.3 ................................................371.3.2 Stripline ............................................361.3.1 microstrip ...........................................361.3 ....................................................361.2 ......................................................361.1 .........................................................361 ...............................................36 .........................................................344.4.3 ................................................344.4.2 ................................................344.4.1 ................................................344.4 ......................................344.3.4 ................................334.3.2 ...................................................324.3.1 ...................................................324.3 ...................................................324.2 ......................................................324.1 ......................................................324 ...................................................... EMCPCB0001PCB EMC782.1 (77)2 .........................................................771.2 ....................................................771.1 .. (77)1 ...............................................................77 PCB EMC (76).....................................................76 .......................................75 .. (75)...................................................75 ......................................................74 ......................................74 . (74) (74)2 EMC (74)1.2.2 ..................................721.2.1 . (72)1.2 ....................................................721.1 .. (72)1 .......................................................72 EMC ................................................717.5 EMC ..........................................707.4 EMC ............................................707.3 EMC ............................................707.2 ....................................................697.1 EMC .. (69)7 EMC (67)6.3.6 ..........................................666.3.5 ...........................................666.3.4 .............................666.3.3 ............................666.3.2 PCB ...................666.3.1 .. (66)....................................................65 .........................64 ...............................................63 .. (63).........................................63 ........................................63 . (63) (63)6 (61)....................................605.2.1 .. (60)5.2 ...................................... EMCPCB0001PCB EMC931.5 ......................................................931.4.5 ..................................................931.4.4 ................................................931.4.3 .......................................931.4.2 .........................................931.4.1 PCB .............................................931.4 ......................................................921.3 ...............................................911.2.4 ..................................................901.2.3 PCB ..............................................901.2.2 .............................................901.2.1 ...........................................901.2 ........................................................901.1 ...........................................................901 PCB .................................................90 .........................................................896 ......................................................885.8 ..........................................885.7 .....................................................865.6 ...................................................865.5 ....................................................855.4 ....................................................855.3 ......................................................855.2 ...........................................................845.1 ........................................................845 ...............................................................844.5 ...................................................844.4 ...............................................834.4 ....................................................834.3 ....................................................834.2 ......................................................834.1 ........................................................834 ...............................................................823.2 ..............................813.1 ...............................................813 ...............................................................802.5 ....................................................792.4 ...................................................782.3 .............................................782.2 ........................................................ EMCPCB0001PCB EMCPCB EMCEMC EMIPCB EMCPCB EMC PCB EMC PCB EMCEMC-Electromagnetic CompatibilityEMI Electromagnetic InterferenceHigh-Speed Digital Design : Emi BookEMC Training for EMC design)IEC 60950 Safty of Infomation Technology Equiment GB4943-2000 PCB EMC PCBEMCPCB0001PCB EMCPCB EMCEMC(EMC-Electromagnetic Compatibility) GJB72-855.10 ( ) ( )EMC EMC CAD SI EMC EMCEMI PCB CADEMC EMC QCC CAD PCB EMC CAD PCB EMCPCB EMCCAD EMC SI EMC PCB EMC EMC1 42 4 73 5EMCPCB0001PCB EMC3 6 3 12PCB EMC PCBPCB EMC EMC CAD EMCCAD EMCNOTES 09351 PCB EMC2000-09-01EMCPCB0001PCB EMC1PCB EMC EMC1.1EMC CISPR16 CLASS B PCB EMC1.1.1 Vcc GNDPCB 8260 IC 22 248V BGND1.1.2CAD EDA CADEMC1.2EMCPCB0001PCB EMCVCD 6 PCB GSM GSRPCB PCB2.0mm 4 2000 710.599.12167.656.4714 2.212.155.594.5612 1.621.623.973.3510 1.531.292.472.038 1.030.821.761.4160.620.591.261 40.340.320.590.472 3.0mm 2.0mm 3.0mm2.0mm1.31.3.1 Vcc GND EMCPCBPCB1.3.2 Vcc GND1.3.3EMCa. b. c. d. e.50MHZ 50MHZa. b.c. d.PCB* 1 3SGPS2113P S S G 2112S P G S 21114321 1TOP GNDPOWER BOTTOMCAD PCB TOPGND POWERTOP BOTTOM 2GNDPOWERS1S22 2 2 XXXX XXXA GND PGNDB C123 PCB GNDPGND2 GND S1 S2 PGND S1XX 23TOP GND POWER BOTTOM1 BOTTOM* 3 1 2 4S3PG2S2G1S13214S3G2P S2G1S13213S4S3P G S2S14112S4P S3S2G S14111654321 3 S2 S3 S1 4 5 S2-P P-G2 G1-S2 S21 S1 S2 S3 S4 1 2 S1 S2 S3 S4 S24 3 S2* 2 3 1S4P2G2S3S2P1G1S14225S4G3S3P2P1S2G1S14224S4P2S3G2P1S2G1S14223S4G3S3P G2S2G1S14312S5G2S4P S3S2G1S1521187654321 2 13 3 S44 3-4 5-6 2-3 6-75 4 S2 S3 S4 P2S2 S3* 2 3 1 4S4G4S3G3P2P1G3S2G1S14424S5G3S4P2G2S3P1S2G1S15323S5G4S4P G3S3G2S2G1S15412S6G3S5S4P G2S3S2G1S1631110987654321 3 3-4 7-8 5-6 6 7 S2 S3 S4 S1 S5 S2 S34 EMC 3 EMC S2 S3,2 1 1* 2 3 1 4 5S7G3S6P2S5S4G2P1S3S2G1S17325S5G5S4G4P2P1G3S3G2S2G1S15524S6G4S5P2S4G3P1S3G2S2G1S16423S6G5S5G4S4P G3S3G2S2G1S16512S7G4S6S5G3S4P S3G2S2G1S17411121110987654321 2 4 EMC 1 3142PCB EMC , PCB PCB2.12.1 .1A/D D/A I/OPCB2 .1.22.1.3PCB A/D D/A2.1.4I/OI/O I/O A/D D/A1.2.3. I/O I/O HEAD4.5. ,6. IC7. A/D2.22.2.1DC/DCEMI 300MHz12EMI Array2.2.2PCB 2.2.3EMIPCB2.2.416244 EMI2.2.5PCBIC-----C-----LV33.1PCB 3-13-13-1 IC1 0 1 VCC C dI) L L VV=L DI Dt3-2IC1V 3-33-33-3 IC1 0 1 VCC dI C2 L3.23.2.1RC3-4 ESL3-4 3-43.2.24 ESRf c f c f c3.2.33.2.4100~1500 3-53-5 muRata3.2.53-63-6 muRata3.33.3.1EMC3-7 c d Γ3-7 e Π3-7 f TEMI 3-83-8 EMI3.3.212343.4 PCB EMC3.4.1PCB EMCDecoupleBypassBulk3.4.23-93-9Muti-Layer Capacitor PCB 5nH30m 3-103-10ESL ESR 3-11 3-12 -3-113-123-12 15MHz 175MHz 150MHz3.4.2 ESR3-12 ESR ESR PCB1 ESR2 n ESR/n34 ESR ESR3.4.3 ESLESL ESL 3-13-1 ESLESL ESL3.4.4RF EMI X7R Y5V Z5U3-130805 0.01UF 0.1UF50MHZ MUSA 0.01UF 0.1UF3.4.512 3-12 22nF 11 MHz 1 6M~40MHz3 IC4 IC PCB 3-14 3-14 Vcc Vcc IC3-145 3-146 2 1 3-15 1.5 1.5 3.25MHz 100MHz IC 2 13-153.4.6A 1uf 10uf22uf 33ufB1 4 1uf10uf 22uf 33ufTantalum 10uf 22uf 33uf2144EMC EMI4.1ABCPON16 ESD DMU PGND ( ) ( ) PGND ESD4.2ABC4.34.3.11MHZ1/4 1/20 4.3.2>10MHZEMIB C D E F AIg Zg Vi B E Vi Vi I1 I2 I1 I2 V0 EMIViVi = E dl =−t=−t B dse gII1I2V 0z gI gv i AB CDEFEdlBI1 I24.3.34.3.44.4L 1MHZ 10MHZ L /201 <1MHZ2 >10MHZ34.4.14.4.210MHZ BGND BGND GND PGND AGND DGND 10G4.4.3PCB0.1u( 0.01u)EMIPulseAB 100MILINTELIC PCB CAD11.1PCB 20 6 PCB : EMC EMC EMI1.2CAD1.31.3.1 microstripFR-4 r=4.5TPD = 142.2(ps/inch) 1.3.2 StriplinePCB)(017.1ft ns r PD t ε=)()8.0(67.0ln0Ω+=w t w Z rπε)(100000ft pFZ C PD t =)(0020ft pHC L Z =)(85inch ps r ε FR-4 , r =4.5 TPD = 180.3 (ps/inch) 1.3.3K 15milsK=65 20mils K=601.4( )0.7VZRZ R Z R Z R LL LS S S000+−=+−=ρρEMI1.3PCB C SV C SV PCB EMI PCBLW T H C SV Cti L2,2.12.1.1 MicrostripFR-4 r =4.5Tpd = 142.2(ps/inch)2.1.2 StriplinePCB)(017.1ft ns r PD t ε=)()8.0(67.0ln0Ω+=w t w Z rπε)(100000ft pFZ C PD t =)(0020ft pHC L Z =)(85inch ps r ε FR-4 , r =4.5 Tpd = 180.3 (ps/inch) 2.1.31 38 .1(ps/inch)23420DBEMIEMC18dBEMC12Simense Motorola PCB EMI PCB CADEMC EMC PCB2.2ABC L > L > L ( )G −G G −P P −P DPCB EMCPCB CADS4G4S3G3P2P1G3S2G1S14424S5G3S4P2G2S3P1S2G1S15323S5G4S4P G3S3G2S2G1S15412S6G3S5S4P G2S3S2G1S16311109876543211 S2 S3S2 S3 S4 S5 S2 S3 EMC EMC S4 S5 S2 S3 S5 G3 S4 S1 S6 TOP PIN BOTTOM S6 S2=S3>S5>S4>S6>S1;2 S2=S3>S4>S5>S1;3 S2=S3=S4>S5>S1;4 S2=S3=S4>S1;33.1 3.1.1Ui 1: Zin = U/i 3.1.2PCB PCBPCB2,dU/dz = ( R + jwL) I 1 dI/dz = ( G +jwC) U 2U =A e rz +B e −rz I A e rz −B e −rz3r =(R +jwl ) (G +jwc )4 R G5 Z L /C 6(z )=U −(z )U +(Z )=−I −(Z )I +(Z ) 3.1.33V1 Z11 i1 + Z11 k i2 7 V2 Z22 i2 Z22 k i1 8 ki1= i2, Zo=Z11=Z22V1 Zo 1 k i1 9 V2 Zo 1 k i1 10ZoddZodd = Zo 1 k 11 Zodd Zo2 ZoddZdiff = 2 Zodd 12i1=i2V1 Zo 1 k i1 13 V2 Zo 1 k i1 14Zeven= V1/i1=Zo 1+k 154L1 C1 L12 C12L0 C0 , Kc = C12/C1, Kl L12/L1,1dU1/dz = jwL11*I1+ jwL12*I2 16 dI1/dz = jwC11*U1 jwC12*U2 17 L11 L1 C11 C1 C12U1 U2 Uo, I1= I2 Io dUo/dz = jwL11(1 Kl) Io 18 dIo/dz = jwC11(1 Kc) Uo 19 20Zo =L 11(1−KL )C 11(1+KC )21Vo =1L 11(1−KL )(1+Kc )22Ze =L 11(1+KL )C 11(1−Kc )23Ve =1L 11C 11(1+KL )(1−Kc )TEM Ve =Vo V =1L 0C 0Ve=Vo Kl = Kc = K K 24Ve =Vo =1L 11C 11(1−K 2)=V =1L 0C 0L0 C0 L11 C11 1 K*K 2526 L 11 L 1 L 0 23C11 C0/(1-K*K) 27Z 0=L 0/C 0Zo 1=L 11/C 11 20 22 26 27 Kl = Kc = K28 Zo =Zo 11−K 1+K =Z 0(1−k ) 29Ze =Zo 11+K 1−K=Z 0(1 K ) (10b) (13) PCB PCB40~75 10 33EMC EMC EMC3.2PCB PCB PCB PCB。
EMC测试指导书
EMC设备操作指导书一：此设备可以做EMC中的EMI项目中的辐射测试和传导测试。
二：由于每个国家对EMC测试标准不一样，我们就以中国国标为标准来测试我们的产品，国标文件版本号在后面告诉大家。
三四：在EMI项目中传导测试和辐射测试的频率范围在9KHZ-300MHZ,由于测试方法和测试参数设置要求不同，要把频率范围分为9KHZ-30MHZ和30MHZ-300MHZ来分别测试。
五：EMI测试标准按照国标：GB_17743_2007六六：EMI测试设备：9KHZ-30MHZ通用型。
1：PC电脑2：R3030测试主机3：人工电源网络七：连接图：1：9KHZ-30MHZ的传导测试连接图：2：30MHZ-300MHZ的传导测试连接图：3：30MHZ-300MHZ辐射测试连接图：备注：1：由于设备天线是2M的，只能做30MHZ-300MHZ范围的辐射测试。
所以9K-30MHZ辐射测试不提供连接图。
2：衰减器的作用是衰减信号，保护R3030测试主机。
八：软件使用：1：辐射测试和传导测试用的软件是一样的，所以有的操作方法基本相同。
下面对照图片对软件进行详细说明。
步骤1：软件的启动以后进入软件以后如图一。
备注a ：Hardware 里面是R3030主机与电脑PC 机连接的设置。
b ：System 里面是R3030主机采集信号的参数设置。
c ：Run 是运行软件d:测试9KHZ-30MHZ选择图一步骤2：点击Hardware里面进行R3030主机与电脑PC 机连接的设置，见图二：图二备注：a.Add是添加连接的设置，完成以后如上面的设置，修改IP(Address)为169.254.1.3，这个IP 地址应该和R3030电脑上面的IP地址相同。
b.完成设置点击Check Test,进行测试，通过界面会显示Test OK,回到图一界面。
步骤3：点击System里面进行R3030主机采集信号的参数设置，见图三：图三备注：a.Add是添加参数设置，参数见设置好的数据。
华为产品可制造性设计指导书
单板可制造性设计指导书0定义 Definition可制造性设计：单板可制造性是单板必须具备的、通过良好的单板工艺设计来实现的一个重要特性，具体表现在满足设备工艺能力，大的工艺窗口，高的生产效率，低的制造成本，可接受的制造缺陷率，以及单板的高工艺可靠性。
可制造性设计是单板工艺设计的主要内容，主要包括元器件工艺性认证、单板工艺路线设计、PCB工艺设计、单板工艺可靠性设计等业务，覆盖产品开发全过程。
1 目的Objective本流程的目的：规范产品/单板可制造性设计过程，明确单板工艺设计活动，对单板工艺设计过程实施有效控制。
本流程是IPD流程直接支撑子流程。
2 适用范围Scope本流程适用于所有产品/单板的可制造性设计。
3 KPI指标 KPI Index4流程图Flow Chart设计建议 环境需求安规需求EMC 需求防护需求可制造性需求（初稿）002环保需求单板清单相关工艺规范PCB 工艺设计规范PCB 设计及工艺设计要求PCB PCB 设计及工艺设计要求查检表查检表工艺仿真结果单板试制方案PCB PCB 单板TR4A TR5检表表PCB BOMTR6量产单板工艺问题受理和解决AME （单板工艺）023市场失效单板工艺分析改进AME （单板工艺）024工艺设计能力提升AME （单板工艺）5 流程说明 Instructions of Process 001通过相关工艺规范和类似产品在我司地加工质量水平，了解公司现有制造工艺能力。
001b可制造性需求已经在《概念阶段确定可制造性需求指南》和《单板可制造性需求基线》中列出了通用的单板可制造性需求，该需求是保证单板可以加工制造的基本要求，拟制新产品可制造性需求时，可以在基线的基础上进行裁减。
新开发的产品可能还有区别于通用单板可制造性需求的其他需求，需要在《工程设计调研与设计建议》文档中分析产品特点，收集相关信息，结合对业界及我司类似产品的可制造性分析，由单板工艺工程师在通用可制造性需求的基础上提出并写入《可制造性需求》文档中。
电脑主板EMC设计指南
第一章認識電腦主機版之架構範例1FIR S T IN T E R N A T IO N A L C O M P U T E R, IN C範例2S o c k e t 370F I R S T IN T E R N A T I O N A L C O M P U T E R, I N C 第二章如何Review線路圖λMother Board(1)認識各個重要元件, such as clock generator, CPU,north bridge, south bridge, super I/O controller,audio, video, Lan controller chip, VRM, LDCM.(2)蒐集各元件的data sheet, 並詳加閱覽.(3)了解其block diagram, and architecture.λ Clock Generator(1)了解各時脈訊號線(clock trace)的出處腳位(pin), 去處, 定義及頻率(2)每一條clock是否有預留RC filter,以利日後方便Tunewaveform.(3)供給的Power 是否有CLC 丌型濾波.(3)一條clock 供給兩個(或以上) device,不可以只給一組RC,必須分別預留,否則會因阻抗匹配問題,難以tune waveform.(4)確定可Support SST function.λExternal I/O port(1)所有Signal 必須預留RC filter.(2)Connector 空Pin 皆下地.(3)Vcc Pin 串L,並de-coupling cap.Power部分(1) 選擇Low ESR 之電容.其它重要Chip(1)Review 供給電源是否有加De-coupling 電容. Review完所有線路,做一張Frequency List,標明Frequency,Trace name,O/P,I/P,Chip,及filter值.如下頁所示REQUENCY LIST FOR BURTONKevin Lin 7/20/98Frequenc y (MHz)Trace name O/P IC/CHIP I/P IC/CHIP Connecto r Filter PS.CPUHCLKCLK GEN CPU 15Ω/5P BXHCLK 440BX 18Ω/5P 66.8/100 DCLKO 440BX CKBF 47Ω/5P DCLKICKBF440BX15Ω/ ? DCLK0~11CKBF DIMM x315Ω/5P DCLK0漏畫48 48M_PIX PIIX4 47Ω/3.9P 48M_SIO SUPER I/O 33Ω/3.9P BXPCLK 440BX 47Ω/5P 33.4 PIXOCLK CLKGENPIIX4 33Ω/5P PICCLK1~5Gold Finger 47Ω/5P PICCLK CPU 27Ω/10P 14.318 OSC_PIX PIIX447Ω/10P OSC_ISAGold Finger47Ω/10P 8.25SYSCLK PIIX4GoldFinger? W/O RC ?BIOS MCLK MGA SGRAM 33Ω/? W/O CAP. 66GCLK22Ω/? W/O CAP. 30 VDCLK ? W/O CAP. OPEN VDOCLK 空PIN OPEN E2PCLK空PIN ? I2CCLK W/O CAP. 14.318X4X4CLK GEN27 X6 X6 MGA CLK GEN : W48C101-04 MGA: MGA G100ACKBF : W40S01-04 SUPER I/O : PC87317NB : 440BX SB: 82371EB-A0_2 (PIIX4)第三章Layout Guideline*振盪器置於緊靠被供給的IC旁.*Clock Generator 應置於M/B的中心位置,使到各chipset 的clock trace不致於太長.*Clock trace 必須最先lay,走最短路徑,避免留在最後lay導致繞一大圈,增加迴路面積或打太多via hole.*每一個via hole 會增加1~3nH的電感量,盡量避免打via,若無法避免,最好控制在2個(含)以下.*Clock trace絕不可靠近或直接通過Internal或External connector.並遠離板邊2cm以上.*Clock trace 以8~12 mil 為宜,若空間允許,當然是越寬越好.(阻抗越低)*Clock trace 盡量走在靠近ground的一層,會有較好的flux cancellation.*振盪器,clock generator切忌置於Internal或External connector旁.*相鄰兩個螺絲孔的距離以不超過最高頻率的λ/20為宜.例如最高頻率100MHz,λ/20為15cm.*若空間足夠,clock trace包地線(guard trace),且地線每隔1~2cm 打through hole 至ground plane.*Trace線避免直角轉彎,可採圓弧或兩段式(兩個45度).*頻率大於1MHz的信號線,filter電容下地採多點下地,減少下地阻抗,小於1MHz,採單點下地,如下圖所示.*電容必須直接下地,避免拉一段距離之後才下地.*IC1至IC2信號線的filter靠近IC1,IC output至I/O port信號線的 filter 靠近I/O port.*Chipset(or IC)的Vcc De-coupling 電容須緊靠Chipset(or IC).*為了減低信號線之間的cross-talk,必須遵循3W法則.W為trace之寬度.在trace兩邊各留1W寬度之空間.*M/B空出來未走線的部份,盡量鋪GND,打through hole至GND plane,越多越好.*振盪器下留GND pad(solid plane)與振盪器之金屬外殼接觸.*為了減低PCB之fringing效應,power plane應比GND plane小.H為power plane與GND plane之間的距離(一般為0.006inch),若L=20H(約3mm),可達到70%的通量邊界,L=100H(約15mm),可達98%之通量邊界.*Connector的pin assignment: 空pin皆下地,GND pin錯開置於Vcc或信號線旁邊.*相鄰兩層之信號線走線方向盡量垂直,以減少crosstalk之機會.*較高頻率之信號線走線盡量避免跨切割斷面,若無法避免,必須在trace兩旁的斷面上連接電容.*Clock trace須注意阻抗匹配,以防止反射現象的產生.*若一條clock trace同時供給數顆IC,其佈線切忌用串聯方式.*適當安排placement,比較Noisy的區域(如clock generator,振盪器)附近,最好有螺絲孔下到機殼.*Through hole不可打得太密集而造成切斷面,否則會使某些信號的return path繞過此區域,加大迴路面積.*為了避免高速信號經由GND plane干擾I/O區域,最好切割一塊獨立的I/O GND,以螺絲孔或connector的彈片接觸機殼,確保乾淨,使 I/O信號的所有filter發揮功用,並以Bead做bridge連回大digital GND, 縮短迴路面積.除了I/O信號以外,避免其他信號跨過此區域.*六層板以上,clock線最好lay在power與GND,或兩層GND 之間,以降低其輻射量.*盡量選用可接受之低壓,低速edge rate之邏輯族元件.*盡量避免使用socket以減低元件trace長度之電感性. Audio部份的Layout Guideline注意事項:1.Analog GND 及Vcc必須切割,Vcc比GND小約3mm.2.Analog GND 與 Digital GND以Bead相通,Bead使用耐大電流的.3.Audio Chip 的所有Vcc Pin以最短路徑加De-coupling Cap.下地.4.Audio Chip擺設的方位必須使到Connector的信號線走最短距離,走線轉角以圓弧或兩段式,不可直角轉彎,並遠離Crystal.5.Connector GND(I/O GND)切割,Bypass下到I/O GND, Connector必須有彈片碰觸機殼,讓I/O GND 保持乾淨,串Bead回Analog GND,使迴圈縮小.6.LC filter越靠近Connector越好,值如上所示.7.Analog與Digital GND切割的溝寬約50~60mil.8.Crystal Lay GND pad接觸外殼.9.若有PCI clock輸入到Audio Chip,依其spec tune成最漂亮的sin波.10.Mic 的Vcc 亦必須加LC filter.第四章機構設計重點一.Notebook.由於Notebook是塑膠外殼,不像Desktop有鐵殼罩住,所以一般會設計鐵片,或以coating,電鍍的方式當主機板的shielding,降低電磁波輻射.如果是鐵片必須注意到以下幾點:1.Low shielding cover:(1)必須長彈片與I/O bracket contact.(2)必須長彈片與各周邊(如CDROM,HD,FD等)contact,且至少兩個彈片以上.(3)長彈片與RAM door上的金屬材質contact.(4)與Top shielding cover的完整contact.2.External connector如VGA, Parallel, Serial, Gameport以鎖六角銅柱的方式固定在I/O bracket 上.其它如K/B, Mouse, Audio Jack, USB, Lan(RJ45)最好選用有長彈片的為宜.3.LCD hinge 與Low shielding cover, Top shieldingcover 的完整contact 很重要,它會影響對LCD noise修改的難易度.4.Touch pad 小板子必須長彈片與Low shielding covercontact5.因主機板size受到限制,必須做Daughter board如DC module, LED board, CPU board, LVDS, Audio board 或其他時,必須做兩個以上的六角銅柱固定並下地.6.Modem card 通常會做鐵罩子,Low (或Top) shieldingcover 必須長彈片與其contact.7.Top shielding cover長彈片與Keyboard contact.8.Internal cable (如HD, FD, IR, Mic, Speaker, Touchpad, LED cable要越短越好,且盡量避免跨越主機板.並以FPC cable 且lay GND 層為最佳.9.LCD shielding cover 與LCD panel 的完整contact.10.LCD cable 以導電布或編織網包裹,以鐵片壓鎖的方式與主機GND導通,會比拉pig tail的方式好.11.LVDS或Panel link的differential 信號線,以twist方式為宜.12.Coating 或電鍍的方式缺點是無法長彈片contact,而優點是在接縫的密合度較佳.第五章Debug及Modify技巧一.在測試 EUT之前,必須具備以下條件:1.已詳閱方塊圖,線路圖,並列出Frequency List,腦海中已記住所有EUT的頻率.2.已準備好底片圖或空板,標示出所有Clock trace.(以紅筆標示)3.確定在BIOS裡面,所有function,如Spread Spectrum, PCISlot, USB controller…等均已開啟.4.EUT之所有Internal, External cable 皆已接上.所有外接Device電源已打開.網路須對傳.二.Full scan 四張圖,分別為垂直低頻(30MHz~300MHz),垂直高頻 (300MHz~1000MHz),水平低頻,水平高頻.三.移除所有External cable,再scan四張圖.比較與前次的差異,若有某些頻率消失或明顯下降,則可判斷這些頻率是屬於Cable emission.四.逐一計算這些頻率是Frequency List當中那些頻率的倍頻,check由那一個Port帶出,並以Probe量出是那一Pin(或那幾Pin)帶出,並記錄下來.五.判斷Noise的種類:(1)有展頻的Noise,頻寬約為5~10MHz,屬於FSB或PCI Bus.(2)無展頻的Noise,頻寬約為1~2MHz,除了FSB,PCI以外的clock.Ps. 因I/O port並無以上clock輸出,若有帶出,一定是在某處被Coupling.須check Layout 圖.(3)Video Noise,屬於R,G,B信號或Frame buffer的Data Bus,可能從VGA port, DFP port,帶出,或感染到其他port帶出.(4)Bass型Noise, 屬於下地不良造成,check I/O shielding 的contact 是否有問題.(5)會跳動的Noise,多為Power線本身帶出,或感染其他線帶出.checkpower 線源頭是否有串Bead或並De-coupling cap.六.解決Cable emission的方法如下:(1)check I/O connector 與機殼(I/O shielding)的contact是否完整,亦即是否有六角螺絲或彈片.有時僅須改善Grounding,無須下其它解,便可解掉問題.(2)K/B, Mouse, Com, Printer port 都是屬於K級的超低頻信號,所使用的RC 或LC低通濾波器,值都可以調到相當大,一般而言,Bead在600 ohm, Cap在1000P以下,都不致使這些Portfunction fail.Ps. 使用Bead無庸置疑一定比R好,因為Bead的阻抗會隨頻率而增加,對於高頻(harmonic)有良好的抑制效果,而R只是固定的值.(3)如果是Vcc受感染, Bead, 電容加多大都不會有問題,唯一要注意的是Bead的耐流須大於Vcc線的實際電流.Ps. 一般的信號線Bead的耐流在300mA即可.(4)VGA port 之R,G,B 屬於Analog信號,經驗值Bead在120 ohm以下,電容在47P以下.在Scope量出的信號,Amplitude須在0.7V+0.1內.(5)DFP 的信號(如圖5-1)是屬於High-speed, Low swing的differential 信號,通常在此加任何元件,很可能造成function fail.5-1一般此部份可修改的地方是在VGA controller 到Transmitter以及Receiver到LCD Panel 的Digital signal(包含1條CLK及24條data line), filter的值因chip的driving能力不同,差異不小,但若能使clock的High, Low time, Data 的Setup time, Hold time及Data Enable Setup time符合LCD panel 的Input timing spec.即可.。
硬件EMC设计规范1_华为内部资料
硬件EMC设计规范1_华为内部资料本规范只简绍EMC的主要原则与结论，为硬件⼯程师们在开发设计中抛砖引⽟。
电磁⼲扰的三要素是⼲扰源、⼲扰传输途径、⼲扰接收器。
EMC 就围绕这些问题进⾏研究。
最基本的⼲扰抑制技术是屏蔽、滤波、接地。
它们主要⽤来切断⼲扰的传输途径。
⼴义的电磁兼容控制技术包括抑制⼲扰源的发射和提⾼⼲扰接收器的敏感度，但已延伸到其他学科领域。
本规范重点在单板的EMC 设计上，附带⼀些必须的EMC 知识及法则。
在印制电路板设计阶段对电磁兼容考虑将减少电路在样机中发⽣电磁⼲扰。
问题的种类包括公共阻抗耦合、串扰、⾼频载流导线产⽣的辐射和通过由互连布线和印制线形成的回路拾取噪声等。
在⾼速逻辑电路⾥，这类问题特别脆弱，原因很多：1、电源与地线的阻抗随频率增加⽽增加，公共阻抗耦合的发⽣⽐较频繁；2、信号频率较⾼，通过寄⽣电容耦合到布线较有效，串扰发⽣更容易；3、信号回路尺⼨与时钟频率及其谐波的波长相⽐拟，辐射更加显著。
4、引起信号线路反射的阻抗不匹配问题。
⼀、总体概念及考虑1、五⼀五规则，即时钟频率到5MHz 或脉冲上升时间⼩于5ns，则PCB 板须采⽤多层板。
2、不同电源平⾯不能重叠。
3、公共阻抗耦合问题。
模型：VN1＝I2ZG 为电源I2 流经地平⾯阻抗ZG ⽽在1 号电路感应的噪声电压。
由于地平⾯电流可能由多个源产⽣，感应噪声可能⾼过模电的灵敏度或数电的抗扰度。
解决办法：①模拟与数字电路应有各⾃的回路，最后单点接地；②电源线与回线越宽越好；③缩短印制线长度；④电源分配系统去耦。
4、减⼩环路⾯积及两环路的交链⾯积。
5、⼀个重要思想是：PCB 上的EMC 主要取决于直流电源线的Z 0C→∞，好的滤波，L→0，减⼩发射及敏感。
如果< 0.1Ω极好。
⼆、布局下⾯是电路板布局准则：1、晶振尽可能靠近处理器2、模拟电路与数字电路占不同的区域3、⾼频放在PCB 板的边缘，并逐层排列4、⽤地填充空着的区域三、布线1、电源线与回线尽可能靠近，最好的⽅法各⾛⼀⾯。
华为的EMC基础知识课程
华为的EMC基础知识课程《华为EMC基础知识》课程分三个章节,分别从概念,基本理论和系统方面简单介绍了EMC 的基本概念、标准、测试内容,产品认证和电磁兼容的基本理论,最后介绍了系统安装和维护中的EMC 问题。
本教材主要针对系统使用维护类工程师,对EMC 设计方面的内面较少,仅需了解即可。
《华为EMC基础知识》课程第1章序论1.1 电磁兼容概述1.2 电磁兼容性的基本概念1.2.1 电磁骚扰与电磁干扰1.2.2 电磁兼容性(EMC-Electromagnetic Compatibility) 1.2.3 电磁兼容常用名词术语1.3 电磁干扰1.3.1 电磁干扰三要素1.3.2 电磁兼容研究的主要内容1.4 基本的电磁兼容控制技术1.5 电磁兼容标准1.5.1 电磁兼容标准的制订1.5.2 EMC标准拟订的理论基础1.5.3 电磁兼容标准的分类1.5.4 产品的电磁兼容标准遵循原则1.6 电磁兼容测试技术简介1.6.1 概述1.6.2 EMC测试项目1.6.3 电磁发射1.6.4 抗扰性EMS1.7 EMC测试结果的评价1.8 产品EMC设计的重要性1.9 产品的认证小结:思考题:第2章 EMC基础理论2.1 电磁骚扰的耦合机理2.1.1 引言2.1.2 电磁骚扰的常用单位2.1.3 传导干扰2.1.4 辐射干扰2.2 电磁干扰的模式2.2.1 共模干扰与差模干扰2.2.2 PCB的辐射与线缆的辐射2.3 电磁屏蔽理论2.3.1 屏蔽效能的感念2.3.2 屏蔽体上孔缝的影响2.4 电缆的屏蔽设计2.5 接地设计2.5.1 接地的概念2.5.2 接地的种类2.6 滤波设计2.6.1 滤波电路的基本概念2.6.2 电源EMI滤波器小结:思考题:第3章系统安装和维护3.1 系统安装的EMC要求3.1.1 概述3.1.2 系统环境要求3.1.3 防整机安装3.1.4 电缆布线要求3.2 系统维护3.2.1 防静电要求3.2.2 系统检视3.2.3 系统干扰问题的处理。
【优质文档】emc设计指导书-优秀word范文 (13页)
本文部分内容来自网络整理，本司不为其真实性负责，如有异议或侵权请及时联系，本司将立即删除！== 本文为word格式，下载后可方便编辑和修改！ ==emc设计指导书篇一：华为EMC设计指导书(一)篇二：结构EMC设计指导书结构EMC设计指导书深圳市易安技术开发有限公司版权所有翻录必究目录1. 目的 .................................................................. ..................................................................... .... 5 2. 范围 .................................................................. .............................................(来自:WWw. : emc设计指导书 )............................ 5 3. 定义 .................................................................. ..................................................................... .... 5 4. 引用标准和参考资料 .................................................................. ............................................. 5 5. 缝隙屏蔽设计 .................................................................. (6)5.1. 5.2. 5.2.1. 5.2.2. 5.3. 5.3.1. 5.4. 5.4.1. 5.4.2. 5.4.3.基本原则 .................................................................. ......................................... 6 影响缝隙屏蔽的主要因素 .................................................................. ............. 6 紧固点直接连接方式 .................................................................. ..................... 6 屏蔽材料连接 .................................................................. ................................. 7 缝隙屏蔽设计 .................................................................. ................................. 7 紧固点直接连接 .................................................................. ............................. 7 安装屏蔽材料 .................................................................. ................................. 9 屏蔽材料的选用 .................................................................. ............................. 9 屏蔽材料的安装 .................................................................. ........................... 10 屏蔽材料的压缩量 .................................................................. .. (10)6. 进出线缆屏蔽设计 .................................................................. .. (11)6.1. 6.2. 6.2.1. 6.2.2. 6.2.3. 6.2.4. 6.2.5.基本原则 .................................................................. ....................................... 11 屏蔽电缆处理方式 .................................................................. ....................... 11 屏蔽连接器转接 .................................................................. ........................... 12 EMI滤波器转接 .................................................................. .......................... 13 金属丝网夹线方式 .................................................................. ....................... 14 专用簧片夹线 .................................................................. ............................... 17 安装槽夹线 .................................................................. .. (18)7. 通风孔屏蔽设计 .................................................................. (19)7.1. 7.2. 7.3.覆盖金属丝网 ................................................................................................. 20 穿孔金属板 .................................................................. ................................... 21 截至波导通风板 .................................................................. (23)8. 塑胶件屏蔽设计 .................................................................. (24)8.1. 8.2. 8.2.1. 8.2.2.导电漆 .................................................................. ........................................... 25 塑胶件屏蔽常用结构形式 .................................................................. ........... 26 屏蔽方式 .................................................................. ....................................... 26 盒体与盒盖之间的接缝处理 .................................................................. . (26)9. PCB局部屏蔽设计 .................................................................. . (26)9.1. 9.2. 9.2.1.10.选用材料 .................................................................. ....................................... 27 结构形式 .................................................................. ....................................... 27 盒体式 .................................................................. . (27)屏蔽材料选用 .................................................................. ............................................... 28 10.1. 10.2.选用原则 .................................................................. ....................................... 28 各种优选屏蔽材料的应用 .................................................................. .. (29)11. 附录 .................................................................. (33)11.1.屏蔽材料选用简易对照表 .................................................................. .. (33)结构EMC设计指导书【摘要】：【关键词】：【定义与缩略语】：EMC：Electromagnetic Compatibility 电磁兼容性 RE：Radiated Emission 辐射发射 ESD：Electrostatic discharge 静电放电1. 目的本指导书旨在指导公司结构造型的EMC设计，将EMC设计要素在结构机电中予以实现。