模拟电子和数字电子电子信息专业英语文章

Analog and Digital（模拟电子和数字电子）:Analog and DigitalIdeal Operational Amplifiers and Practical LimitationsIn order to discuss the ideal parameters of operational amplifiers, we must first define the terms, and then go on to describe what we regard as the ideal values for those terms. At first sight, the specification sheet for an operational amplifier seems to list a large number of values, some in strange units, some interrelated, and often confusing to those unfamiliar with the subject. The approach to such a situation is to be methodical, and take the necessary time to read and understand each definition in the order that it is listed. Without a real appreciation of what each means, the designer is doomed to failure. The objective is to be able to design a circuit from the basis of the published data, and know that it will function as predicted when the prototype is constructed.1It is all too easy with linear circuits, which appear relatively simple when compared with today‟s complex logic arrangements, to ignore detailed performance parameters which can drastically reduce the expected performance.Let us take a very simple but striking example. Consider a requirement for an amplifier having a voltage gain of 10 at 50 kHz driving into a 10 k load. A common low-cost, internally frequency-compensated op amp is chosen; it has the required bandwidth at a closed-loop gain of 10, and it would seem to meet the bill. The device is connected, and it is found to have the correct gain. But it will only produce a few volts output swing when the data clearly shows that the output should be capable of driving to within two or three volts of the supply rails. The designer has forgotten that the maximum output voltage swing is severely limited by frequency, and that the maximum low-frequency output swing becomes limited at about 10 kHz. Of course, the information is in fact on the data sheet, but its relevance has not been appreciated. This sort of problem occurs regularly for the inexperienced designer. So the moral is clear: always take the necessary time to write down the full operating requirements before attempting a design. Attention to the detail of the performance specification will always be beneficial. It is suggested the following list of performance details be considered:1. Closed loop gain accuracy, stability with temperature, time and supply voltage2. Power supply requirements, source and load impedances, power dissipation3. Input error voltages and bias currents. Input and output resistance, drift withtime and temperature4. Frequency response, phase shift, output swing, transient response, slew rate,frequency stability, capacitive load driving, overload recovery5. Linearity, distortion and noise6. Input, output or supply protection required. Input voltage range,common-mode rejection7. External offset trimming requirementNot all of these terms will be relevant, but it is useful to remember that it is better to consider them initially rather than to be forced into retrospective modifications.All parameters are subject to wide variationsNever forget this fact. How many times has a circuit been designed using typical values, only to find that the circuit does not work because the device used is not typical? The above statement thus poses a tricky question: when should typical values and when should worst-case values be used in the design? This is where the judgment of the experienced designer must be brought to bear. Clearly, if certain performance requirements are mandatory, then worst-case values must be used. In many cases, however, the desirability of a certain defined performance will be a compromise between ease of implementation, degree of importance, and economic considerations. Do not over-specify or over-designIn the end, we are all controlled by cost, and it is really pointless taking a sledgehammer to crack a nut, Simplicity is of the essence since the low parts count implementation is invariably cheaper and more reliable.As an example of this judgment about worst-case design, consider a low-gain DC transducer amplifier required to amplify 10 mV from a voltage source to produce an output of .l V with an accuracy of ±1% over a temperature range of 0~70︒C. Notice that the specification calls for an accuracy of ±1%. This implies that the output should be 1 V ±10 mV from 0 ~ 70︒C. The first step is, of course, to consider our list above, and decide which of the many parameters are relevant. Two of the most important to this (very limited) specification are offset voltage drift and gain stability with temperature. We will assume that all initial errors are negligible (rarely the case in practice). The experienced designer would know that most op amps have a very large open-loop gain, usually very much greater than 10000. A closed-loop gain change of ±1% implies that the loop gain (as explained later) should change by less than ±100% for a closed-loop gain of 100. This is clearly so easily fulfilled that the designer knows immediately that he can use typical open-loop gain values in his calculations. However, offset voltage drift is another matter. Many op amp specifications include only typical values for offset voltage drift; this may well be in the order of 5 μV/︒C, with an unquoted maximum for any device of 30 μV/︒C. If by chance we use a device which has this worst-case drift, then the amplifier error could be 30×70=2100 μV=2.1 mV over temperature, which is a significant proportion of our total allowable error from all sources.Here is a case, then, where one can be confident that the typical value of open-loop gain can be used, but where the maximum value of drift may well cause significant errors. This sort of judgment is essential in careful design, and great care is required in interpreting manufacturers‟ data. This consideration must be ext ended toall the details listed above apart from the fact that worst-case values are often not quoted. It is often found that values given are not 100% tested. Statistical testing is employed which, for example, guarantees that 90% of all devices fall within the range specified. It could be very inconvenient for the user who relies on the specified performance and then finds that he has several of the …other‟ 10% actually plugged into his circuit.Data Registers and CountersData registerThe simplest type of register is a data register, which is used for the temporary storage of a “word” of data. In its simplest form, it consists of a set of N D flip-flops, all sharing a common clock. All of the digits in the N bit data word are connected to the data register by an N-line “data bus”. Figure 1.1 shows a 4 bit data register, implemented with four D flip-flops. The data register is said to be a synchronous device, because all the flip-flops change state at the same time.Shift registersAnother common form of register used in computers and in many other types of logic circuits is a shift register. It is simply a set of flip-flops (usually D latches or RS flip-flops) connected together so that the output of one becomes the input of the next, and so on in series. It is called a shift register because the data is shifted through the register by one bit position on each clock pulse. Figure 1.2 shows a 4 bit shift register, implemented with D flip-flops.On the leading edge of the first clock pulse, the signal on the DATA input is latched in the first flip-flop. On the leading edge of the next clock pulse, the contents of the first flip-flop is stored in the second flip-flop, and the signal which is present at the DATA input is stored in the first flip-flop, etc. Because the data is entered one bit at a time, this called a serial-in shift register. Since there is only one output, and data leaves the shift register one bit at a time, then it is also a serial out shift register. (Shift registers are named by their method of input and output; either serial or parallel.) Parallel input can be provided through the use of the preset and clear inputs to the flip-flop. The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register. Parallel output can be obtained from the outputs of each flip-flop as shown in Figure 1.3.Communication between a computer and a peripheral device is usually done serially, while computation in the computer itself is usually performed with parallel logic circuitry. A shift register can be used to convert information from serial form to parallel form, and vice versa. Many different kinds of shift registers are available, depending upon the degree of sophistication required.Counters — weighted coding of binary numbersIn a sense, a shift register can be considered a counter based on the unary numbersystem. Unfortunately, a unary counter would require a flip-flop for each number in the counting range. A binary weighted counter, however, requires only flip-flops to count to N. A simple binary weighted counter can be made using T flip-flops. The flip-flops are attached to each other in a way so that the output of one acts as the clock for the next, and so on. In this case, the position of the flip-flop in the chain determines its weight; i.e., for a binary counter, the “power of two” it corresponds to.A 3-bit (modulo 8) binary counter could be configured with T flip-flops as shown in Figure 1.4. A timing diagram corresponding to this circuit is shown in Figure 1.5.Note that a set of lights attached to O0, O1, O2 would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse. As many T flip-flops as required could be combined to make a counter with a large number of digits.Note that in this counter, each flip-flops changes state on the falling edge of the pulse from the previous flip-flop. Therefore there will be a slight time delay, due to the propagation delay of the flip-flops between the time one flip-flop changes state and the time the next one changes state, i.e., the change of state ripples through the counter, and these counters are therefore called ripple counters. As in the case of a ripple carry adder, the propagation delay can become significant for large counters.It is possible to make, or buy in a single chip, counters which will count up, count down, and which can be preset to any desired number. Counters can also be constructed which count in BCD and base 12 or any other number base.A count down counter can be made by connecting the Q output to the clock input in the previous counter. By the use of preset and clear inputs, and by gating the output of each T flip- flop with another logic level using AND gates (say logic 0 for counting down, logic 1 for counting up), then a presetable up-down binary counter can be constructed. Figure 1.6 shows an up-down counter, without preset or clear.Synchronous countersThe counters shown previously have been “asynchronous counters”; so called because the flip-flops do not all change state at the same time, but change as a result of a previous output. The output of one flip-flop is the input to the next; the state changes consequently “ripple through” the flip-flops, requiring a time proportional to the length of the counter. It is possible to design synchronous counters, using JK flip-flops, where all flip-flops change state at the same time; i.e., the clock pulse is presented to each JK flip-flop at the same time. This can be easily done by nothing that, for a binary counter, any given digit changes its value (from 1 to 0 or from 0 to 1) whenever all the previous digits have a value of 1. A count down timer can be made by connecting the Q output to the J and K, through the AND gates. Preset and clear could also be provided, and the counter could be made “programmable” as in the previous case.The timing diagram is similar to that shown for the asynchronous (ripple) counters, except that the ripple time is now zero; all counters clock at the same time. It is common for synchronous counters to trigger on the positive edge of the clock,rather than the trailing edge.Nature of Phase LockThe phase detector compares the phase of a periodic input signal against the phase of the VCO. Output of PD is a measure of the phase difference between its two inputs. The difference voltage is then filtered by the loop filter and applied to the VCO. Control voltage on the VCO changes the frequency in a direction that reduces the phase difference between the input signal and the local oscillator.When the loop is locked, the control voltage is such that the frequency of the VCO is exactly equal to the average frequency of the input signal. For each cycle of input there is one, and only one, cycle of oscillator output. One obvious application of phase lock is in automatic frequency control (AFC). Perfect frequency control can be achieved by this method, whereas conventional AFC techniques necessarily entail some frequency error.To maintain the control voltage needed for lock it is generally necessary to have a nonzero output from the phase detector. Consequently, the loop operates with some phase error present. As a practical matter, however, this error tends to be small in a well-designed loop.A slightly different explanation may provide a better understanding of loop operation. Let us suppose that the incoming signal carries information in its phase or frequency; this signal is inevitably corrupted by additive noise. The task of a phase lock receiver is to reproduce the original signal while removing as much of the noise as possible.To reproduce the signal the receiver makes use of a local oscillator whose frequency is very close to that expected in the signal. Local oscillator and incoming signal waveforms are compared with one another by a phase detector whose error output indicates instantaneous phase difference. To suppress noise the error is averaged over some length of time, and the average is used to establish frequency of the oscillator.If the original signal is well behaved (stable in frequency), the local oscillator will need very little information to be able to track, and that information can be obtained by averaging for a long period of time, thereby eliminating noise that could be very large. The input to the loop is a noisy signal, whereas the output of the VCO is a cleaned-up version of the input. It is reasonable, therefore, to consider the loop as a kind of filter that passes signals and rejects noise.Two important characteristics of the filter are that the bandwidth can be very small and that the filter automatically tracks the signal frequency. These features, automatic tracking and narrow bandwidth, account for the major uses of phase lock receivers. Narrow bandwidth is capable of rejecting large amounts of noise; it is not at all unusual for a PLL to recover a signal deeply embedded in noise.History and applicationAn early description of phase lock was published by de Bellescize in 1932 and treated the synchronous reception of radio signals. Superheterodyne receivers hadcome into use during the 1920s, but there was a continual search for a simpler technique; one approach investigated was the synchronous, or homodyne, receiver. In essence, this receiver consists of nothing but a local oscillator, a mixer, and an audio amplifier. To operate, the oscillator must be adjusted to exactly the same frequency as the carrier of the incoming signal, which is then converted to an intermediate frequency of exactly 0 Hz. Output of the mixer contains demodulated information that is carried as sidebands by the signal. Interference will not be synchronous with the local oscillator, and therefore mixer output caused by an interfering signal is a beat-note that can be suppressed by audio filtering.Correct tuning of the local oscillator is essential to synchronous reception; any frequency error whatsoever will hopelessly garble the information. Furthermore, phase of the local oscillator must agree, within a fairly small fraction of a cycle, with the received carrier phase. In other words, the local oscillator must be phase locked to the incoming signal.For various reasons the simple synchronous receiver has never been used extensively. Present-day phase lock receivers almost invariably use the superheterodyne principle and tend to be highly complex. One of their most important applications is in the reception of the very weak signals from distant spacecraft. The first widespread use of phase lock was in the synchronization of horizontal and vertical scan in television receivers. The start of each line and the start of each interlaced half-frame of a television picture are signaled by a pulse transmitted with the video information. As a very crude approach to reconstructing a scan raster on the TV tube, these pulses can be stripped off and individually utilized to trigger a pair of single sweep generators.A slightly more sophisticated approach uses a pair of free-running relaxation oscillators to drive the sweep generators. In this way sweep is present even if synchronization is absent.Free-running frequencies of the oscillators are set slightly below the horizontal and vertical pulse rates, and the stripped pulses are used to trigger the oscillators prematurely and thus to synchronize them to the line and half-frame rates (half-frame because United States television interlaces the lines on alternate vertical scans).In the absence of noise this scheme can provide good synchronization and is entirely adequate. Unfortunately, noise is rarely absent, and any triggering circuit is particularly susceptible to it. As an extreme, triggered scan will completely fail at a signal-to-noise ratio that still provides a recognizable, though inferior, picture.Under less extreme conditions noise causes starting-time jitter and occasional misfiring far out of phase. Horizontal jitter reduces horizontal resolution and causes vertical lines to have a ragged appearance. Severe horizontal misfiring usually causes a narrow horizontal black streak to appear.Vertical jitter causes an apparent vertical movement of the picture. Also, the interlaced lines of successive half-frames would so move with respect to one another that further picture degradation would result.Noise fluctuation can be vastly reduced by phase locking the two oscillators to the stripped sync pulses. Instead of triggering on each pulse a phase-lock techniqueexamines the relative phase between each oscillator and many of its sync pulses and adjusts oscillator frequency so that the average phase discrepancy is small.Because it looks at many pulses, a phase lock synchronizer is not confused by occasional large noise pulses that disrupt a triggered synchronizer. The flywheel synchronizers in present day TV receivers are really phase-locked loops. The name “flywheel” is used because the circuit is able to coast through periods of increased noise or weak signal. Substantial improvement in synchronizing performance is obtained by phase-lock.In a color television receiver, the color burst is synchronized by a phase-lock loop.Space flight requirements inspired intensive application of phase lock methods. Space use of phase lock began with the launching of the first American artificial satellites. These vehicles carried low-power (10 mW) CW transmitters; received signals were correspondingly weak. Because of Doppler shift and drift of the transmitting oscillator, there was considerable uncertainty about the exact frequency of the received signal. At the 108 MHz frequency originally used, the Doppler shift could range over a ±3 kHz interval.With an ordinary, fixed-tuned receiver, bandwidth would therefore have to be at least 6 kHz, if not more. However, the signal itself occupies a very narrow spectrum and can be contained in something like a 6 Hz bandwidth.Noise power in the receiver is directly proportional to bandwidth. Therefore, if conventional techniques were used, a noise penalty of 1000 times (30 dB) would have to be accepted. The numbers have become even more spectacular as technology has progressed; transmission frequencies have moved up to S-band, making the Doppler range some ±75 kHz, whereas receiver bandwidths as small as 3 Hz have been achieved. The penalty for conventional techniques would thus be about 47 dB. Such penalties are intolerable and that is why narrowband, phase-locked, tracking receivers are used.Noise can be rejected by a narrowband filter, but if the filter is fixed the signal almost never will be within the pass-band. For a narrow filter to be usable it must be capable of tracking the signal. A phase-locked loop is capable of providing both the narrow bandwidth and the tracking that are needed. Moreover, extremely narrow bandwidths can be conveniently obtained (3 to 1000 Hz are typical for space applications); if necessary, bandwidth is easily changed.For a Doppler signal the information needed to determine vehicle velocity is the Doppler shift. A phase-lock receiver is well adapted to Doppler recovery, for it has no frequency error when locked.Other applicationsThe following applications, further discussed elsewhere in the book, represent some of the current uses of phase-lock.1. One method of tracking moving vehicles involves transmitting a coherentsignal to the vehicle, offsetting the signal frequency, and re-transmitting back to the ground. The coherent transponder in the vehicle must operate so that the input and output frequencies are exactly related in the ratio m/n, where m and nare integers. Phase-lock techniques are often used to establish coherence.2. A phase-locked loop can be used as a frequency demodulator, in which it hassuperior performance to a conventional discriminator.3. Noisy oscillators can be enclosed in a loop and locked to a clean signal. If theloop has a wide bandwidth, the oscillator tracks out its own noise and its output is greatly cleaned up.4. Frequency multipliers and dividers can be built by using PLLs.5. Synchronization of digital transmission is typically obtained by phase-lockmethods.6. Frequency synthesizers are conveniently built by phase-lock loops.中文翻译：模拟电子和数字电子理想运算放大器和实际限制为了讨论运算放大器的理想参数，我们必须首先定义一些指标项，然后对这些指标项讲述我们所认为的理想值。