06-信息工程学院外文翻译(AD9850手册的 第8~13页)
AD9850中文资料
VC C4
2
U2
VCC CLK GND
16MHz
VCC
36 81
U21
DDS_D0 DDS_D1
4 3
D0
R
DDS_D2 DDS_D3
2 1
D A D1
D2
DA
DDS_D4 28 DDS_D5 27 DDS_D6 26 DDS_D7 25
W_CLK 7
FQ_UP
8
D3
IOUT
D4
D5
dds 芯片复位
A,@R1;
写入 5 个频率字
@DPTR,A
R1;
R0,PROC_9850;
A,#00H
DPTR,#FQ_UP ;装载频率字并启动转换
@DPTR,A ;
J1，J4 为总线插槽，具体管脚定义如下表：
符号
定义
引脚
功能说明
D0~D7
数据总线
4~11 D0～D7 /A0～A7 总线分时复用，非扩展
方式下可作为位控
A0~A7
低 8 位地址线 12~19
CS0~CS7
输 入 输 出 地 址 23~30 由处理器板中的 CPLD 对数据存储地址空间
段选择信号
中的高位地址线译码产生，占据最高的
图 0341-6 模块器件分布图
U2 为有源晶振；
J2 为电源，从上往下依次为：VCC，GND；
U21 为 AD9850；
J6 为电源插座；
J5 为 CPLD 下载编程接口；从左向右依次为：VCC，GND，TCK，TDO，TDI，TMS；
J3 信号输出端。从上到下依次为： SIN_OUT，GND，BUS_CLK，GND；
AD9859数据手册中文翻译
AD9859数据手册特征400 msps内部时钟速度集成10位DAC32位调谐字相位噪声≤–120 dBc/Hz@1 kHz偏移量（DAC输出）卓越的动态性能160兆赫（±100千赫偏移）输出时>75分贝SFDR串行I/O控制1.8V电源软硬件控制电源关闭48铅TQFP/EP包支持大多数输入电平为5 V的数字输入PLL REFCLK乘法器（4×到20×）内部振荡器；可由单晶体驱动相位调制能力多芯片同步简介AD9859是一种直接数字合成器（DDS），具有一个10位DAC，工作速度高达400 msps。
AD9859采用先进的DDS技术，结合内部高速、高性能的DAC，形成一个数字可编程、完整的高频合成器，能够在高达200兆赫的频率灵活模拟输出正弦波形。
AD9859提供快速跳频和微调解决方案（32位频率调谐字）。
频率调节控制字通过串行I/O端口加载到AD9859中。
AD9859规定在-40°C至+105°C的延伸工业温度范围内运行。
AD9859-电气规范除非另有说明，否则，AVDD、DVDD=1.8 V±5%、DVDDU I/O=3.3 V±5%、RSET=3.92 kΩ、外部参考时钟频率=20 MHz，且在启用了20×参考时钟乘法器情况下。
DAC输出必须引用到AVDD，而不是AGND。
引脚功能描述40 SCLK I 该引脚用作I/O操作的串行数据时钟。
41 SDIO I/O 当将I/O端口作为3线串行端口操作时，此引脚仅用作串行数据输入。
当作为2线串行端口操作时，此插脚是双向串行数据插脚。
43 DVDD_I/O I 数字电源（仅适用于I/O单元，3.3 V）。
44 SYNC_IN I 用于同步多个AD9859S的输入信号。
此输入连接到主AD9859的同步时钟输出。
45 SYNC_CLK O 时钟输出引脚用作外部硬件的同步器。
信息科学与电子工程专业英语 全文译文
Unit 1 电子学：模拟和数字Unit 1-1第一部分：理想运算放大器和实际限制为了讨论运算放大器的理想参数，我们必须首先定义一些指标项，然后对这些指标项讲述我们所认为的理想值。
第一眼看运算放大器的性能指标表，感觉好像列出了大量的数值，有些是陌生的单位，有些是相关的，经常使那些对运放不熟悉的人感到迷惑。
对于这种情况我们的方法是花上必要的时间有系统的按照列出的次序阅读并理解每一个定义。
如果没有对每一项性能指标有一个真正的评价，设计人员必将失败。
目标是能够依据公布的数据设计电路，并确认构建的样机将具有预计的功能。
对于线性电路而言，它们与现在的复杂逻辑电路结构相比看起来较为简单，（因而在设计中）太容易忽视具体的性能参数了，而这些参数可极大地削弱预期性能。
现在让我们来看一个简单但很引人注意的例子。
考虑对于一个在50kHz频率上电压增益为10的放大器驱动10k 负载时的要求。
选择一个普通的带有内部频率补偿的低价运放，它在闭环增益为10时具有所要求的带宽，并且看起来满足了价格要求。
器件连接后，发现有正确地增益。
但是它只能产生几伏的电压变化范围，然而数据却清楚地显示输出应该能驱动达到电源电压范围以内2到3伏。
设计人员忽视了最大输出电压变化范围是受频率严格限制的，而且最大低频输出变化范围大约在10 kHz受到限制。
当然，事实上这个信息也在数据表上，但是它的实用性并没有受到重视。
这种问题经常发生在那些缺乏经验的设计人员身上。
所以这个例子的寓意十分明显：在开始设计之前总要花上必要的时间来描写全部的工作要求。
关注性能指标的详情总是有益的。
建议下面列出的具体的性能指标应该考虑：1. 在温度，时间和供给电压下的闭环增益的精确性和稳定性2. 电源要求，电源和负载阻抗，功率消耗3. 输入误差电压和偏置电流，输入输出电阻，随着时间和温度的漂移4. 频率响应，相位偏移，输出变化范围，瞬态响应，电压转换速率，频率稳定性，电容性负载驱动，过载恢复5. 线性，失真和噪声6. 输入，输出或电源保护要求，输入电压范围，共模抑制7. 外部补偿调整要求不是所有的指标项都是有关的，但要记住最初就考虑它们会更好，而不要被迫返工。
信息科学与电子工程专业英语翻译(第9、11单元)
Unit 9 数字信号和信号处理Unit 9-1第一部分：数字信号处理数字信号处理（DSP）是研究数字表示的信号以及这些信号的处理方法。
数字信号处理和模拟信号处理是信号处理的子领域。
数字信号处理包括音频及语音信号处理、声纳和雷达信号处理、传感器阵列处理、谱估计、统计信号处理、图像处理、通信信号处理、生物医学信号处理等子领域。
数字信号处理的目标通常是测量连续的真实世界的模拟信号或对其滤波，因此，第一步常常是使用模数转换器将信号从模拟形式转换成数字形式。
通常，要求的输出信号为另一个模拟输出信号，这就需要数模转换器。
数字信号处理的算法有时通过使用专用计算机来实现，它们（专用计算机）利用被称为数字信号处理器的专用微处理器（简称DSP）。
这些数字信号处理器实时处理信号，通常是针对具体目的而设计的专用集成电路（ASIC）。
当灵活性和快速开发比大批量生产的成本更重要时，DSP算法也可以用现场可编程门阵列来实现。
数字信号处理域在数字信号处理中，工程师通常在下面几个域的一个域中来研究数字信号：时域（一维信号），空域（多维信号），频域，自相关域以及小波域。
他们按照某些依据来猜测（或试验不同的可能性）那一个域能够最好地表示信号的本质特性来选择在其中进行信号处理的域。
从测量设备得到的样本序列产生（信号的）时域或空域表示，而离散Fourier变换则产生频域表示即频谱。
自相关定义为信号与其自身经过时间或空间间隔变化后的互相关。
信号采样随着计算机应用的增长，数字信号处理的使用和需求日益增多。
为了能够在计算机上使用模拟信号，必须使用模数转换器（ADC）对其进行数字化。
采样通常分两步实现：离散化和量化。
在离散化阶段，信号空间被分割为相等的区间，用相应区间的代表性信号值代替信号本身。
在量化阶段，用有限集中的值来近似代表性的信号值。
为了能够正确地重建被采样的模拟信号，必须满足奈奎斯特-香农采样定理。
定理规定：采样频率必须大于两倍的信号带宽。
AD9850数据手册
模拟器件 COMS 工艺，125MHZ 完整的DDS 频率合成器特点125M 时钟频率片内高性能DAC 转换器和高速比较器 DAC SFDR > 50 dB @ 40 MHz AOUT 32位频率控制字简单的控制接口：串行或并行装载模式可进行相位调节3.3V 或5V 单电源供电低功耗：380 mW @ 125 MHz (5 V)155 mW @ 110 MHz (3.3 V)省电模式超小型28引脚SSOP 封装 应用频率/相位——方便的正弦波合成 针对数字通信的时钟恢复和锁存电路 数控ADC 编码发生器 灵活的本机振荡器应用概述AD9850是一款高度集成的设备，采用先进的DDS 技术，结合内部高速，高性能的D / A 转换器和比较器，以构成一个完整的，数字可编程频率合成器和时钟发生器。
当连接到一个准确的时钟源时，AD9850产生一个频谱纯净，频率/相位可编程的模拟输出正弦波。
这个正弦波可以直接使用作为频率源，或者它可以被转变为方波作为精准时钟发生器使用。
AD9850先进的高速DDS 内核提供了一个32位的频率调谐字，这使得其在外部125MHZ 参考时钟的输入下，分辨率可达0.0291HZ 。
AD9850的电路架构使得其产生的最高输出频率为其参考的基准时钟频率的一半（或62.5兆MHZ ），而且其输出频率是数控可变的，速率高达72.310 次每秒。
该器件还提供了5位的相位控制字，从而使其输出信号的相位该变量可以为180°，90°，45°，22.5°，11.25°，以及它们的任意组合。
AD9850还包含一个高速比较器，该比较器可以输入经过滤波（外部）的片内DAC 产生的信号以生成一个低抖动方波输出。
这使得该芯片可以作为精准的时钟信号源。
AD9850的频率调谐，控制和相位调制字是通过一个并行字节或方式载入到芯片内部的。
并行载入格式由五个8位的控制字组成。
AD9850 datasheet 数据手册
REV.EInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.aCMOS, 125 MHzComplete DDS SynthesizerAD9850FUNCTIONAL BLOCK DIAGRAMCLOCK OUTOUTSETREF CLOCK IN MASTER RESETFREQUENCY, PHASE, AND CONTROLDATA INPUTGENERAL DESCRIPTIONThe AD9850 is a highly integrated device that uses advanced DDS technology coupled with an internal high speed, high performance, D/A converter and comparator, to form a com-plete digitally programmable frequency synthesizer and clock generator function. When referenced to an accurate clock source, the AD9850 generates a spectrally pure, frequency/phase-programmable, analog output sine wave. This sine wave can be used directly as a frequency source or converted to a square wave for agile-clock generator applications. The AD9850’s innovative high speed DDS core provides a 32-bit frequency tuning word, which results in an output tuning resolution of 0.0291 Hz, for a 125 MHz reference clock input. TheAD9850’s circuit architecture allows the generation of output frequencies of up to one-half the reference clock frequency (or 62.5 MHz), and the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new frequencies per second. The device also provides five bits of digitallycontrolled phase modulation, which enables phase shifting of its output in increments of 180°, 90°, 45°, 22.5°, 11.25° and anycombination thereof. The AD9850 also contains a high speed comparator that can be configured to accept the (externally)filtered output of the DAC to generate a low jitter square wave output. This facilitates the device’s use as an agile clock gen-erator function.The frequency tuning, control, and phase modulation words are loaded into the AD9850 via a parallel byte or serial loading format. The parallel load format consists of five iterative loads of an 8-bit control word (byte). The first byte controls phase modulation, power-down enable, and loading format; bytes 2–5comprise the 32-bit frequency tuning word. Serial loading is accomplished via a 40-bit serial data stream on a single pin. The AD9850 Complete-DDS uses advanced CMOS technology to provide this breakthrough level of functionality and performance on just 155 mW of power dissipation (+3.3 V supply).The AD9850 is available in a space saving 28-lead SSOP, sur-face mount package. It is specified to operate over the extended industrial temperature range of –40°C to +85°C.FEATURES125 MHz Clock RateOn-Chip High Performance DAC and High Speed ComparatorDAC SFDR > 50 dB @ 40MHz A OUT 32-Bit Frequency Tuning WordSimplified Control Interface:Parallel Byte or Serial Loading FormatPhase Modulation Capability+3.3 V or +5 V Single Supply Operation Low Power:380 mW @ 125 MHz (+5 V)155 mW @ 110 MHz (+3.3 V)Power-Down FunctionUltrasmall 28-Lead SSOP PackagingAPPLICATIONSFrequency/Phase–Agile Sine-Wave Synthesis Clock Recovery and Locking Circuitry for Digital CommunicationsDigitally Controlled ADC Encode Generator Agile Local Oscillator ApplicationsOne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 1999AD9850BRS ParameterTemp Test LevelMin Typ MaxUnitsCLOCK INPUT CHARACTERISTICS Frequency Range +5 V Supply FullIV 1125MHz +3.3 V SupplyFull IV 1110MHz Pulsewidth High/Low +5 V Supply +25°C IV 3.2ns +3.3 V Supply +25°CIV4.1nsDAC OUTPUT CHARACTERISTICS Full-Scale Output Current R SET = 3.9 k Ω+25°C V 10.24mA R SET = 1.95 k Ω+25°C V 20.48mA Gain Error+25°C I –10+10% FS Gain Temperature Coefficient Full V 150ppm/°C Output Offset+25°C I 10µA Output Offset Temperature Coefficient Full V 50nA/°C Differential Nonlinearity +25°C I 0.50.75LSB Integral Nonlinearity+25°C I 0.51LSB Output Slew Rate (50Ω, 2 pF Load)+25°C V 400V/µs Output Impedance +25°C IV 50120k ΩOutput Capacitance +25°C IV 8pF Voltage Compliance+25°C I 1.5V Spurious-Free Dynamic Range (SFDR):Wideband (Nyquist Bandwidth)1 MHz Analog Out +25°C IV 6372dBc 20 MHz Analog Out +25°C IV 5058dBc 40 MHz Analog Out +25°C IV 4654dBc Narrowband40.13579 MHz ± 50 kHz +25°C IV 80dBc 40.13579 MHz ± 200 kHz+25°C IV 77dBc 4.513579 MHz ± 50 kHz/20.5 MHz CLK +25°C IV 84dBc 4.513579 MHz ± 200 kHz/20.5 MHz CLK +25°C IV 84dBc COMPARATOR INPUT CHARACTERISTICS Input Capacitance +25°C V 3pF Input Resistance +25°C IV 500k ΩInput Current+25°C I –12+12µA Input Voltage Range +25°C IV 0V DD V Comparator Offset*Full VI 3030mV COMPARATOR OUTPUT CHARACTERISTICS Logic “1” Voltage +5 V Supply Full VI +4.8V Logic “1” Voltage +3.3 V Supply Full VI +3.1V Logic “0” VoltageFull VI +0.4V Propagation Delay, +5 V Supply (15 pF Load)+25°C V 5.5ns Propagation Delay, +3.3 V Supply (15 pF Load)+25°C V 7ns Rise/Fall Time, +5 V Supply (15 pF Load)+25°C V 3ns Rise/Fall Time, +3.3 V Supply (15 pF Load)+25°C V 3.5ns Output Jitter (p-p)+25°C V 80ps CLOCK OUTPUT CHARACTERISTICS Clock Output Duty Cycle (Clk Gen. Config.)+25°CIV50 ± 10%REV. E–2–(V S= +5 V ؎ 5% except as noted, RSET = 3.9 k ⍀)AD9850–SPECIFICATIONSAD9850AD9850BRSParameter Temp Test Level Min Typ Max Units CMOS LOGIC INPUTS (Including CLKIN)Logic “1” Voltage, +5 V Supply+25°C I 3.5V Logic “1” Voltage, +3.3 V Supply+25°C I 3.0V Logic “0” Voltage+25°C I0.4V Logic “1” Current+25°C I12µA Logic “0” Current+25°C I12µA Input Capacitance+25°C V3pF POWER SUPPLY (A OUT = 1/3 CLKIN)+V S Current @:62.5 MHz Clock, +3.3 V Supply Full VI3048mA110 MHz Clock, +3.3 V Supply Full VI4760mA62.5 MHz Clock, +5 V Supply Full VI4464mA125 MHz Clock, +5 V Supply Full VI7696mAP DISS @:62.5 MHz Clock, +3.3 V Supply Full VI100160mW110 MHz Clock, +3.3 V Supply Full VI155200mW62.5 MHz Clock, +5 V Supply Full VI220320mW125 MHz Clock, +5 V Supply Full VI380480mWP DISS Power-Down Mode+5 V Supply Full V30mW +3.3 V Supply Full V10mW NOTES*Tested by measuring output duty cycle variation.Specifications subject to change without notice.TIMING CHARACTERISTICS*(V S = +5 V ؎ 5% except as noted, R SET = 3.9 k⍀)AD9850BRSParameter Temp Test Level Min Typ Max Unitst DS(Data Setup Time)Full IV 3.5nst DH(Data Hold Time)Full IV 3.5nst WH(W_CLK min. Pulsewidth High)Full IV 3.5nst WL(W_CLK min. Pulsewidth Low)Full IV 3.5nst WD(W_CLK Delay After FQ_UD)Full IV7.0nst CD(CLKIN Delay After FQ_UD)Full IV 3.5nst FH(FQ_UD High)Full IV7.0nst FL(FQ_UD Low)Full IV7.0nst CF(Output Latency from FQ_UD)Frequency Change Full IV18CLKIN Cycles Phase Change Full IV13CLKIN Cycles t FD(FQ_UD Min. Delay After W_CLK)Full IV7.0nst RH(CLKIN Delay After RESET Rising Edge)Full IV 3.5nst RL(RESET Falling Edge After CLKIN)Full IV 3.5nst RS(Minimum RESET Width)Full IV5CLKIN Cycles t OL(RESET Output Latency)Full IV13CLKIN Cycles t RR(Recovery from RESET)Full IV2CLKIN Cycles Wake-Up Time from Power-Down Mode+25°C V5µsNOTES*Control functions are asynchronous with CLKIN.Specifications subject to change without notice.REV. E–3–AD9850–4–REV. EABSOLUTE MAXIMUM RATINGS*Maximum Junction Temperature . . . . . . . . . . . . . . . +165°C V DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V S Digital Output Continuous Current . . . . . . . . . . . . . . . 5 mA DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . .–40°C to +85°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . +300°C SSOP θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 82°C/W*Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.EXPLANATION OF TEST LEVELSTest Level I –100% Production Tested.III –Sample Tested Only.IV –Parameter is guaranteed by design and characterizationtesting.V –Parameter is a typical value only.VI –All devices are 100% production tested at +25°C.100% production tested at temperature extremes for military temperature devices; guaranteed by design and characterization testing for industrial devices.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD9850 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper E SD precautions are recommended to avoid performance degradation or loss of functionality.Application Note : Users are cautioned not to apply digital input signals prior to power-up of this device. Doing so may r esult in a latch-up condition.ORDERING GUIDEModel Temperature Range Package Description Package Option AD9850BRS–40°C to +85°CShrink Small Outline (SSOP)RS-28AD9850–5–REV. ETable I.Lead Function DescriptionsPin No.Mnemonic Function4–1,D0–D78-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and 8-bit phase/28–25control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data word.5, 24DGND Digital Ground. These are the ground return leads for the digital circuitry.6, 23DVDD Supply Voltage Leads for digital circuitry.7W_CLK Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.8FQ_UD Frequency Update. On the rising edge of this clock, the DDS will update to the frequency (or phase)loaded in the data input register, it then resets the pointer to Word 0.9CLKIN Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at 1/2V supply. The rising edge of this clock initiates operation.10, 19AGND Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).11, 18AVDD Supply Voltage for the analog circuitry (DAC and comparator).12R SETThis is the DAC’s external R SET connection. This resistor value sets the DAC full-scale output current. For normal applications (F S I OUT = 10 mA ), the value for R SET is 3.9 k Ω connected to ground. The R SET /I OUT relationship is: I OUT = 32 (1.248 V/R SET ).13QOUTB Output Complement. This is the comparator’s complement output.14QOUT Output True. This is the comparator’s true output.15VINN Inverting Voltage Input. This is the comparator’s negative input.16VINPNoninverting Voltage Input. This is the comparator’s positive input.17DACBL (NC)DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and shouldnormally be considered a “no connect” for optimum performance.20IOUTB The Complementary Analog Output of the DAC.21IOUT Analog Current Output of the DAC.22RESETReset. This is the master reset function; when set high it clears all registers (except the input register) and the DAC output will go to Cosine 0 after additional clock cycles—see Figure 19.PIN CONFIGURATIONSD3D7 MSB/SERIAL LOAD D6D5D4D2D1LSB D0RESETDVDDDGND DGND DVDD W CLK FQ UD CLKINAGND AGND IOUTB IOUTAVDD R SET QOUTB QOUT AVDD VINNVINP DACBL (NC)NC = NO CONNECTRBW # 100Hz START 0HzVBW 100HzATN # 30dB SWP 762 secSTOP 62.5MHz Figure 1.SFDR, CLKIN = 125 MHz/f OUT = 1 MHzRBW # 300Hz START 0HzVBW 300Hz ATN # 30dBSWP 182.6 sec STOP 62.5MHzFigure 2.SFDR, CLKIN = 125 MHz/f OUT= 41 MHzCh 1 500mV ⍀M 20.0ns Ch 1 1.58V D 500ps Runs AfterFigure 3.Typical Comparator Output Jitter, AD9850Configured as Clock Generator w/42 MHz LP Filter (40 MHz A OUT /125 MHz CLKIN)AD9850–Typical Performance Characteristics–6–REV. ERBW # 300Hz START 0HzVBW 300HzATN # 30dB SWP 182.6 secSTOP 62.5MHzFigure 4.SFDR, CLKIN = 125 MHz/f OUT = 20 MHzRBW # 3Hz CENTER 4.513579MHzVBW 3Hz ATN # 20dBSWP 399.5 sec SPAN 400kHzFigure 5.SFDR, CLKIN = 20.5 MHz/f OUT = 4.5 MHzOFFSET FROM 5MHz CARRIER – Hz–––––––––––100100k1kd B c10k Figure 6. Output Residual Phase Noise (5 MHz A OUT /125 MHz CLKIN)AD9850–7–REV. ECh1 1.00V ⍀ M 1.00ns Ch 1 1.74V Figure parator Output Rise Time (5 V Supply/15 pF Load)CLKIN – MHz140204060801001206852S F D R – d B66605856546462Figure 8.SFDR vs. CLKIN Frequency (A OUT = 1/3 of CLKIN)FREQUENCY OUT – MHz9080304010S U P P L Y C U R R E N T – m A203070605040Figure 9.Supply Current vs. A OUT Frequency (CLKIN = 125/110 MHz for 5 V/3.3 V Plot)Ch1 1.00V ⍀ M 1.00ns Ch 1 1.74VFigure parator Output Fall Time (5 V Supply/15 pF Load)CLOCK FREQUENCY – MHz0140204060801001209010S U P P L Y C U R R E N T –m A80504030207060Figure 11.Supply Current vs. CLKIN Frequency (A OUT = 1/3 of CLKIN)DAC I OUT – mA205S F D R – d B1015Figure 12.SFDR vs. DAC I OUT (A OUT = 1/3 of CLKIN)AD9850–8–REV. E5-POLE ELLIPTICALFigure 13.Basic AD9850 Clock Generator Application with Low-Pass FilterFigure 14.AD9850 Clock Generator Application in a Spread-Spectrum Receivera.Frequency/Phase –Agile Local Oscillatorb.Frequency/Phase –Agile Reference for PLLREFRFc.Digitally-Programmable ”Divide-by-N “ Function in PLLFigure 15.AD9850 Complete-DDS Synthesizer in Frequency Up-Conversion ApplicationsTHEORY OF OPERATION AND APPLICATIONThe AD9850 uses direct digital synthesis (DDS) technology, in the form of a numerically controlled oscillator, to generate a frequency/phase-agile sine wave. The digital sine wave is con-verted to analog form via an internal 10-bit high speed D/Aconverter, and an onboard high speed comparator is provided to translate the analog sine wave into a low jitter TTL/CMOS-compatible output square wave. DDS technology is an innova-tive circuit architecture that allows fast and precise manipulation of its output frequency under full digital control. DDS also enables very high resolution in the incremental selection of output frequency; the AD9850 allows an output frequency resolution of 0.0291 Hz with a 125 MHz reference clock ap-plied. The AD9850’s output waveform is phase-continuous when changed.The basic functional block diagram and signal flow of theAD9850 configured as a clock generator is shown in Figure 16.The DDS circuitry is basically a digital frequency divider function whose incremental resolution is determined by the frequency of the reference clock divided by the 2N number of bits in the tuning word. The phase accumulator is a variable-modulus counter that increments the number stored in it each time itreceives a clock pulse. When the counter overflows it wraps around, making the phase accumulator’s output contiguous.The frequency tuning word sets the modulus of the counter that effectively determines the size of the increment (∆ Phase) that gets added to the value in the phase accumulator on the next clock pulse. The larger the added increment, the faster the ac-cumulator overflows, which results in a higher output fre-quency. The AD9850 uses an innovative and proprietary algorithm that mathematically converts the 14-bit truncated value of the phase accumulator to the appropriate COS value.This unique algorithm uses a much reduced ROM look-up table and DSP techniques to perform this function, which contributes to the small size and low power dissipation of the AD9850. The relationship of the output frequency, reference clock, and tuning word of the AD9850 is determined by the formula:f OUT = (∆ Phase × CLKIN )/232where:∆ Phase =value of 32-bit tuning wordCLKIN =input reference clock frequency in MHz f OUT =frequency of the output signal in MHz The digital sine wave output of the DDS block drives the inter-nal high speed 10-bit D/A converter that reconstructs the sineAD9850–9–REV. EFigure 16.Basic DDS Block Diagram and Signal Flow of AD9850The reference clock frequency of the AD9850 has a minimum limitation of 1 MHz. The device has internal circuitry that senses when the minimum clock rate threshold has been exceeded and automatically places itself in the power-down mode. When in this state, if the clock frequency again exceeds the threshold,the device resumes normal operation. This shutdown mode prevents excessive current leakage in the dynamic registers of the device.The D/A converter output and comparator inputs are available as differential signals that can be flexibly configured in anymanner desired to achieve the objectives of the end-system. The typical application of the AD9850 is with single-ended output/input analog signals, a single low-pass filter, and generating the comparator reference midpoint from the differential DAC out-put as shown in Figure 13.Programming the AD9850The AD9850 contains a 40-bit register that is used to program the 32-bit frequency control word, the 5-bit phase modulation word and the power-down function. This register can be loaded in a parallel or serial mode.In the parallel load mode, the register is loaded via an 8-bit bus;the full 40-bit word requires five iterations of the 8-bit word.The W_CLK and FQ_UD signals are used to address and load the registers. The rising edge of FQ_UD loads the (up to) 40-bit control data word into the device and resets the address pointer to the first register. Subsequent W_CLK rising edges load the 8-bit data on words [7:0] and move the pointer to the next register. After five loads, W_CLK edges are ignored until either a reset or an FQ_UD rising edge resets the address pointer to the first register.In serial load mode, subsequent rising edges of W_CLK shift the 1-bit data on Lead 25 (D7) through the 40 bits of program-ming information. After 40 bits are shifted through, an FQ_UD pulse is required to update the output frequency (or phase).The function assignments of the data and control words are shown in Table III; the detailed timing sequence for updating the output frequency and/or phase, resetting the device, and powering-up/down, are shown in the timing diagrams of Figures 18–24.Note:There are specific control codes, used for factory test purposes, that render the AD9850 temporarily inoperable. The user must take deliberate precaution to avoid inputting the codes listed in Table II.wave in analog form. This DAC has been optimized for dynamic performance and low glitch energy as manifested in the low jitter performance of the AD9850. Since the output of the AD9850 is a sampled signal, its output spectrum follows the Nyquist sampling theorem. Specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the Reference Clock Frequency ± the selected output frequency. A graphical representation of the sampled spectrum, with aliased images, is shown in Figure 17.REFERENCE CLOCKFREQUENCYFigure 17. Output Spectrum of a Sampled SignalIn this example, the reference clock is 100 MHz and the output frequency is set to 20 MHz. As can be seen, the aliased images are very prominent and of a relatively high energy level as deter-mined by the sin(x)/x roll-off of the quantized D/A converter output. In fact, depending on the fo/Ref Clk relationship, the first aliased image can be on the order of –3dB below the fun-damental. A low-pass filter is generally placed between the out-put of the D/A converter and the input of the comparator to further suppress the effects of aliased images. Obviously, con-sideration must be given to the relationship of the selected output frequency and the Reference Clock frequency to avoid unwanted (and unexpected) output anomalies.A good rule-of-thumb for applying the AD9850 as a clock generator is to limit the selected output frequency to <33% of Reference Clock frequency, thereby avoiding generating aliased signals that fall within, or close to, the output band of interest (generally dc-selected output frequency). This practice will ease the complexity (and cost) of the external filter requirement for the clock generator application.AD9850–10–REV. ETable II.Factory-Reserved Internal Test Control CodesLoading Format Factory-Reserved Codes Parallel 1) W0 = XXXXXX102) W0 = XXXXXX01Serial1) W32 = 1; W33 = 02) W32 = 0; W33 = 13) W32 = 1; W33 = 1Table III.8-Bit Parallel-Load Data/Control Word Functional AssignmentWord data[7]data[6]data[5]data[4]data[3]data[2]data[1]data[0]W0Phase-b4Phase-b3Phase-b2Phase-b1Phase-b0Power-Down Control Control (MSB) (LSB)W1Freq-b31Freq-b30Freq-b29Freq-b28Freq-b27Freq-b26Freq-b25Freq-b24(MSB)W2Freq-b23Freq-b22Freq-b21Freq-b20Freq-b19Freq-b18Freq-b17Freq-b16W3Freq-b15Freq-b14Freq-b13Freq-b12Freq-b11Freq-b10Freq-b9Freq-b8W4Freq-b7Freq-b6Freq-b5Freq-b4Freq-b3Freq-b2Freq-b1Freq-b0(LSB)OLD FREQ (PHASE)NEW FREQ (PHASE)*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCKDATAW CLKREF CLKCOS OUTFQ UDFigure 18.Parallel-Load Frequency/Phase Update Timing SequenceAD9850COS OUTRESETt RH CLK DELAY AFTER RESET RISING EDGE3.5ns t RLRESET FALLING EDGE AFTER CLK 3.5nst RRRECOVERY FROM RESET 2 CLK CYCLES tRSMINIMUM RESET WIDTH 5 CLK CYCLES t OLRESET OUTPUT LATENCY 13 CLK CYCLESSYMBOL DEFINITION MIN SPECRESULTS OF RESET:– FREQUENCY/PHASE REGISTER SET TO 0– ADDRESS POINTER RESET TO W0– POWER-DOWN BIT RESET TO “0”– DATA INPUT REGISTER UNEFFECTEDFigure 19. Master Reset Timing SequenceDATA (W0)W CLKFQ UDREF CLKDAC STROBEFigure 20.Parallel-Load Power-Down Sequence/Internal OperationDATA (W0)W CLKFQ UDREF CLKFigure 21.Parallel-Load Power-Up Sequence/Internal OperationAD9850DATA (W0)(PARALLEL)W CLK FQ UDARE REQUIRED TO SHIFT IN REQUIRED W32–W34 DATA DATA (SERIAL)REQUIRED TO RESET CONTROL REGISTERSNOTE: FOR DEVICE START-UP IN SERIAL MODE, HARD-WIRE LEAD 2 AT “0”, LEAD 3 AT “1”, AND LEAD 4 AT “1”(SEE FIGURE 23).Figure 22.Serial-Load Enable SequenceFigure 23.Leads 2–4 Connection for Default Serial-Mode OperationDATA–W CLKFQ UDFigure 24.Serial-Load Frequency/Phase Update Sequence Table IV.40-Bit Serial-Load Word Function AssignmentW0Freq-b0 (LSB) W1Freq-b1W2Freq-b2W3Freq-b3W4Freq-b4W5Freq-b5W6Freq-b6W7Freq-b7W8Freq-b8W9Freq-b9W10Freq-b10W11Freq-b11W12Freq-b12W13Freq-b13W28Freq-b28W29Freq-b29W30Freq-b30W31Freq-b31 (MSB)W32ControlW33ControlW34Power-DownW35Phase-b0 (LSB)W36Phase-b1W37Phase-b2W38Phase-b3W39Phase-b4 (MSB) W14Freq-b14W15Freq-b15W16Freq-b16W17Freq-b17W18Freq-b18W19Freq-b19W20Freq-b20W21Freq-b21W22Freq-b22W23Freq-b23W24Freq-b24W25Freq-b25W26Freq-b26W27Freq-b27AD9850DATA (7) –W CLKFQUDFigure 25.Serial-Load Power-Down SequenceDIGITALINV DAC Output Comparator Output Comparator Input Digital InputsFigure 26.AD9850 I/O Equivalent CircuitsPCB LAYOUT INFORMATIONThe AD9850/CGPCB and AD9850/FSPCB evaluation boards (Figures 27–30) represent typical implementations of the AD9850 and exemplify the use of high frequency/high resolu-tion design and layout practices. The printed circuit board that contains the AD9850 should be a multilayer board that allows dedicated power and ground planes. The power and ground planes should be free of etched traces that cause discontinuities in the planes. It is recommended that the top layer of the multi-layer board also contain interspatial ground plane, which makes ground available for surface-mount devices. If separate analog and digital system ground planes exist, they should be con-nected together at the AD9850 for optimum results.Avoid running digital lines under the device as these will couple noise onto the die. The power supply lines to the AD9850should use as large a track as possible to provide a low-impedance path and reduce the effects of glitches on the power supply line.Fast switching signals like clocks should be shielded withground to avoid radiating noise to other sections of the board.Avoid crossover of digital and analog signal paths. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the circuit board. Use microstrip techniques where possible.Good decoupling is also an important consideration. The analog (AVDD) and digital (DVDD) supplies to the AD9850 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND,respectively, with high quality ceramic capacitors. To achieve best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right upagainst the device. In systems where a common supply is used to drive both the AVDD and DVDD supplies of the AD9850, it is recommended that the system’s AVDD supply be used.Analog Devices, Inc., applications engineering support is avail-able to answer additional questions on grounding and PCB layout. Call 1-800-ANALOGD.Evaluation BoardsTwo versions of evaluation boards are available for the AD9850,which facilitate the implementation of the device for bench-top analysis, and serve as a reference for PCB layout. The AD9850/FSPCB is intended for applications where the device will primarily be used as frequency synthesizer. This version facilitates connection of the AD9850’s internal D/A converter output to a 50Ω spectrum analyzer input; the internal com-parator on the AD9850 DUT is not enabled (see Figure 28 for electrical schematic of AD9850/FSPCB). The AD9850/CGPCB is intended for applications using the device in the clock genera-tor mode. It connects the AD9850’s DAC output to the internal comparator input via a single-ended, 42 MHz low-pass, 5-pole Elliptical filter. This model facilitates the access of the AD9850’s comparator output for evaluation of the device as a frequency- and phase-agile clock source (see Figure 29 for electrical schematic of AD9850/CGPCB).Both versions of the AD9850 evaluation boards are designed to interface to the parallel printer port of a PC. The operating software runs under Microsoft ® Windows and provides a user-friendly and intuitive format for controlling the functionality and observing the performance of the device. The 3.5" floppy provided with the evaluation board contains an executable file that loads and displays the AD9850 function-selection screen.The evaluation board may be operated with +3.3 V or +5 V supplies. The evaluation boards are configured at the factory for an external reference clock input; if the onboard crystal clock source is used, remove R2.All trademarks are the property of their respective holders.。
ad9851中文资料
ＤＤＳ基本原理及性能特点
ＤＤＳ的基本原理是利用采样定理，通过查表法产生波形。ＤＤ Ｓ的结构有很多种，其基本的电路原理可用图 3 来表示。
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相位累 加器
波形存 储器
D/A 转 换器
低通滤 波器
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相位累加器由Ｎ位加法器与Ｎ位累加寄存器级联构成。每来一个 时钟脉冲ｆｓ，加法器将频率控制字ｋ与累加寄存器输出的累加相位 数据相加，把相加后的结果送至累加寄存器的数据输入端。累加寄存 器将加法器在上一个时钟脉冲作用后所产生的新相位数据反馈到加 法器的输入端，以使加法器在下一个时钟脉冲的作用下继续与频率控 制字相加。这样，相位累加器在时钟作用下，不断对频率控制字进行 线性相位累加。由此可以看出，相位累加器在每一个时钟脉冲输入时， 把频率控制字累加一次，相位累加器输出的数据就是合成信号的相 位，相位累加器的溢出频率就是ＤＤＳ输出的信号频率。 用相位累 加器输出的数据作为波形存储器（ＲＯＭ）的相位取样地址，这样就 可把存储在波形存储器内的波形抽样值（二进制编码）经查找表查出， 完成相位到幅值转换。波形存储器的输出送到Ｄ／Ａ转换器，Ｄ／Ａ 转换器将数字量形式的波形幅值转换成所要求合成频率的模拟量形 式信号。低通滤波器用于滤除不需要的取样分量，以便输出频谱纯净 的正弦波信号。 ＤＤＳ在相对带宽、频率转换时间、高分辨力、相 位连续性、正交输出以及集成化等一系列性能指标方面远远超过了传 统频率合成技术所能达到的水平，为系统提供了优于模拟信号源的性 能。 （１）输出频率相对带宽较宽
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电子信息工程文献专业英语中英互译
Electronic power steering systemWhat it is?Electrically powered steering uses an electric motor to drive either the power steering hydraulic pump or the steering linkage directly. The power steering function is therefore independent of engine speed, resulting in significant energy savings.How it works?Conventional power steering systems use an engine accessory belt to drive the pump, providing pressurized fluid that operates a piston in the power steering gear or actuator to assist the driver.In electro-hydraulic steering, one electrically powered steering concept uses a high efficiency pump driven by an electric motor. Pump speed is regulated by an electric controller to vary pump pressure and flow, providing steering efforts tailored for different driving situations. The pump can be run at low speed or shut off to provide energy savings during straight ahead driving (which is most of the time in most world markets).Direct electric steering uses an electric motor attached to the steering rack via a gear mechanism (no pump or fluid). A variety of motor types and gear drives is possible. A microprocessor controls steering dynamics and driver effort. Inputs include vehicle speed and steering, wheel torque, angular position and turning rate.Working In Detail:A "steering sensor" is located on the input shaft where it enters the gearbox housing. The steering sensor is actually two sensors in one: a "torque sensor" that converts steering torque input and its direction into voltage signals, and a "rotation sensor" that converts the rotation speed and direction into voltage signals. An "interface" circuit that shares the same housing converts the signals from the torque sensor and rotation sensor into signals the control electronics can process. Inputs from the steering sensor are digested by a microprocessor control unit that alsomonitors input from the vehicle's speed sensor. The sensor inputs are then compared to determine how much power assist is required according to a preprogrammed "force map" in the control unit's memory. The control unit then sends out the appropriate command to the "power unit" which then supplies the electric motor with current. The motor pushes the rack to the right or left depending on which way the voltage flows (reversing the current reverses the direction the motor spins). Increasing the current to the motor increases the amount of power assist.The system has three operating modes: a "normal" control mode in which left or right power assist is provided in response to input from the steering torque and rotation sensor's inputs; a "return" control mode which is used to assist steering return after completing a turn; and a "damper" control mode that changes with vehicle speed to improve road feel and dampen kickback.If the steering wheel is turned and held in the full-lock position and steering assist reaches a maximum, the control unit reduces current to the electric motor to prevent an overload situation that might damage the motor. The control unit is also designed to protect the motor against voltage surges from a faulty alternator or charging problem.The electronic steering control unit is capable of self-diagnosing faults by monitoring the system's inputs and outputs, and the driving current of the electric motor. If a problem occurs, the control unit turns the system off by actuating a fail-safe relay in the power unit. This eliminates all power assist, causing the system to revert back to manual steering. A dash EPS warning light is also illuminated to alert the driver. To diagnose the problem, a technician jumps the terminals on the service check connector and reads out the trouble codes.Electric power steering systems promise weight reduction, fuel savings and package flexibility, at no cost penalty.Europe's high fuel prices and smaller vehicles make a fertile testbed for electric steering, a technology that promises automakers weight savings and fuel economy gains. And in a short time, electric steering will make it to the U.S., too. "It's just just a matter of time," says Aly Badawy, director of research and development for Delphi Saginaw SteeringSystems in Saginaw, Mich. "The issue was cost and that's behind us now. By 2002 here in the U.S. the cost of electric power steering will absolutely be a wash over hydraulic."Today, electric and hybrid-powered vehicles (EV), including Toyota's Prius and GM's EV-1, are the perfect domain for electric steering. But by 2010, a TRW Inc. internal study estimates that one out of every three cars produced in the world will be equipped with some form of electrically-assisted steering. The Cleveland-based supplier claims its new steering systems could improve fuel economy by up to 2 mpg, while enhancing handling. There are true bottom-line benefits as well for automakers by reducing overall costs and decreasing assembly time, since there's no need for pumps, hoses and fluids.Another claimed advantage is shortened development time. For instance, a Delphi group developed E-TUNE, a ride-and-handling software package that can be run off a laptop computer. "They can take that computer and plug it in, attach it to the controller and change all the handling parameters -- effort level, returnability, damping -- on the fly," Badawy says. "It used to take months." Delphi has one OEM customer that should start low-volume production in '99.Electric steering units are normally placed in one of three positions: column-drive, pinion-drive and rack-drive. Which system will become the norm is still unclear. Short term, OEMs will choose the steering system that is easiest to integrate into an existing platform. Obviously,greater potential comes from designing the system into an all-new platform. "We have all three designs under consideration," says Dr. Herman Strecker, group vice president of steering systems division at ZF in Schwaebisch Gmuend, Germany. "It's up to the market and OEMs which version finally will be used and manufactured." "The large manufacturers have all grabbed hold of what they consider a core technology," explains James Handy sides, TRW vice president, electrically assisted steering in Sterling Heights, Mich. His company offers a portfolio of electric steering systems (hybrid electric, rack-, pinion-, and column-drive). TRW originally concentrated on what it still believes is the purest engineering solution for electric steering--the rack-drive system. The system is sometimes refer to as direct drive orball/nut drive. Still, this winter TRW hedged its bet, forming a joint venture with LucasV arity. The British supplier received $50 million in exchange for its electric column-drive steering technology and as sets. Initial production of the column and pinion drive electric steering systems is expected to begin in Birmingham, England, in 2000.In 1995, according to Delphi, traditional hydraulic power steering systems were on 7596 of all vehicles sold globally. That 37-million vehicle pool consumes about 10 million gallons in hydraulic fluid that could be superfluous, if electric steering really takes off.The present invention relates to an electrically powered drive mechamsm for providing powered assistance to a vehicle steering mechanism. According to one aspect of the present invention, there is provided an electrically powered driven mechanism for providing powered assistance to a vehicle steering mechanism having a manually rotatable member for operating the steering mechanism, the drive mechanism including a torque sensor operable to sense torque being manually applied to the rotatable member, an electrically powered drive motor drivingly connected to the rotatable member and a controller which is arranged to control the speed and direction of rotation of the drive motor in response to signals received from the torque sensor, the torque sensor including a sensor shaft adapted for connection to the rotatable member to form an extension thereof so that torque is transmitted through said sensor shaft when the rotatable member is manually rotated and a strain gauge mounted on the sensor shaft for producing a signal indicative of the amount of torque being transmitted through said shaft. Preferably the sensor shaft is non-rotatably mounted at one axial end in a first coupling member and is non-rotatably mounted at its opposite axial end in a second coupling member, the first and second coupling members being inter-engaged to permit limited rotation there between so that torque under a predetermined limit is transmitted by the sensor shaft only and so that torque above said predetermined limit is transmitted through the first and second coupling members.Now, power steering systems of some cars have become the standard-setting, the whole world about half of the cars used to powersteering. With the development of automotive electronics technology, some cars have been using electric power steering gear, the car of the economy, power and mobility has improved. Electric power steering device on the car is a new power steering system device, developed rapidly in recent years both at home and abroad, because of its use of programmable electronic control devices, the flexibility in the same time there are also potential safety problems. In the analysis This unique product on the basis of the author of the characteristics of electronic control devices, security clearance just that the factors that deal with security measures, and discussed a number of concerns the safety of specific issues. The results show that : Existing standards can not meet the electric power steering device security needs and made the electric power steering device safety evaluation of the idea. Research work on the electric power steering device development and evaluation of reference value.电子动力转向系统电子动力转向系统是什么?电子动力转向系统是通过一个电动机来驱动动力方向盘液压泵或直接驱动转向联动装置。
西安工业大学及二级学院(部)英文对照翻译
陕西省薄膜技术与微光电器件军民两用技术工程中心
Shaanxi Province Engineering Center of Thin Films and Micro-Optoelectronic Devices
继续教育学院
School of Continuing Education
Teaching and Research Instituteof Political Theory
北方信息工程学院
North College of Information Engineering
陕西省薄膜技术与光学检测重点实验室
计算机科学与工程学院
School of Computer Science and Engineering
建筑工程学院
School of Civil Engineering
电子信息工程学院
School of Electronic Information Engineering
理学院
School ofScience
经济管理学院
School of Economics and Managenities
艺术与传媒学院
School of Art and Communication
外国语学院
School of Foreign Languages
体育学院
School ofPhysical Education
西安工业大学及二级学院部英文对照翻译西安工业大学xiantechnologicaluniversity光电工程学院schooloptoelectronicengineering机电工程学院schoolmechatronicengineering材料与化工学院schoolchemicalengineering计算机科学与工程学院schoolcomputerscienceengineering建筑工程学院schoolcivilengineering电子信息工程学院schoolelectronicinformationengineering理学院schoolscience经济管理学院schoolmanagement人文学院schoolhumanities艺术与传媒学院schoolcommunication外国语学院schoolforeignlanguages体育学院schoolphysicaleducation继续教育学院schoolcontinuingeducation思想政治理论教学科研部teachingresearchinstitutepoliticaltheory北方信息工程学院northcollegeinformationengineering陕西省薄膜技术与光学检测重点实shaanxiprovincekeylabthinfilmstechnologyopticaltest陕西省薄膜技术与微光电器件军民两用技术工程中心shaanxiprovinceengineeringcenterthinfilmsmicrooptoelectronicdevices中白高技术合作研究中心sinobelarushitechjointresearchcenter陕西省薄膜技术与光学检测重点开放实验室shaanxiprovincethinfilmtechnologyopticaltestopenkeylaboratory
课文参考译文 (6)-信息科学与电子工程专业英语(第2版)-吴雅婷-清华大学出版社
Unit 6 移动通信Unit 6-1第一部分：移动通信一个移动通信系统是指用户在这个系统中可以一边和别人互相通信，一边在物理位置上进行移动。
例如：传呼机、蜂窝电话和无绳电话。
移动性使得射频通信功能强大而且广为流行。
用户所持的收发器叫移动单元、终端或手持单元。
无线基础设施的复杂性往往要求移动单元只通过一些固定的、较昂贵的称为基站的设备进行通信。
每个移动单元通过两个射频信道接收来自基站的信息并向基站发射信息，这两个信道分别称为前向信道或下行链路，以及逆向信道或上行链路。
我们大多数讨论的是移动单元，因为和基站相比，手持单元构成市场极大的一块，它们的设计更接近于其他射频系统。
蜂窝系统对于一个有限的可用频谱（例如：900MHz附近的一个25MHz的频谱），数十万人如何在拥挤的城区里相互通信？为了回答这个问题，首先考虑一种较简单的情况：几千个FM电台可利用88-108MHz的频带在一个国家里广播。
这是可能的，因为在物理位置上相隔足够远的电台可使用同一载波频率（频率重用），而相互干扰可以忽略。
两个电台的中间位置除外，这里接收到的两个电台信号强度相近。
两个可以使用相同载波频率的电台的最小距离是由每个电台发射的信号功率所决定的。
在移动通信系统中，用蜂窝结构来实现频率重用概念，其中每一个蜂窝是六边形的，其周围环绕着6个其它的蜂窝，如图6.1(a)所示。
频率重用概念是：如果位于中央的蜂窝使用频率f1进行通信，那么与其相邻的6个蜂窝就不能使用这个频率，但外面不直接相邻的蜂窝可再次使用这个频率。
实际上，更有效的频率分配方式是如图6.1(b)所示的“7蜂窝”重用模式。
注意：实际上每个蜂窝是使用了一组频率。
图6.1(b)中的每一个蜂窝中的移动单元都有一个基站提供服务，而所有的基站则有一个移动电话交换机构（MTSO）来控制。
同信道干扰在蜂窝系统中，一个重要的问题是两个使用同一频率的单元之间的干扰有多大。
这种干扰叫做同信道干扰，这一效应依赖于两个同信道单元之间的距离与单元半径之比，而与发射功率无关。
AD9858
AD9858直接数字式频率综合器技术数据手册李跃锋译特点.1GHz采样速度.最高输入时钟2GHz (内含可选2分频器).集成了10位D/A变换器.在偏离载频1kHz处的相位噪声<130dBc(D/A变换器输出).32位可编程频率寄存器.简化8位并行和SPI串行控制接口.自动频率扫描功能.4个频率区.3.3V电源.功率耗散<2W.100引脚EPAD-TQFP封装.集成了可编程泵源和具有快速锁定电路的鉴频鉴相.泵源独立供电,可到5V.集成了2GHz混频器应用范围.VHF/UHF本振合成.调谐器.仪器设备.多功能时钟合成.蜂窝基站跳频合成器.雷达.SONET/SDH时钟合成简要介绍AD9858直接数字式频率综合器(DDS)内部提供了一个每秒1G次采样率的10位数模变换器。
AD9858采用先进的DDS技术，又结合内部的高速、高性能D/A变换器，构成了一种频率高、数字可编程的完善的合成器，能够产生频率变化灵活、最高频率大于400MHz的模拟正弦波信号。
AD9858具有跳频速度快、频率分辨率高(32位频率调谐字)的特点。
频率调谐字和功能控制字通过并行(8位)或串行接口调入。
AD9858含有一个集成泵源(CP)和一个鉴频/鉴相器，用于需要把高速DDS和锁相环结合起来的场合;还提供了一个片内模拟混频器, 用于需要把高速DDS、锁相环和混频器结合起来的场合,例如频率平移锁相环、调谐器等。
AD9858的时钟输入端还提供了一个除2分频器，该分频器允许输入时钟的最高频率达2GHz。
AD9858的额定工作温度范围是-40~+85℃，属于扩展工业级产品。
引脚功能排列图功能方框图图1 AD9858的功能方框图工作原理一概述AD9858直接数字式频率综合器(DDS)是一种可塑性很强的器件,应用范围很广。
该器件由一个32位相位累加器的NCO、一个14位移相、一个高效的DDS核心、一个每秒1G次采样率的10位数模变换器组成。
信息工程专业英语 习题参考答案
1.1 Text 1.2 Reading Materials
Unit 1 1. Put the Phrases into English (1) operational amplifier; (2) transfer function; (3) electronic devices; (4) integrated circuit; (5) feedback circuits; (6) performance preferences.
Unit 8 1. Put the Phrases into English (1) dish antenna; (2) radio detection; (3) air traffic control; (4) radar astronomy; (5) antimissile systems; (6) electromagnetic spectrum; (7) civilian field; (8) severe weather; (9) short-term weather forecasting.
2. Put the Phrases into Chinese (1) 一个抗混叠滤波器； (2) 新式数字设备； (3) 有序样本值； (4) 间距相等的时间间隔； (5) 采样点； (6) 低通量化滤波器； (7) 人类听觉的限制； (8) 不规则跳动。
3. Translation (1) 采样值表示振幅，由一些决定如何准确测量样品的 位数编码而成。 (2) 当信号被数字-模拟转换器(DAC)转换成音频信号后， 会有锯齿状的不规则波形(显示如下)即量化错误。 (3) 最右边的波形频率特别高，所以采样波将被看做(被 混叠为)缓慢的虚线(这与最左边的曲线相同)。 (4) 输出信号将较为平缓直到下一个采样进来。 (5) 如果采样率是商业的CD标准，那么这种噪音会高于 人类听觉的限制，所以你自己的耳朵可以作为低通量化滤波 器。
基于AD9850的多功能信号源的设计
图2 正电压变负电压电路出。
通常选定R 2=30k Ω(10k Ω<R 2<200k Ω)。
通过改变R 1电阻值即可方便地得到相应的输出电压值。
例如:R 1=258k Ω时,V OU T =12V 。
3.2 正电压变负电压图2所示为正电压变负电压的应用电路。
元件参数的选择与图1相同(注意POL 接V CC ),输出电压同样由R 1、R 2的关系确定:R 1=R 2×|V OU T |V REF(2)式(2)中V REF =1.25V ,同样选定R 2=30k Ω,改变R 1的阻值即可得到相应的输出电压。
例如:R 1=288kΩ时,V OU T =-12V 。
这里需要提请注意:图2所示的电路输出V OU T 只能在-28V ～-V IN 之间变化,要想得到高于-V IN 的负电压,必须将D 2的阴极与输入V IN 相连,再按式(2)计算R 1的阻值从而得到V OU T 。
但这种电路改变同时会使输出电流最大值降低一半,从而降低了负电源的供电能力,因此应尽可能采用图2所示电路得到相应的负电压。
3.3 输出电流选择MAX629提供了一个输出电流选择引脚ISET 。
无论是正电压变负电压或正电压变正电压,都可以改变ISET 与V CC 、GND 的连接,得到最大500mA 、最小250mA 的输出电流。
当电路所需电流低于250mA 时,ISET =GND ,用户即可采用功率较小的电感,输出端的电容也可采用普通电容,这样既节省空间,又降低了成本。
4 结语MAX629既可用于正电压变负电压又可用于正电压变正电压,同时输出电压改变灵活方便,变化范围宽。
具有体积小巧、成本低廉、转换灵活的优点,在需要DC 2DC 转换的控制电路中具有广泛的应用前景。
器件应用基于AD9850的多功能信号源的设计中国人民解放军电子工程学院(合肥230037) 周义建 游志刚 摘 要 文章介绍了美国AD 公司推出的直接数字频率合成芯片AD9850,并给出了一种基于该芯片的多功能信号源的设计方案,该信号源具有结构简单、精度高、控制灵活的特点。
电子信息 外文文献译文
XXXX学院毕业设计（论文）外文参考文献译文本2012届原文出处A Novel Cross-layer Quality-of-service ModelFor Mobile AD hoc Network毕业设计(论文)题目基于COMNETIII的局域网的规划与设计院（系）电气与电子信息学院专业名称电子信息工程学生姓名学生学号指导教师A Novel Cross-layer Quality-of-service ModelFor Mobile AD hoc NetworkLeichun Wang, Shihong Chen, Kun Xiao, Ruimin Hu National Engineering Research Center of Multimedia Software, Wuhan UniversityWuhan 430072, Hubei, chinaEmail:******************Abstract:The divided-layer protocol architecture for Mobile ad hoc Networks (simply MANETs) can only provide partial stack. This leads to treat difficulties in QoS guarantee of multimedia information transmission in MANETs, this paper proposes Across-layers QoS Model for MANETs, CQMM. In CQMM, a core component was added network status repository (NSR), which was the center of information exchange and share among different protocol layers in the stack. At the same time, CQMM carried out all kinds of unified QoS controls. It is advantageous that CQMM avoids redundancy functions among the different protocol layers in the stack and performs effective QoS controls and overall improvements on the network performances.Keyword: Cross-layers QoS Model, Mobile Ad hoc Networks (MANETs), Network Status Repository (NSR), QoS Controls.1 introductionWith the rapid development of multimedia technologies and the great increase of his bandwidth for personal communication, video and video services begin to be deployed in MANETs. Different from static networks and Internet, multimedia communications in MANETs such as V oice and Video services require strict QoS guarantee, especially the delay guarantee. In addition, communication among different users can be integrated services with different QoS requirements. These lead to great challenges in QoS guarantee of multimedia communication in MANETs. There are two main reasons in these: 1) MANETs runs in atypical wireless environment with time-varying and unreliable physical link, broadcast channel, and dynamic and limited bandwidth and so forth. Therefore, it can only provide limited capability for differentiated services with strict QoS requirements [1].2) It is difficult that traditional flow project and access control mechanism are implemented because of mobility, multiple hops and self-organization of MANETs.At present, most researches on QoS based on traditional divided-layer protocol architecture for MANETs focus on MAC protocol supporting QoS [2], QoS routingprotocol [3] and adaptive application layer protocol with QoS support [4], and so on. It is avoid less that there will be some redundancies on functions among the different protocol layers in the stack. This will increase the complexity of QoS implementation and cause some difficulties in overall improvement on the network performances. Therefore, it is not suitable for MANETs with low processing abilityIn recent years, the cross-layers design based on the partial protocol layers in MANETs was put forward.[1] proposed the mechanism with QoS guarantee for heterogeneous flow MAC layer.[5,6,7,8] did some researches on implementing video communication with QoS guarantee by exchange and cooperation of information among a few layers in MANETs. These can improve QoS in MANETs’communication to some extent. However, MANETs is much more complex than wired system and static network, and improvements on QoS guarantee depend on full cooperation among all layers in the protocol stack. Therefore, it is difficult for the design to provide efficient QoS guarantee for communication and overall improvements on the network performances in MANETs.To make good use of limited resources and optimize overall performances in MANETs, this paper proposes a novel cross-layer QoS model, CQMM, where different layers can exchange information fully and unified QoS managements and controls can be performed.The rest of the paper is organized as follows. CQMM is described in section 2 in detail. In section 3, we analyze CQMM by the comparison with DQMM.The section 4 concludes the paper.2. A CROSS-LAYER QOS MODEL FOR MANETS-CQMM2.1 Architecture of CQMMIn MANETs, present researches on QoS are mostly based on traditional divided-layer protocol architecture, where signals and algorithms supporting QoS are designed and implemented in different layers respectively, such as MAC protocol supporting QoS in data link layer [9], routing protocol with QoS support in network layer[10.11],and so forth. It can be summarized as A Divided-layer QoS Model for MANETs, DQMM (see fig.1).In DQMM, different layers in the protocol stack are designed and work independently; there are only static interfaces between different layers that are neighboring in logic; and each protocol layer has some QoS controls such as error control in logic link layer, congestion control in network, etc. On the one hand, DQMM can simplify the design of MANETs greatly and gain the protocols with high reliability and extensibility. On the other one, DQMM also has some shortcomings: 1) due to the independent design among he different protocol layers, there are some redundancy functions among the different protocollayers in the stack, 2) it is difficult that information is exchanged among different layers that are not neighboring in logic, which leads to some problems in unified managements, QoS controls and overall improvements on the network performances.Fig.1Therefore, it is necessary that more attention are focused on the cooperation among physical layer data link layer, network layer and higher when attempting to optimize performances of each of layer in MANETs. For this reason, we combine parameters dispersed in different layers and design a novel cross-layer QoS model, CQMM, to improve the QoS guarantee and the overall network performances. The architecture of CQMM is provided in fig 2From fig.2, it can be seen that CQMM keeps the core functions and relative independence of each protocol layer in the stack and allows direct information exchange between two neighboring layers in logics to maintain advantages of the modular architecture .On the basic of these, a core component is added in CQMM, Network Status Repository (simply NSR).NSR is the center, by which different layers can exchange and share information fully. On the one hand, each protocol layer can read the status information of other protocol layers from NSR to determine its functions and implementation mechanisms. On the other one, each protocol layer can write its status information to NSR that can be provided with other layers in the protocol stack. In CQMM, the protocol layers that are neighboring in logics can exchange information directly orindirectly by NSR, and the protocol layers that are not neighboring in logics can exchange information using cross-layer ways via NSR. Therefore, information exchange is flexible in CQMM.All kinds of QoS controls in CQMM such as management and scheduling of network resources, network lifetime, error control, and congestion control and performance optimization and so on are not carried out independently. On the contrary, CQMM is in charge of the unified management and all QoS controls by the cooperation among different protocol layers in the stack. Each QoS control in MANETs is related to all layers in the protocol stack, and also constrained by all layers in the stack. The results of all QoS operations and managements are fed back to the different layers and written back to NSR, which will become the parameters of all kinds of QoS controls in MANETs.2.2 protocol design in CQMMIn CQMM, the protocol designs aims at the full and free information exchange and cooperation among different protocol layers to avoid possible redundancy functions when maintaining the relative independence among different layers and the advantages of the modular architecture.Physical layer: Physical layer is responsible for modulation, transmission and receiving of data, and also the key to the size, the cost and the energy consumption of each node in MANETs. In CQMM, the design of physical layer is to choose the transmission media, the frequency range and the modulation algorithm wit the low cost, power and complexity, big channel capability and so on, according to the cost of implementation, energy constraint, and capability and QoS requirements from high layer.Data link layer: The layer is low layer in the protocol stack and can be divided into two sub-layers: logic link sub-layer and MAC sub-layer. Compared with high layers, data link layer can sense network status in MANETs earlier such as the change of channel quality, the network congestion and so on. Therefore, on the one hand data link layer can perform the basic QoS controls such as error control and management of communication channel. On the other one, the layer can be combined with high layers to establish, choose and maintain the routing faster, prevent the congestion of the network earlier, and choose appropriate transport mechanisms and control strategies for transport layer.Network layer: The design and implementation of network layer protocol in CQMM is to establish, choose and maintain appropriate routings by taking into consideration the power, the cache, the reliability of each node in a routing. QoS requirements of services from high layer such as the bandwidth and the delay, and implementation strategies oferror control in logic link sub-layer and the way of the channel management in MAC sub-layer.Transport layer: In CQMM, the protocol design of transport layer needs to be aware of both functions and implementation mechanism of lower layers such as the way of error control in data link layer, the means to establish, choose and maintain routing in the network layer, and QoS requirements from the application layer, to determine corresponding transmission strategies. In addition, the transport layer also needs to analyze all kinds of events from low layers such as the interrupt and change of the routing and the network congestion, and then respond properly to avoid useless sending data.Application layer: There are two different strategies in the design of the application layer: 1) differentiated services. According to the functions provided by the low layers applications are classed as the different ones with different priority levels. 2) Application-aware design. Analyze specific requirements of different applications such as the bandwidth, the delay and the delay twitter and so on, and then assign and implement the functions for each layer in the protocol stack according to the requirements.2.3 QoS Cooperation and Management in CQMMIn CQM, the core of QoS cooperation and management is that NSR acts as the exchange and share center of status information in protocol stack, and by the full exchange and share of network status among different protocol layers the management and scheduling of the network resources and the overall optimization of the network performances can be implemented effectively. The management and scheduling of the network resources, the cross-layer QoS cooperation and the overall optimization of the network performances.Management and scheduling of network resources: Network resources include all kinds of resources such as the cache, the energy and the queue in each node, and the communication channel among nodes and so froth. In CQMM, the management and scheduling of the network resources are not to the unified management and scheduling of the network resources and full utilization of limited resources in order to increase the QoS of all kinds of communication.QoS cooperation and control: In CQMM, all kinds of QoS controls and cooperation such as the rate adaptation, the delay guarantee and the congestion control and so on, are not implemented by each layer alone, but completed through the operation of all layers in the protocol stack. For example, the congestion in MANETs can be earlier prevented and controlled by the cooperation among different layers such as ACK from MAC sub-layer,the routing information and the loss rate and delay of package from network layer, and the information of rate adaptation in transport layer and so on.Performances Optimization: In CQMM, the optimization of the network performances aims to establish a network optimization model constrained by all layers in the protocol architecture and finds the “best”ways according to the model in order to improve the overall performances in MANETs.3. ANALYSIS OF CQMMPresent QoS models for MANETs can mainly be classed as a QoS model based on traditional divided-layer architecture DQMM and a cross-layer QoS model proposed by this paper CQMM. QoS model used by [1, 5-8] is to some extent extended on the basis of DQMM in nature. Here, we only compare CQMM with DQMM3.1 Information ExchangeDifferent protocol architecture and principle between CQMM lead to great differences in the means, the frequency, the time and the requirement of the information exchange, (see table 1)From Table 1, it can be seen that compared wit DQMM CQMM has some advantages: 1) more flexible information exchange. Neighboring layers can information by the interfaces between layers or NSR, and crossing layers may exchange information through NSR; 2) simpler transform in information format. Different layers can exchange information by NSR, so these layers only need to deal with the format transform between the layers and NSR;3)lower requirements. The protocol layers can read them in proper time Information from different protocol layers temporarily stored in NSR, so the layers exchanging information are not required to be synchronous in time;4) more accurate control. NSR in CQMM can store information of some time from the different layers, which is advantageous to master the network status and manage the network more accurately. However, these require higher information exchange frequencies among the different layers,, more processing time of each node, and more communication among them.。
AD9850介绍AD9850中文资料
精心整理第13章DDS 芯片AD9850/AD9851的设计13.1硬件设计信号源作为现代电子产品设计和生产中的重要工具,必须满足高精度、高速度、高分辨率等要求。
本章基于DDS(DirectDigitalSynthesis,直接数字频率合成)技术，采用AD9850DDS 芯片，采用F169单片机作为控制芯片，实现一种了简易信号发生器的设计，该信号发生器具有输出频率范围宽，可以输出正弦和方波两种波形，与键盘结合易于实现全数字化的设计。
（DDS ）80℃，采用28图13-3系统的10位后输入到DAC ，DAC 再输出两个互补的电流。
DAC 满量程输出电流通过一个外接电阻set R 调节，调节关系为set I =32(1.148V/RSET)，set R 的典型值是3.9K Ω。
将DAC 的输出经低通滤波后接到AD9850内部的高速比较器上即可直接输出一个抖动很小的方波。
其系统功能如图3-3所示。
AD9850在接上精密时钟源和写入频率相位控制字之后就可产生一个频率和相位都可编程控制的模拟正弦波输出，此正弦波可直接用作频率信号源或经内部的高速比较器转换为方波输出[23]。
在125MHz 的时钟下，32位的频率控制字可使AD9850的输出频率分辨率达0.0291Hz ；并具有5位相位控制位，而且允许相位按增量180，45，90，22.5，11.25或这些值的组合进行调整。
精心整理图13-3AD9850的内部结构13.1.2AD9850的控制字与控制时序AD9850有40位控制字，32位用于频率控制，5位用于相位控制。
1位用于电源休眠（Powerdown ）控制，2位用于选择工作方式。
这40位控制字可通过并行方式或串行方式输入到AD9850，在并行装入方式中，通过8位总线D0…D7将可数据输入到寄存器，在重复5次之后再在FQ_UD 上升沿把40位数据从输入寄存器装入到频率/相位数据寄存器（更新DDS 输出频率和相位），同时把地址指针复位到第一个输入寄存器。
电子信息工程专业英语翻译清华出版社English for IT and EE-12
noise in fingerprint images and deliver increased accuracy in
real-time.1
研发对于指纹图像中噪声更稳健 并能实时提供更高精度的算法是 重要的。
extraction algorithm relies heavily on the quality of the input fingerprint images.
18
7
In order to ensure that the performance of an automatic
fingerprint identification/verification system will be robust
with respect to the quality of the fingerprint images, it is
essential to incorporate a fingerprint enhancement algorithm in the minutiae extraction module.5
It is difficult to extract the minutiae points accurately when
the fingerprint is of low quality. Also this method does not
take into account the global pattern of ridges and furrows.
matching of the fingerprints. An input fingerprint is first
电子信息工程专业英语课文翻译(第3版)
电子信息工程专业英语教程第三版译者：唐亦林p32In 1945 H. W. Bode presented a system for analyzing the stability of feedback systems by using graphical methods. Until this time, feedback analysis was done by multiplication and division, so calculation of transfer functions was a time consuming and laborious task. Remember, engineers did not have calculators or computers until the '70s. Bode presented a log technique that transformed the intensely mathematical process of calculating a feedback system's stability into graphical analysis that was simple and perceptive. Feedback system design was still complicated, but it no longer was an art dominated by a few electrical engineers kept in a small dark room. Any electrical engineer could use Bode's methods find the stability of a feedback circuit, so the application of feedback to machines began to grow. There really wasn't much call for electronic feedback design until computers and transducers become of age.1945年HW伯德提出了一套系统方法，用图形化方法来分析反馈系统的稳定性。
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杭州电子科技大学信息工程学院毕业设计（论文）外文文献翻译
毕业设计（论文）题目扫描信号发生器
翻译题目关于AD9850的操作和应用理论系电子工程
专业电子信息工程
姓名刘息
班级06091811
学号06092020
指导教师张晓红
文献的第8页
操作和应用理论
AD9850的使用直接数字合成（DDS）技术，数控振荡器的形式，产生一个频率/相位敏捷正弦波。
数字正弦波通过内部高速10位的D / A转换器转换成模拟形式，板上的高速比较器提供了一个低抖动的TTL / CMOS兼容输出方波转化为模拟正弦波。
DDS技术是一种创新的电路架构，允许其输出频率的快速和精确的操纵下的全数字控制。
DDS也使增量选择输出频率非常高的分辨率，AD9850的允许0.0291赫兹与125 MHz参考时钟的输出频率的分辨率。
变更时，AD9850的输出波形是连续相位。
基本功能框图和信号流
AD9850的配置为时钟发生器如图4所示。
DDS的电路基本上是一个数字分频器功能由频率决定的增量决议参考时钟除以2N数位调谐字。
相位累加器是一个可变模计数器，增量存储在它的数量，每次接收到一个时钟脉冲。
当计数器溢出，它环绕，使相位累加器的输出连续。
频率调谐字设置计数器的模量，有效确定增量的大小（相位）被添加到在相位累加器的值在下一个时钟脉冲。
添加增量越大，越快，累加器溢出，导致在一个较高的输出频率。
AD9850的使用创新和专有算法，数学转换的14位相位累加器截断值的适当的COS值。
这种独特的算法，使用查表和DSP技术来执行此功能的小尺寸和低功耗，AD9850的，这有助于大大减少ROM。
输出频率的参考时
钟，AD9850的调谐字的关系，由公式 f out =()322
∆决定
Phase⨯
CLKIN
其中：
相位是32位控制字的值。
CLKIN是输入参考时钟频率。
f out 是输出信号的频率。
数字波输出正弦波的DDS块驱动器的10位D内部高速/ A转换器，重建模拟形式的正弦波。
该DAC已优化的动态性能和低突波能量，低抖动性能的AD9850的表现。
由于输出
第9~12页
AD9850的采样信号，其输出频谱如下Nyquist采样定理。
具体来说，其输出频谱包含的基本加锯齿信号（图像）是参考时钟频率的倍数 选定的输出频率。
一个采样频谱的图形表示，锯齿的图像，如图5所示。
在这个例子中，参考时钟为100 MHz，输出频率为20 MHz。
可以看出，锯齿的图像是非常突出，具有一个相对高的能量水平，且由sin（x）/ x的量化D / A转换输出滚降决定。
事实上，根据FO /参考时钟关系，第一锯齿图像可以在3dB 以下。
一个低通滤波器一般放置在D/ A转换器的输出端和比较器的输入端之间，以进一步抑制锯齿图像的影响。
显然，必须考虑到选定的输出频率与参考时钟频率的关系，以避免输出异常。
要AD9850作为时钟发生器，就必须限制选定的输出频率小于参考时钟频率<33％，从而使产生锯齿的信号接近或者在我们需要的输出波段（一般DC选定的输出频率）的范围之内。
这种做法简化了外部滤波器的复杂性（和成本）以及时钟发生器应用的要求。
AD9850的参考时钟频率最低限制为1 MHz的。
当超过最低时钟速率的阈值时该器件的内部电路会感知到，并自动把自己设置到掉电模式。
在这种状态下，如果时钟频率再次超过阈值，设备就恢复正常运行。
这种关机模式防止泄漏到设备动态寄存器的电流过大。
D / A转换输出和比较器输入可以作为差分信号以所需的任何方式灵活配置给终端系统来实现的目标。
AD9850的典型应用是与单端输出/输入的模拟信号和一个单一的低通滤波器，组成代差的DAC输出来作为比较参考中点，如图1所示。
在AD9850的编程
AD9850的包含一个40位寄存器，用于编程和断电功能。
这个寄存器可以装在并行或串行模式。
在并行加载模式，寄存器通过8位总线加载；完整的40位字需要5个8位字的迭代。
W_CLK和FQ_UD信号是用来处理和加载寄存器。
FQ_UD负载上升沿（最多）40位到设备的数据和地址指针复位到第一个寄存器的控制字。
随后W_CLK上升沿加载8位数据，字[7:0]，将指针移动到下一个寄存器。
经过5次加载，W_CLK边缘会被忽略，直到
第一个寄存器得到复位或FQ_UD上升边缘复位的地址指针。
在串行加载模式下，在随后的上升沿，W_CLK通过引脚25（D7）转移的40位的编程信息，1位数据。
40位的信息转移通过之后，一个FQ_UD的脉冲被请求来更新输出频率（或相位）。
表III 所示的是数据和控制字的功能分配。
图6到图12时序图显示的是输出频率和/或相位的更新，设备的复位，电源的开/关操作的详细时序。
注：有特定的控制代码是用于出厂检验的目的，它会使AD9850的暂时无法使用。
用户必须采取谨慎的预防措施，不要输入表二所列的代码。
第13页
PCB布局信息
AD9850/CGPCB和AD9850/FSPCB评估板（图15至18）是AD9850的典型的功能实现，和频率高/高分辨率的设计和布局做法的使用举例。
包含了AD9850的印制电路板，应该是一个有专用电源和接地的多层电路板。
电源和接地的区域应该不能有蚀刻的
痕迹，否则会导致板子断路。
建议多层电路板的顶层要包含一个的内空的接地区域给贴片器件。
为了AD9850的最佳效果应该把单独的模拟和数字系统接地连接在一起。
不要把数字线在有耦合噪音的区域布线。
AD9850的电源走线应该尽可能宽以提供一个低阻抗，从而减少供电线路毛刺的影响。
像时钟信号这样的快速跳变的信号，应该与接地屏蔽开来，以避免噪声辐射影响到电路板上的其他
部分。
数字和模拟信号走线避免交叉。
板子对面的布线应该彼此成直角。
这可以减少电路板的馈通效应。
在可能的情况下使用微带技术。
良好的去耦也是一个重要的考虑因素。
AD9850的模拟（AVDD）和数字（DVDD的）的部分是独立分别固定的，以最大限度地减少设备的模拟和数字部分之间的耦合。
所有模拟和数字电源都应该分别用高品质的陶瓷电容器来去耦合之后，然后连接到AGND（模拟地）和DGND （数字地）。
为了达到最好的去耦电容的性能，他们应放在尽可能接近的设备，最好是正对着的设备。
在一个由共同的电源来驱动的AVDD和DVDD的AD9850的电源系统里，建议最好可以使用该系统的AVDD电源。
ADI公司的应用工程支持部可以回答关于接地和PCB布局的更多其他问题。
打电话给1-800-ANALOGD或者在/ DDS的网址与我们联系。
评估板
为了方便台式分析设备的执行情况和为PCB布局作参考，有两个版本AD9850的评估板。
AD9850/FSPCB用于设备的应用主要是作为频率合成器。
这个版本是关于AD9850的内部D / A转换输出和一个50欧姆频谱分析仪的连接；输入上的内部比较AD9850的被测设备未启用（图15是AD9850/FSPCB电气原理）。
AD9850/CGPCB是以作为时钟发生器的模式来应用在设备中的。
它通过一个单端42 MHz的低通5极椭圆滤波器连接AD9850的DAC输出与内
部比较器输入。
这种模式有利于AD9850的作为频率和相位可变的时钟源设备的输出比较器的访问（见图17 电气原理图AD9850/CGPCB SCHE-MATIC）。
关于AD9850评估板的两个版本都是被设计接口到PC的并行打印机端口的。
操作系统软件在微软系统下运行良好，而且可以直观格式的观测设备的操控制功能和性能。
评估板提供的3.5英寸软盘中包含可执行文件的加载和显示AD9850的功能选择画面。
评估板可工作在3.3 V或5 V电源下。
评估板在工厂设置成外部参考时钟输入；如果主板上的晶体时钟源是启用的，只要删除R2。