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DDR3硬件电路设计——经验

DDR3硬件电路设计——经验随着CPU 性能不断提高，我们对内存性能的要求也逐步升级。

不可否认，紧紧依高频率提升带宽的DDR迟早会力不从心，因此JEDEC 组织很早就开始酝酿DDR2 标准，加上LGA775接口的915/925以及最新的945等新平台开始对DDR2内存的支持，所以DDR2内存将开始演义内存领域的今天。

DDR2 能够在100MHz 的发信频率基础上提供每插脚最少400MB/s 的带宽，而且其接口将运行于1.8V 电压上，从而进一步降低发热量，以便提高频率。

此外，DDR2 将融入CAS、OCD、ODT 等新性能指标和中断指令，提升内存带宽的利用率。

从JEDEC组织者阐述的DDR2标准来看，针对PC等市场的DDR2内存将拥有400、533、667MHz等不同的时钟频率。

高端的DDR2内存将拥有800、1000MHz两种频率。

DDR-II内存将采用200-、220-、240-针脚的FBGA封装形式。

最初的DDR2内存将采用0.13微米的生产工艺，内存颗粒的电压为1.8V，容量密度为512MB。

内存技术在2005年将会毫无悬念，SDRAM为代表的静态内存在五年内不会普及。

QBM与RDRAM内存也难以挽回颓势，因此DDR 与DDR2共存时代将是铁定的事实。

PC-100的“接班人”除了PC一133以外，VCM(VirXual Channel Memory）也是很重要的一员。

VCM即“虚拟通道存储器”，这也是目前大多数较新的芯片组支持的一种内存标准，VCM内存主要根据由NEC公司开发的一种“缓存式DRAM”技术制造而成，它集成了“通道缓存”，由高速寄存器进行配置和控制。

在实现高速数据传输的同时，VCM还维持着对传统SDRAM的高度兼容性，所以通常也把VCM内存称为VCM SDRAM。

VCM与SDRAM 的差别在于不论是否经过CPU处理的数据，都可先交于VCM进行处理，而普通的SDRAM 就只能处理经CPU处理以后的数据，所以VCM要比SDRAM 处理数据的速度快20%以上。

DDR3 硬件设计和 Layout 设计【中为电子科技工作室.】

DDR3硬件设计和Layout设计译自飞思卡尔官方文档Hardware and Layout Design Considerations for DDR3 SDRAMMemory Interfaces目录1 设计检查表 (3)2 终端匹配电阻功耗计算 (8)3 VREF (8)4 VTT电压轨 (8)5 DDR布线 (9)5.1 数据线— MDQ[0:63], MDQS[0:8], MDM[0:8], MECC[0:7] (9)5.2 Layout建议 (10)6 仿真 (12)7 扩展阅读 (13)8 历史版本 (13)9 声明 (13)这是一篇关于DDR3 SDRAM IP core的设计向导，出自飞思卡尔，为了实现PCB的灵活设计，我们可以采用合适的拓扑结构简化设计时的板级关联性。

飞思卡尔强烈推荐系统/板级工程师在PCB制板前进行设计验证，包括信号完整性、时序等等。

1 设计检查表如表1，罗列了DDR设计检查清单，推荐逐一检查，并在最右侧作出决策。

MDQSx/x。

DDR3数据线在做蛇形走线等长匹配时，应该保证蛇形走线间至少有25mil 的间距。

2 终端匹配电阻功耗计算DDR的地址线和控制线会有灌电流和拉电流经终端电阻R T流过，那么该电阻的功耗计算如下：Power = x R T = x (47Ω) = 7.5mW根据上述，我们需要选择高达1/16W的电阻。

另外，V TT电流的计算请参看第4节。

3 V REFV REF电流需求相对较小，低于3mA。

V REF是为控制器和DDR芯片的差分接收器提供0.75V 的直流偏置（V DD/2），V REF的误差或噪声可能会在总线上引起时序错误、不期望的抖动和误动作等。

为避免上述问题，V REF噪声必须控制在JEDEC要求范围内，因此，V REF和V TT不能在同一平面，因为DRAM的V REF对V TT的噪声很敏感。

但是，VREF和VTT的产生必须经由同一个电源产生，以保证高度统一，所以每一个VREF要放置合适的去耦电容（包括控制器、每一个DIMM/DDR芯片、V REF电源），并且做到布局布线简单，预防潜在问题。

xilinx平台DDR3设计教程之设计篇_中文版教程3

现在你应该已经看完了仿真和综合教程我们进入了设计篇，说白了就是讲一讲DDR IP的用户接口是怎么用的用户接口在哪里？请你打开下面这个目录里面的example_top.v这也就是你综合出来工程的顶层文件了我们来理一理这个文件的结构吧开头部分，全是介绍，你删了都关系然后是各种参数的设定这里有bank，row，column，rank，等等各种设置其实你不用动它们这些都是你之前选条子的时候已经选好了的不记得自己选什么条子了？乖乖，你不如再翻翻仿真教程先？各种仿真延迟参数也跟你选的条子有关你也别管了我都不管这些和DDR条子的各种接口你要知道，用户接口是个内部接口，你这里当然看不到了。

如果之前选了“use system clock”的话这里就看不到clk_ref相关的参考时钟管脚了。

这里顺便提一下column和row地址是在ddr3_addr里面复用的。

column一般是10bit宽度。

row一般14-16bit宽度。

ddr3_ba是选bank的，一般是3bit宽度，对应8个bank。

ddr3_cs_n是选rank的，有几个rank就有几个bit的宽度，因为要考虑啥都不选的情况，和之前几个参数不一样的。

各种参数配置相互之间的关系换算，选择继续和你没有关系作为设计者的你，可以继续无视这些部分各种wire定义你有兴趣研究不？我是没兴趣终于开始实例化DDR3了看见DDR3 右边的#号了没？这说明下面这些都不是管脚，而是配置用的参数。

你继续不用改这都六百多行了，你还是啥也不用改。

唉呀妈呀，DDR3实例化的实体总算找到了，就叫做u_DDR3找到没，我这里是747行接下来你要改动的，其实只有区区几行那就是769行Application interface开始的几个ports从770行的app_addr开始到775行的app_wdf_wren结束一共六行此外，因为你之前选了data mask，所以790行有个app_wdf_mask这一行的赋值你可以直接改成零。

Design Guide for Two DDR3-1066 UDIMM Systems

Technical NoteDesign Guide for Two DDR3-1066 UDIMM SystemsIntroductionDDR3 memory systems are very similar to DDR2 memory systems. One noteworthydifference is the fly-by architecture used in DDR3 JEDEC-standard modules. Dependingon the intended market for the finished product, the memory buses will vary, and thememory system support requirements will range from point-to-point topologies tolarge, multiple registered DIMM topologies.This design guide is intended to assist board designers in developing and implementingtheir products. The document focuses on memory topologies requiring two unbufferedDIMM devices operating at a data rate of 1066Mb/s and two variations of the addressand command bus. The first design variation discussed is a system with one DIMM percopy of the address and command bus using 1T clocking. The second design variation isa system with two DIMM devices on the address and command bus using 2T clocking.The first section of this technical note outlines a set of board design rules, providing astarting point for a board design. The second section details the calculation process fordetermining the portion of the total timing budget allotted to the board interconnect.The intent is that board designers will use the first section to develop a set of generalrules and then, through simulation, verify their designs in the intended environment.Fly-By ArchitectureDesigners who build systems using unbuffered DIMM devices can implement theaddress and command bus using various configurations. For example, some controllershave two copies of the address and command bus, so the system can have one or twoDIMM devices per copy, but no more than two DIMM devices per channel. Further, theaddress bus can be clocked using 1T or 2T clocking. With 1T clocking, a new commandcan be issued on every clock cycle; 2T timing will hold the address and command busvalid for two clock cycles. This reduces the efficiency of the bus to one command per twoclocks, but it substantially increases the amount of setup and hold time available for theaddress and command bus. The data bus remains the same for the address bus varia-tions.DDR3 modules use faster clock speeds than earlier DDR technologies, making signalquality extremely important. For improved signal quality, the clock, control, command,and address buses have been routed in a fly-by topology, where each clock, control,command, and address pin on each DRAM is connected to a single trace and termi-nated. (Other topologies use a tree structure, where termination is off the module nearthe connector.) Inherent to fly-by topology, the timing skew between the clock and DQSsignals can easily be accounted for using the write-leveling feature of DDR3.PDF: 09005aef83a0af6b/Source: 09005aef83657fb2 Micron Technology, Inc., reserves the right to change products or specifications without notice. tn4108_ddr3_design_guide.fm-Rev. B 1/11 EN©2009 Micron Technology, Inc. All rights reserved.The address, command, and control signals are routed on the module with fly-by archi-tecture. As illustrated throughout this technical note, the input signal lines are termi-nated on the module, and further termination is not required. For example, as shown inFigure1 and Figure2 on page3, the V TT terminating resistors are at the end of the fly-bychannel.Figure 1: DDR3-1066 Two-UDIMM Topology – 1T Address and Command BusFigure 2: DDR3-1066 Two-UDIMM Topology – 2T Address and Command BusNote that a timing skew exists between the DRAM controller and the various DRAMdevices on the DIMM, and the DRAM controller must account for the timing skews.DDR3 modules support write leveling, which is intended to help determine the timingskews. For an in-depth discussion of write-leveling features, refer to Micron’s DDR3 datasheets that discuss write leveling.DDR3 Signal GroupsThe signals that compose a DDR3 memory bus can be divided into four unique groups,each with its own configuration and routing requirements.•Data group: Data strobe DQS[8:0], data strobe complement DQS#[8:0], data maskDM[8:0], data DQ[63:0], and check bits CB[7:0] (x72)•Address and command group: Bank addresses BA[2:0]; addresses A[15:0]; andcommand inputs, including RAS#, CAS#, and WE#•Control group:Chip select S#[3:0], clock enable CKE[3:0], on-die terminationODT[3:0], and RESET#0•Clock group: Differential clocks CK[3:0] and CK#[3:0]Board StackupA two-DIMM DDR3 channel can be routed on a four-layer board. The layout should usecontrolled impedance traces of Z O = 40Ω (±10%) characteristic impedance. An exampleboard stackup is shown in Figure3 on page4. The trace impedance is based on a 5-mil-wide trace and 0.5oz copper (Cu) with a dielectric constant of 4.2 for the FR4 prepregmaterial. For this stackup, it is assumed that the 0.5oz Cu on the outer layers is plated fora total thickness of 2.1 mils. Other solutions exist to achieve a 40Ω characteristic imped-ance, so board designers should work with their PCB vendors to specify a stackup.TN-41-08: Design Guide for Two DDR3-1066 UDIMM SystemsDDR3 Command and Address Voltage Margin and Slew Rate Figure 3: Sample Board StackupDDR3 Command and Address Voltage Margin and Slew RateThe primary difference between DDR2 and DDR3 module command, address, andcontrol signals is fly-by topology with impedance matching. Impedance matching isrequired for proper fly-by operation.With a single DIMM placed at the end of the motherboard bus, the system is matchedthroughout. The driver impedance could be as much as 40Ω, but is generally set a littlelower; the motherboard is routed at 40Ω; and the DIMM lead-in, which is about 4 inches,is routed at 40Ω. DRAM-to-DRAM routing is 60Ω, but when the additional capacitanceof the DRAM devices is taken into account, this lead-in becomes an effective 40Ωimpedance. The termination resistor to V TT is 39Ω. This configuration provides fast slewrates and clean edge transitions due to the minimal number of reflections.For configurations with 2 DIMMs on a channel, a mismatch occurs at the first DIMM.This mismatch will look like 20Ω impedance and there will be a reflection toward thedriver. If the driver impedance is 40Ω, the reflection will terminate at the controller.When the signal sees the 20Ω impedance, the amplitude drops by about 50%. After thefirst DIMM, the impedances are matched, and there will be little reflection from thetermination.Thus the primary effect of using a second DIMM is mostly amplitude reduction. Therewill also be a slight timing shift and some slew rate change. The slew rate change is dueto the amplitude change, not a rise-time change. Rise time is based on a percentage ofthe total swing, whereas slew rate is based on the amplitude change.The following figures provide examples of the slew rate change for a two-DIMM deviceversus a one-DIMM device. The slew rate changes are primarily associated with theamplitude change due to voltage division rather than the capacitive loading that domi-nated in DDR2. Figure4 shows the waveform for the third DRAM on a single DIMM;Figure5 compares the waveform for the third DRAM on the first DIMM of a two-DIMMdevice and the waveform for the third DRAM on the second DIMM of a two-DIMMdevice.Figure 4: U3, SR, 1T at 1066Figure 5: U3, DR, 1T at 1066Rank 1Rank 0Address and Command Signals for 2T ClockingOn a DDR3 memory bus, the address and command signals are unidirectional signalsdriven by the memory controller. The address and command signals are captured at theDRAM using the memory clocks. For a system with two unbuffered DIMM devices perchannel, signaling differs from that of a device with one unbuffered DIMM per channel.This difference is illustrated in Figure4, compared with Figure5 on page5 and Figure6on page6. The reduced slew rate makes it difficult, if not impossible, to use 1T timingand meet the setup and hold times at the DRAM.To address this issue, the controller can use 2T address timing—increasing the timeavailable for the address command bus by one clock period, as shown in Figure6. ForDDR3-1066, using 2T on the address and command signals, the address and commandbus runs at a maximum fundamental frequency of 266 MHz.Note that S#, ODT, and CKE timings do not change between 1T and 2T addressingbecause they carry only half of the load carried by the other command signals.Figure 6: U3, DR, R0, 2T at 10662T Address and Command Routing RulesIt is important to reference address and command lines to a solid power plane or to aground plane, preferably to a solid V DD power plane. V DD is the 1.5V supply that alsosupplies power to the DRAM on the DIMM. On a four-layer board, the address andcommand lines are typically routed on the second signal layer and referenced to a solidpower plane. The system address and command signals should be power referencedover the entire bus to provide a low-impedance current return path.DDR3 unbuffered DIMM devices also reference the address and control signals to V DD tomaintain the power reference onto the module. The address and command signalsshould be routed from the controller to the first DIMM, away from the data groupsignals. Because address and command signals are captured at the DIMM using theclock signals, they must maintain a length relationship to the clock signals at the DIMM.Unlike DDR2, where external V TT termination resistors are required, DDR3 modulesincorporate on-board V TT termination resistors, as shown in Figure7. This change wasadded to support fly-by architecture. All inputs, including the clock, have fly-by topolo-gies; the data bus pins are directly connected to the DRAM controller. A possible designconsideration would be to vary the topology shown in Figure 7 by bringing the addressand control busses as far as the length B + C/2 and tie-off to each DIMM from the C/2point.Figure 7: DDR3 Address and Command Signal Group 2T Routing TopologyTable 1: Address and Command Group 2T Routing RulesLengthA = Obtain from DRAM controller vendor (“A” is the length from the die pad to the ball on the ASI C package)B = 1.9 to 4.5 inchesC = 0.425 inchesTotal: A + B + C = 2.5 to 5.0 inchesLength Matching±20 mils of memory clock length at the DIMM1TraceTrace width = 5 mils: target 40Ω impedanceTrace space = 12 to 15 mils, reducing to 11.5 mils between the pins of the DIMMTrace space from DIMM pins = 7 milsTrace space to other signal groups = 20 to 25 milsNotes: 1.This value is controller-dependent.Parallel/Pull-Up Resistor (V TTR) Termination ResistorThe V TT supply is still required on the motherboard. However, the external paralleltermination resistors required for DDR2 are not required for DDR3 JEDEC-compliantmodules; the V TT terminating resistors are built onto the module.Address and Command Signals for 1T ClockingOn a DDR3 memory bus, the address and command signals are unidirectional signalsdriven by the memory controller. The address and command signals are captured at theDRAM using the memory clocks. For a system with two unbuffered DIMM devices perchannel, the signaling differs from a device with one unbuffered DIMM per channel (seeFigure4 through Figure6 starting on page5). The reduced slew rate makes it difficult, ifnot impossible, to use 1T timing and meet the setup and hold times at the DRAM.To address this issue, the controller can use 2T address timing—increasing the timeavailable for the address command bus by one clock period, as shown in Figure6.To increase the timing margin, loading on the address and command bus must bereduced. Some controllers provide two copies of the address and command bus. Onecopy is connected to each DIMM, effectively reducing the total maximum load on thebus to one DIMM. With reduced loading, the timing and voltage margin is increased to apoint that 1T address bus timing is generally achievable (see Figure4 on page5).Address and command 1T signal-group routing topology is shown in the block diagramin Figure8 on page9. For DDR3-1066 using 1T on the address and command signals, theaddress and command bus runs at a maximum fundamental frequency of 533 MHz.Adding an extra copy of address and command signals helps improve signaling, but loadreduction alone may not be enough to comply with setup and hold times for 1T signals. 1T Address and Command Routing RulesIt is important to reference address and command lines to a solid power plane or to aground plane.On a four-layer board, the address and command lines are typically routed on thesecond signal layer and referenced to a solid power plane. The system address andcommand signals should be power referenced over the entire bus to provide a low-impedance current return path.The address and command signals should be routed away from the data group signals,from the controller to the first DIMM. Because address and command signals arecaptured at the DIMM using the clock signals, they must maintain the length relation-ship to the clock signals at the DIMM.Figure 8: DDR3 Address and Command Signal Group 1T Routing TopologyTable 2: Address and Command Group 1T Routing RulesLengthA = Obtain from DRAM controller vendor (“A” is the length from the die pad to the ball on the ASI C package)B = 1.9 to 4.5 inchesC = 0.425 inchesTotal: A + B + C = 2.5 to 5.0 inchesLength Matching±20 mils of memory clock length at the DIMM1TraceTrace width = 5 mils: target 40Ω impedanceTrace space = 12 to 15 mils, reducing to 11.5 mils between the pins of the DIMMTrace space from DIMM pins = 7 milsTrace space to other signal groups = 20 to 25 milsNotes: 1.This value is controller-dependent.Setup and Hold DeratingSetup and hold times require derating whenever the slew rate is faster than 1 V/ns. Thederating factors can be obtained from the device data sheet. Slew rates slower than1V/ns generally do not require derating; however, derating can reclaim some timemargin.TN-41-08: Design Guide for Two DDR3-1066 UDIMM SystemsControl SignalsAdditionally, when developing a timing budget, derating the setup and hold times toV REF points is necessary to ensure that all components are using the same timing refer-ence points.Parallel/Pull-Up Resistor (V TTR) Termination ResistorThe external parallel termination resistors that were required for DDR2 are not requiredfor DDR3 JEDEC-compliant modules; the V TT terminating resistors are built onto themodule.Control SignalsThe control signals in a DDR3 system are different from the address signals in severalways. First, the control signals need to use 1T timing. Second, each DIMM rank (alsocalled rank) has its own copy of the control signals. Figure9 on page10 shows a blockdiagram of the topology used for the control signals.The control signals in a DDR3 system differ from the address signals in several ways.First, the control signals use 1T timing. Second, each DIMM rank (also called rank) hasits own copy of the control signals. Control signal-group routing topology is shown in theblock diagram below.Figure 9: DDR3 Control Signal Group Routing Topology ArrayODTLike DDR2, DDR3 supports on-die termination (ODT) signals. For DDR3 modules, ODTprovides more ranges to select from, and also supports dynamic ODT. For a detaileddiscussion of dynamic ODT, refer to Micron’s DDR3 data sheets.In DDR3 devices, ODT signals are used to control the termination of the data group signals. DDR3 does not need the external serial and parallel termination resistors on the data group signals used in earlier DDR systems. The enhanced DDR3 ODT termination scheme terminates signals via internal termination resistors in the DRAM device and in the controller. ODT signals are used to turn termination on or off in the DRAM (ODT is enabled or disabled using the mode registers), depending on the type of bus transition and the system load.ODT SimulationsSimulations were performed to define ODT settings and values. Table 3 on page 11 shows write simulations run with ODT values of 40Ω, 60Ω, and 120Ω for the active slot and 20Ω, 30Ω, and 40Ω for the standby slot. Table 4 on page 12 shows read simulations run with controller ODT values of 60Ω, 57Ω, 150Ω, and 300Ω; and ODT values at 20Ω, 30Ω, 40Ω, 60Ω, and 120Ω.The ODT scheme shown in Table 5 on page 12 provides an alternative method for dual rank (DR) modules. Using dynamic ODT provides tighter ODT control. Simulations showed that up to 20ps of additional margin is possible using dynamic ODT.No single ODT value delivered the best maximum aperture and voltage margin, with the lowest jitter. So the results were reviewed and the best overall value was selected. The ODT values provided in this technical note are only recommendations and provide a good starting point for analyzing a system.For example, two similar designs might use different ODT values based on specificdesign needs; one might need greater voltage margin, the other more timing margin. If a DRAM controller supplier recommends an ODT scheme that differs from thosepresented here, designers should follow the supplier’s recommendation for ODT use.Notes:1.Made possible via dynamic ODT.Table 3:DDR3 ODT Control for Write SimulationsConfiguration Write To DRAM Controller Slot 1Slot 2Slot 1(DIMM 1)Slot 2(DIMM 2)Rank 1Rank 2Rank 1Rank 2Dual rank Dual rank Slot 1ODT off 120ΩODT off ODT off 30ΩSlot 2ODT off ODT off 30Ω120ΩODT off Dual rank Single rank Slot 1ODT off 120ΩODT off 20Ωn/a Slot 2ODT off ODT off 20Ω120Ω1n/a Single rank Dual rank Slot 1ODT off 120Ω1n/a ODT off 20ΩSlot 2ODT off 20Ωn/a 120ΩODT off Single rank Single rank Slot 1ODT off 120Ω1n/a 30Ωn/a Slot 2ODT off 30Ωn/a 120Ω1n/a Dual rank Empty Slot 1ODT off 40ΩODT off n/a n/a Empty Dual rank Slot 2ODT off n/a n/a 40ΩODT off Single rank Empty Slot 1ODT off 40Ωn/a n/a n/a EmptySingle rank Slot 2ODT offn/an/a40Ωn/aNotes:1.Made possible via dynamic ODT.Notes:1.This value is controller-dependent.Table 4:DDR3 ODT Control for Read SimulationsConfiguration Write To DRAM ControllerSlot 1Slot 2Slot 1(DIMM 1)Slot 2(DIMM 2)Rank 1Rank 2Rank 1Rank 2Dual rank Dual rank Slot 175ΩODT off ODT off ODT off 30ΩSlot 275ΩODT off 30ΩODT off ODT off Dual rank Single rank Slot 175ΩODT off ODT off 20Ωn/a Slot 275ΩODT off 20ΩODT off n/a Single rank Dual rank Slot 175ΩODT off n/a ODT off 20ΩSlot 275Ω20Ωn/a ODT off ODT off Single rank Single rank Slot 175ΩODT off n/a 30Ωn/a Slot 275Ω30Ωn/a ODT off n/a Dual rank Empty Slot 175ΩODT off ODT off n/a n/a Empty Dual rank Slot 275Ωn/a n/a ODT off ODT off Single rank Empty Slot 175ΩODT off n/a n/a n/a EmptySingle rankSlot 275Ωn/an/aODT offn/aTable 5: Alternative DDR3 ODT Control for Dual Rank Write SimulationsConfiguration Write To DRAM Controller Slot 1Slot 2Slot 1(DIMM1)Slot 2(DIMM2)Rank 1Rank 2Rank 1Rank 2Dual rankDual rankSlot 1Rank 1ODT off 120Ω1ODT off 30ΩODT off Rank 2ODT off ODT off 120Ω30ΩODT off Slot 2Rank 1ODT off 30ΩODT off 120Ω1ODT off Rank 2ODT off30ΩODT offODT off120ΩTable 6:Control Group Routing RulesLengthA = Obtain from DRAM controller vendor (“A” is the length from the die pad to the ball on the ASI C package)B = 1.9 to 4.5 inchesC = 0.425 inchesD = 0.2 to 0.55 inchesTotal: A + B + C = 2.5 to 6.0 inches Length Matching±20 mils of memory clock length at the DIMM 1TraceTrace width = 5 mils: target 40Ω impedanceTrace space = 12 to 15 mils, reducing to 11.5 mils between the pins of the DIMM Trace space from DIMM pins = 7 milsTrace space to other signal groups = 20 to 25 milsControl Signal Routing RulesSimilar to the address signals, the control signals must be referenced to a solid powerplane or to a ground plane. On a four-layer board, the control signals are typically routedon the bottom signal layer and referenced to a solid power plane. The system controlsignals must be power referenced over the entire bus to provide a Low-Z current returnpath. Unlike address signals, control signals are routed point-to-point from thecontroller to the DIMM.The control signals do not require any series or parallel resistance. The control signalsmust be routed with clearance from the data group signals, from the controller to thefirst DIMM. Because the control signals are captured at the DIMM using the clocksignals, they must maintain the length relationship to the clock signals at the DIMM. Parallel/Pull-up Resistor (V TTR) Termination ResistorThe external parallel termination resistors that were required for DDR2 are no longerrequired with DDR3 JEDEC-compliant modules because the V TT terminating resistorsare built onto the module.Data SignalsIn a DDR3 system, the data is captured by the memory and the controller using the datastrobe (DQS and DQS#) rather than the clock. The data strobe complement (DQS#) mustbe routed as a differential pair with the data strobe (DQS). To achieve the double datarate, data is captured on each crossing point of the DQS/DQS# pairs. Each eight bits ofdata has an associated data strobe (DQS and DQS#) and data mask (DM) bit. Becausethe data is captured off the strobe, the data bits associated with the strobe must belength-matched closely to their strobe bit. This grouping of data and data strobe isreferred to as a byte lane. The length matching among byte lanes is not as tight as it iswithin the byte lane. Figure10 shows the signals in a single-byte lane and the bustopology for the data signals; Table7 shows the data and data strobe byte-lane groups.Figure 10: DDR3 Data Byte Lane Routing and Bus TopologyTable 7: Data and Data Strobe Byte Lane GroupsData Data Strobe Data Strobe Complement Data MaskDQ[7:0]DQS0DQS#0DM0DQ[15:8]DQS1DQS#1DM1DQ[23:16]DQS2DQS#2DM2DQ[31:24]DQS3DQS#3DM3DQ[39:32]DQS4DQS#4DM4DQ[47:40]DQS5DQS#5DM5DQ[55:48]DQS6DQS#6DM6DQ[63:56]DQS7DQS#7DM7C B[7:0]DQS8DQS#8DM8Data Signal Routing RulesIt is important that the data lines be referenced to a solid ground plane. These high-speed data signals require a good ground return path to avoid signal quality degradationdue to inductance in the signal return path. The system data signals should be ground-referenced from the memory controller to the DIMM connectors, and from DIMMconnector to DIMM connector to provide a Low-Z current return path. This is accom-plished by routing the data signals on the top layer for the entire length of the signal. Thedata signals should not have any vias. If this cannot be avoided, then the time delayassociated with the via should be accounted for in the trace length.Table 8: Data Group Routing RulesLengthA = Obtain from DRAM controller vendor (“A” is the length from the die pad to the ball on the ASI C package)B = 1.9 to 4.5 inchesC = 0.425 inchesTotal: A + B + C = 2.5 to 5.0 inchesLength Matching in Data/Strobe Byte Lane±20 mils data strobe, data strobe complement1100 mils for each byte laneLength Matching in Byte Lane to Byte LaneNot required; de-skewing is required because of fly-by topology on the address command busTraceDataTrace width = 7.9 mils: target 40Ω impedanceTrace space = 11.8 mils minimumTrace space from DIMM pins = 7 milsTrace space to other signal groups = 12 milsDifferential StrobeTrace width = 7.9 mils: target 40Ω impedanceTrace space = 4 mils between pairsTrace space to other signals = 15.8 milsNotes: 1.Differential signals have a faster propagation time than single-ended signals. If the datasignals are routed slightly shorter than the data strobe, the data strobe signal will arrive atthe DRAM in the center of its associated data signals. Because the propagation delay canvary with design parameters, simulating these signals is recommended.Clock SignalsThe memory clocks CK[4:0] and CK#[4:0] are used by the DRAM on a DDR3 bus tocapture the address and command data. Unbuffered DIMM devices require two clockpairs per DIMM. Some DDR3 memory controllers drive all these clocks, and othersrequire an external clock driver to generate these signals. This technical note assumesthat the memory controller will drive the four clock pairs required for a two-DIMMunbuffered system. Clocks are not terminated to V TT like the address signals of a DDR3bus. The clocks are differential and must be routed as a differential pair. Each clock pairis differentially terminated on the DIMM. Figure11 on page16 illustrates the routingtopology used for the clocks, but in this example, only one of the two clock pairsrequired per DIMM is shown.Figure 11: DDR3 Clock Signal Group Routing TopologyClock Signal Routing RulesThe clocks are routed as a differential pair from the controller to the DIMM. The clocksare used to capture the address and control signals at the DRAM on the DIMM. As aresult, the clocks must maintain a length relationship to the address and control signalsat the DIMM to which they are connected. Most controllers have the ability to prelaunchthe address and control signals; this feature is used to center the clock in the addressvalid eye. Prelaunching the address and control signals is required because the clocksare loaded lighter than the address signals, and as a result have less flight time from thecontroller to the DRAM on the DIMM. Differentially routed signals also have a shorterflight time than single-ended signals. This effect causes the clock signals to arrive at theDRAM even sooner than the address, command, and control signals; thus, the differen-tial flight time is a little faster than the single-ended signals to the first DRAM based onthe differential coupling. To compensate for the difference in propagation delay, it isrecommended to route the clock signals slightly longer than the address, command, andcontrol signals.TN-41-08: Design Guide for Two DDR3-1066 UDIMM SystemsDDR3 Memory Power Supply RequirementsDDR3 Memory Power Supply RequirementsA DDR3 bus implementation requires three separate power supplies. The DRAM and the memory portion of the controller require a 1.5V supply. The 1.5V supply provides power for the DRAM core and I/O, and at a minimum, the I/O of the DRAM controller. The second power supply is V REF , which is used as a reference voltage by the DRAM and the controller. The third power supply is V TT , the bus termination supply. Table 10 on page 18 summarizes the tolerances for each of these supplies.V REF Voltage and Layout RecommendationsDDR3 supports a separate V REF for address, command, and control pins (V REFCA ) and for the data bus (V REFDQ ). V REFCA and V REFDQ may come from the same power source, but they should be routed to and then decoupled separately at the DDR3 DIMM. Note that the term V REF applies to both V REFCA and V REFDQ .The memory reference voltage, V REF , requires a voltage level of half V DD /V DDQ with the tolerance shown in Table 10. V REF can be generated using a simple resistor divider with 1% or better accuracy. V REF must track half V DD /V DDQ over voltage, noise, and tempera-ture changes. Peak-to-peak AC noise on V REF must not exceed ±2% V REF(DC). To ensure a solid DDR3 design, it is imperative that the V REF noise, including crosstalk, is kept to a minimum.When implementing V REF , consider the following layout recommendations:•Use a 30 mil trace between the decoupling cap and the destination.•Maintain a 15 mil clearance from other nets.•Simplify implementation by routing V REF on the top signal trace layer.•Isolate V REF and/or shield with ground.•Decouple using distributed 0.01µf and 0.1µf capacitors by the regulator, controller, and DIMM slots. Place one 0.01µf and one 0.1µf near the V REF pin of each DIMM. Place one 0.1µf near the source of V REF , one near the V REF pin on the controller, and two between the controller and the first DIMM.Table 9:Clock Group Routing RulesLengthA = Obtain from DRAM controller vendor (“A” is the length from the die pad to the ball on the ASI C package)B = 1.9 to 5.0 inchesB2 = 2.325 to 5.425 inches Length Matching±4 mils for C K to C K#±9.9 mils clock pair to clock pair at the DIMM TraceTrace width = 8 mils: target 40Ω trace impedance, 80Ω differential impedance Trace space = 5 milsTrace space to other signal groups = 20 mils。

DDR3-硬件设计和-Layout-设计

冲和下冲等）。
终端匹配方案
设计者应该采用主流的终端匹配方案，像商业电脑主板那样的设计，ODT 终端匹配被应用在
数据总线上，地址/命令和控制线也应通过电阻连接到 VTT。当然，其它的终端匹配也是有
效的，但最好通过仿真来验证，确保信号质量满足要求。
3
终端匹配电阻的选择，其功耗是否满足芯片制造商的要求。
功耗计算 Power = x RT
4
假如数据线组增加了外部终端匹配电阻，请查看数据线组是否与其他 DDR3
信号组远离/隔离。
注：因为在 DDR3 数据组中通常优先选用内部 ODT 终端匹配，额外电阻是不
需要的。当然，假如不用 ODT 电阻，那么就需要增设外部电阻器了。
5
请查看 VTT 电阻 RT 布局是否正确，RT 终端电阻应该直接连接到 DDR 总线末端
4 / 13
序号
27
28 29 30
描述
该在同一层布线，并且保证过孔数量的一致性。
注：一些 DDR 芯片数据线接口是 32 位的。
通道 0：MDQ(7:0)，MDM(0)，MDQS(0)，
(0)
通道 1：MDQ(15:8)，MDM(1)，MDQS(1)，
(1)
通道 2：MDQ(23:16)，MDM(2)，MDQS(2)，
VREF 是否合理去耦，源端和终端都应布置一个 0.1uF 电容。
VREF 参考源是否会随 VDDQ、温度、噪声变化，这个变化是否满足 JEDEC 要求。
VREF 电流是否满足系统（DDR 和处理器）需求。
如果采用电阻分压网络产生 VREF，那么请保证电阻阻值和至少 1%的精度。
Routing
建议 DDR3 布线顺序如下：

DDR3要求规范

SODIMM： Small Outline DIMM，定位于笔记本市常 SODIMM是相对于DIMM而言的，前面提到的Unbufferd DIMM和Registered DIMM都隶属于 DIMM，内存模组的长度等，包括金手指的信号分布在内都是一样的。而SODIMM可以理解为小
Registered DIMM的时序： Registered DIMM和其他内存条相比增加了两种关键的器件，PLL和register。 PLL： Phase Locked Loop，锁相环，在模组中起到调节时序，增加时钟驱动力的作用。一般而言，无论是SDR还是DDR或DDR2的PLL，其输入输出管脚及其工作原理都是相似的。应用在内存模组上的PLL一般都有一个时钟输入，一个Feedback反馈输入，数个时钟输出及一个Feedback反馈输出。PLL的两个输入间为零延迟，也就是，FBin和CKin之间的相位差为
对A. 于PC一B块的受叠P层CB（层st数ac约ku束p的）基和板阻（抗如4层板）来说，其所有的信号线只能走在TOP和BOTTOM层，中间的两层，其中一层为GND平面层，而另一层为VCC 平面层，Vtt和Vref在VCC平面层布线。而当使用6层来走线时，设计一种专用拓扑结构变得更加容易，同时由于Power层和GND层的间距变小了，从而提高了PI。互联通道的另一参数阻抗，在DDR2的设计时必须是恒定连续的，单端走线的阻抗匹配电阻50 Ohms 必须被用到所有的单端信号上，且做到阻抗匹配，而对于差分信号，100 Ohms的终端阻抗匹配电阻必须被用到所有的差分信号终端，比如CLOCK和DQS信号。另外，所有的匹配电阻必须上拉到 VTT，且保持50 Ohms，ODT的设置也必须保持在50 Ohms。
目3、前，DD比R信较号普遍分使析用中的DDR2的速度已经高达800 Mbps，甚至更高的速度，如1066 Mbps，而 DDR3的速度已经高达1600 Mbps。对于如此高的速度，从PCB的设计角度来讲，要做到严格的时序匹配，以满足波形的完整性，这里有很多的因素需要考虑，所有的这些因素都是会互相影响的，但是，它们之间还是存在一些个性的，它们可以被分类为PCB叠层、阻抗、互联拓扑、时延匹配、串扰、电源完整性和时序，目前，有很多EDA工具可以对它们进行很好的计算和仿真，其中Cadence

DDR3的相关设计规范

DDR3的相关设计规范DDR3是一种常见的电子产品中使用的随机存取存储器（RAM）类型。

它使用双倍数据率（Double Data Rate，DDR）技术，提供高速数据传输和更高的带宽。

DDR3具有许多设计规范，以下是其中一些重要的规范。

1.精确的电气规范：DDR3的设计需要满足电气规范，以确保可靠的数据传输。

其中包括时钟频率、电压供应、信号幅度和交错延迟等方面的要求。

例如，DDR3的标准供电电压为1.5伏特（V）。

2.时序要求：DDR3的时序要求指定了命令、地址和数据等信号之间的时间关系。

这包括读取和写入操作的延迟时间、复位时间和刷新周期等。

时序要求的正确实现是确保DDR3稳定和可靠性的关键。

3.物理尺寸和连接接口：DDR3的物理尺寸和连接接口规范指定了模块的尺寸、引脚布局和插槽位置等。

这包括模块的长度、宽度和高度，以及引脚的布局和排列方式。

物理尺寸和连接接口规范确保DDR3可以正确地插入和连接到相应的插槽。

4.数据传输带宽：DDR3的设计规范涉及数据传输的带宽要求。

带宽是指每秒钟可以传输的数据量，通常以字节或位为单位。

DDR3的设计需要满足特定的带宽要求，以满足高速数据传输的需要。

5.控制和引脚定义：DDR3的设计规范中包括控制和引脚定义，用于指定不同引脚的功能和使用方式。

这些包括地址线、数据线、控制线、时钟线和电源线等。

控制和引脚定义规范确保正确的信号传输和通信。

6.容量和频率选项：DDR3的设计规范提供了不同容量和频率选项，以满足不同应用需求。

容量选项包括存储器模块的总容量，通常以GB为单位。

频率选项指定了DDR3的传输速率，通常以MHz为单位。

7.错误校正代码（ECC）支持：DDR3的设计规范中还包括对错误校正代码的支持。

ECC是一种能够检测和纠正内存中的错误的技术。

DDR3的设计需要支持ECC功能，以增强数据完整性和可靠性。

综上所述，DDR3的设计规范涵盖了电气规范、时序要求、物理尺寸和连接接口、数据传输带宽、控制和引脚定义、容量和频率选项，以及错误校正代码支持等方面。

DDR3_Layout_Guideline_RevB_2014

ISSI DDR3 SDRAM Layout GuidelinesRevision B0. July 15, 2014.IntroductionThis is a general PCB layout guideline for ISSI DDR3 SDRAM, especially targeting point to point applications.DDR3 is an evolutionary transition from previous memory generations of DDR2 products which increases clock frequencies and bandwidth with on the fly calibration to adjust for voltage and temperature variations to maintain stable Output drive characteristics, On-Die termination (ODT) with dynamic control and additional advanced features that are ideally suited for point to point applications.In DDR3 board designs controller manufacturers may require special or additional guidelines in these cases ISSI recommends the controller guidelines be applied first and confirmed to ISSI component specifications are not violated.PCB Layout GuidelinesFR-4 is commonly used for the dielectric material. Thickness and trace widths should be adjusted to match the desired impedance. Trace lengths are also important and their performance impact should be confirmed in simulations for each of the critical clock and net groups. Generally, single impedances (CA, Control & DQ’s) are 50Ω(+/- 10%) and differential impedances (Clocks, DQS’s) are nominally 100Ω(+/- 10%) and are typically routed on inner layers if possible. In slower applications, crosstalk issues would be less and closer spacing may be allowed after careful simulation to evaluate the design rule changes. Minimum spacing guidelines in these examples are dependent on dielectric thickness, routing pitch and should be verified with simulations to reduce intranet/internet group coupling/crosstalk. All impedances should be verified and monitored for each layer to make sure they comply with design specifications.Power DistributionAs clock frequencies increase power distribution networks (PDN) must be carefully controlled to insure adequate timing margin and noise immunity. This is especially critical in wide I/O designs where simultaneous switching of the outputs (SSO) is common. In this case power distribution networks can experience large peak current demands on Vddq and Vssq lines. If the power network isn’t carefully designed, peak current demand (High Drive Strength) can negatively impact timing margins and in extreme cases cause power supply deficiencies. Supply and ground planes, routing and decoupling should be checked insure optimal voltage/current supply for DDR3 devices.The following are general guidelines for PDN development in DDR3 board designs.1.Solid Power and Ground planes should be used in DDR3 routing areas.2.Place a 0.1uF cap and 0.01uF as close as possible for every VDDQ pin.3.VTT decoupling should be as close to the components and pull-up resistors as possible.4.Place a 0.1uF decoupling cap between VTT and VDD.5.Low ESL decoupling capacitors should be used and routing should be carefully evaluated to minimize inductance.6.Power connections from supply planes to vias for device pins or decoupling capacitors should be as short (<8 mils) and aswide as possible (trace widths should be the same or larger than the via size) to minimize trace impedance.A hierarchical design approach is recommended in DDR3 board layout with differential clocks (CK/CK#) and Data Strobes (DQS/DQS#). Overall routing lengths for these signals (CK/CK# & DQS/DQS#) should be controlled / matched to within ±2 ps or a maximum of 10mils between true and compliment signals. Route the CK/CK# clocks and set as the target trace propagation delays for the DQ net group. Match the CK/CK# clock to within ±5 ps of all DQS/DQS#. DQ and DM net groups should be routed with their respective DQS/DQS# and DM on the same PCB layer and matched within ±10ps, maximum difference of50mils. DQS/DQS# should be used as the target trace propagation delay for the associated Data and data mask signals.Route the address/control signal group ideally on the same layer as the CK/CK# clocks, to within ±10 ps skew of the CK/CK# traces. Following table is a good example for baseline specifications at the beginning of a board design. Values in this table are general guidelines and should be confirmed with board simulations to verify design targets and operating margins.Notes:1.Minimum trace width is 0.13mm (5mil).2.Intranet spacing, the distance between two adjacent traces within a net, is 8mil (depending on dielectric thickness)3.Internet spacing, the distance between the two outermost signals of different signal group is 15mil. Same rule appliesbetween one clock pair and another clock pair.4.Differential clocks should be routed in parallel with short trace lengths.5.Differential clocks must be routed on the same layer and placed on an internal layer minimize the noise.6.Due to crosstalk and signal noise reduction keeping the trace lengths as short possible ISSI recommends less that 20mm.7.Signals from the same net group should be routed on the same layer.8.Signals from the same Byte group, such as DQS, DM and 8 bits of DQ, must be routed in the same layerV REF ControlV REF should be designed to provide optimum noise margin in the system. V REF levels must be carefully controlled and isolated from noise conditions to prevent potential timing errors which can reduce setup and hold time margins, increase jitter, and cause erratic memory bus behavior. V REF is expected to track variations in V DDQ and the peak to peak noise must remain within specification.1.Place a 0.1uF capacitor between V REF and V DDQ2.Place a 0.1uF capacitor between V REF and V SSQ3.V REF should have a minimum trace length to reduce inductance.4.V REF should have a wide trace. Min 20 mil is recommended.5.V REF should maintain a minimum of 25mil width and spacing from other signals to minimize coupling effects and ideallybe isolated with adjacent ground traces.6.Each V REF source and destination should be decoupled with 0.1uF caps.EMI and Termination.The DDR3 SDRAM uses a programmable impedance output buffer. The output drive strength is calibrated during initialization, this feature minimizes any process variation present in the driver. To calibrate output driver impedance, RZQ needs to be located between the ZQ ball and VSSQ. The value of RZQ must be 240Ω ±1% and can’t be shared. Each DDR3 should have its own RZQ. Drive strength is selected by programming value in the memory mode register 1 (MR1). The default strength isRZQ/6(=40Ω). In layout, the impedance for all single ended data groups is approximately 50Ω and differential signals are nominally 100Ω. Refer to the controller manufacturers design guideline for the any restrictions or recommendations.LAND patternFollow IPC-SM-782A, keep size of land pattern to be equal to 80% of the ball size of BGA.Please contact the ISSI Application Engineering team for any DDR3 product development questions.Anderson Zhang(Anderson_Zhang@), Jiff Lee(jiff_lee@), Jiho Kim(jhkim@)。

DDR3设计调试

DDR3设计配置：1.关于配置寄存器：部分配置寄存器基地址在0x2100_0000#define DDR3_BASE_ADDR (0x21000000)#define DDR_SDCFG (*(unsigned int*)(DDR3_BASE_ADDR + 0x00000008))#define DDR_SDRFC (*(unsigned int*)(DDR3_BASE_ADDR + 0x00000010))#define DDR_SDTIM1 (*(unsigned int*)(DDR3_BASE_ADDR + 0x00000018))#define DDR_SDTIM2 (*(unsigned int*)(DDR3_BASE_ADDR + 0x00000020))#define DDR_SDTIM3 (*(unsigned int*)(DDR3_BASE_ADDR + 0x00000028))#define DDR_PMCTL (*(unsigned int*)(DDR3_BASE_ADDR + 0x00000038))#define RDWR_LVL_RMP_WIN (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000D4)) #define RDWR_LVL_RMP_CTRL (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000D8)) #define RDWR_LVL_CTRL (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000DC))#define DDR_ZQCFG (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000C8))#define DDR_PHYCTRL (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000E4))大部分寄存器位于chip-level registers 0x0262_0000 #define DDR3PLLCTL0 (*(unsigned int*)(0x02620330))#define DDR3PLLCTL1 (*(unsigned int*)(0x02620334))#define DATA0_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262040C))#define DATA1_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620410))#define DATA2_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620414))#define DATA3_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620418))#define DATA4_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262041C))#define DATA5_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620420))#define DATA6_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620424))#define DATA7_WRLVL_INIT_RATIO (*(unsigned int*)(0x02620428))#define DATA8_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262042C))#define DATA0_GTLVL_INIT_RATIO (*(unsigned int*)(0x0262043C))#define DATA1_GTLVL_INIT_RATIO (*(unsigned int*)(0x02620440))#define DATA2_GTLVL_INIT_RATIO (*(unsigned int*)(0x02620444))#define DATA3_GTLVL_INIT_RATIO (*(unsigned int*)(0x02620448))#define DATA4_GTLVL_INIT_RATIO (*(unsigned int*)(0x0262044C))#define DATA5_GTLVL_INIT_RATIO (*(unsigned int*)(0x02620450))#define DATA6_GTLVL_INIT_RATIO (*(unsigned int*)(0x02620454))#define DATA7_GTLVL_INIT_RATIO (*(unsigned int*)(0x02620458))#define DATA8_GTLVL_INIT_RATIO (*(unsigned int*)(0x0262045C))#define DDR3_CONFIG_REG_0 (*(unsigned int*)(0x02620404))#define DDR3_CONFIG_REG_12 (*(unsigned int*)(0x02620434))#define DDR3_CONFIG_REG_23 (*(unsigned int*)(0x02620460))#define DDR3_CONFIG_REG_24 (*(unsigned int*)(0x02620464))二、KICK Unlock和DDR3 PLL配置初始化DDR3控制器之前必须完成KICK Unlock和DDR3 PLL的配置。

DDR简介及设计基础指南 201401028

DDR简介及设计基础指南版本：V1.3目录第1章前言 (3)第2章内存简介 (3)2.1 基本存储原理 (3)2.2 内存的频率 (4)2.3 内存基本参数 (6)2.3.1 内存封装以及引脚定义说明 (6)2.3.1物理Bank (7)2.3.2逻辑Bank (8)2.3.3 tRCD解析 (9)2.3.4 CL解析 (9)2.3.4 tDQSS解析 (10)2.3.5 tRP(行预充电有效周期) (10)2.3.6 Burst Length(突发长度) (11)2.3.7 DQM（数据掩码） (12)2.3.8 DQS（数据选取脉冲） (12)2.3.9 Refresh(刷新) (13)2.3.10 DDR3与DDR2的区别 (15)2.3.11 ODT简介 (16)2.4 内存的工作原理 (17)2.4.1 内存工作流程 (18)2.4.2 模式寄存器（MRS）设置 (19)2.4.3 数据“读”过程 (21)2.4.4 数据“写”过程 (23)第3章硬件设计要求 (24)3.1 DDR的电源设计 (25)3.1.1 DDR的核心电源设计（VDD&VDDQ） (25)3.1.2 参考电压（Vref）设计 (26)3.1.3 Vtt简介及设计 (26)3.2 电源完整性设计（PI）介绍 (27)3.3 电路设计介绍 (32)3.4 内存的布局 (34)3.4.1 内存布线术语介绍 (34)3.4.2 DDR布线检查 (37)3.4.3 DDR有关的EMC设计 (41)第4章DDR仿真及测试方法 (42)4.1 DDR PCB设计仿真 (42)4.2 DDR测试参数介绍 (43)4.3简要可靠性测试方法 (46)第5章DDR4简介 (47)5.1 DDR4性能前瞻 (49)5.2 新技术特性 (52)5.3 未来展望 (54)第1章前言近年来CPU的发展速度之快让人目不暇接，新产品的运算能力成倍提升,而内存在发展的过程中随着CPU的飞速发展，其运行速度也在显著提升。

DDR3内存的PCB仿真与设计说明

本文主要使用时域分析丄具对DDR3设计进行量化分析，介绍了影响信号完整性的主要因素对DDR3进行时序分析，通过分析结果进行改进及优化设计。

1概述当今计算机系统DDR3存储器技术已得到广泛应用，数据传输率一再被提升，现已高达1866Mbpso在这种高速总线条件下，要保证数据传输质量的可靠性和满足并行总线的时序要求，对设计实现提出了极大的挑战。

本文主要使用了Cadence公司的时域分析工具对DDR3设计进行量化分析，介绍了影响信号完整性的主要因素对DDR3进行时序分析，通过分析结果进行改进及优化设计，提升信号质量使其可鼎性和安全性大大提高。

2 DDR3介绍DDR3存与DDR2存相似包含控制器和存储器2个部分，都采用源同步时序，即选通信号（时钟）不是独立的时钟源发送，而是山驱动芯片发送。

它比DR2有更高的数据传输率，最高可达1866Mbps； DDR3还采用8位预取技术，明显提高了存储带宽；其工作电压为1. 5V,保证相同频率下功耗更低。

DDR3接口设计实现比较困难，它采取了特有的Fly-by拓扑结构，用“Write leveling"技术来控制器件部偏移时序等有效措施。

虽然在保证设计实现和信号的完整性起到一定作用，但要实现高频率高带宽的存储系统还不全面，需要进行仿真分析才能保证设计实现和信号质量的完整性。

3仿真分析对DDR3进行仿真分析是以结合项LI进行具体说明：选用PowerPC 64位双核CPU模块，该模块采用Micron公司的MT41J256M16HA—125IT为存储器。

Freescale公司P5020为处理器进行分析，模块配置存总线数据传输率为1333MT/S,仿真频率为666MHz。

3. 1仿真前准备在分析前需根据DDR3的阻抗与印制板厂商沟通确认其PCB的叠层结构。

在高速传输中确保传输线性能良好的关键是特性阻抗连续，确定高速PCB信号线的阻抗控制在一定的圉，使印制板成为“可控阻抗板”，这是仿真分析的基础。

DDR3的相关设计规范

DDR3的相关设计规范(个人总结）一、阻抗控制DDR3要严格控制阻抗，单线50ohm，差分100ohm，差分一般为时钟、DQS。

在走线过程中，尽量减小阻抗跳变的因素,比如：换层（无法避免）、保证参考平面完整不跨分割、线宽变化、避免stub 线等。

二、布局布局整齐、美观,根据走线顺序调整DDR位置.如果走菊花链，两片DDR3距离可适当拉近，以节约空间。

如果走T型,多片DDR3中间需要打孔，则适当拉开距离。

DDR3与CPU之间在满足工艺要求的条件下，尽可能靠近点，以免走线过长.所有DDR3滤波电容紧挨电源管脚放置,以免影响滤波效果。

最好每个电源管脚都放置一个滤波电容。

DDR3电源模块要尽量靠近DDR3摆放.减小电源路径上的一些干扰及损耗三、布线.数据线：数据线每八根一组（DQ0—DQ7），外加相应的DQS差分对和DQM，因此，DQ0-DQ7、DQS差分对和DQM 为一组，共11根信号线，依次类推。

走线要同组同层,同组信号线中不能穿插不属于本组的同层信号线，换层次数一致(打孔次数一致），优先以地平面为参考。

DQS查分对内等长小于5mil.信号线之间保持两倍线宽的间距（有空间的情况下最好做到三倍线宽以上的间距）。

局部区域可适当减小距离。

以减小信号之间的串扰。

其它非数据线不要靠太近（特别是同层信号线）。

地址线:地址线、控制线、时钟线统称为地址线（A0-A15、WEN、BA0、BA1、BA2、CASN、ODT、RESETN、CKE、RASN、CSN、和时钟差分(CLK、CLKN）。

）走线时可以不同层（当然能同层最好不过了，难道比较大)，优先以地平面为参考，时钟差分对内等长误差小于5mil，信号线之间保持两倍线宽的间距(有空间的情况下最好做到三倍线宽以上的间距）。

以减小信号之间的串扰.实在没空间的情况下可走一比一的间距.其它非地址线不要靠太近（特别是同层信号线）。

其它非DDR自身的信号线都不要从DDR信号线区域经过,尽量远离这些高速信号线。

xilinx平台DDR3设计教程之仿真篇_中文版教程

想做个DDR设计不？想还是不想？你要知道FPGA这种东西，片内存储资源终究有限，实在谈不上海量存储。

万一哪天你想要海量存储数据了咋办？你是不是得用DRAM条子啊？什么？你还想用SRAM？今年已经2013年了童鞋~关于DRAM，或许是SDRAM，或许是DDR1（再次提醒你，2013年了已经），或许是DDR2或者DDR3。

这些条子都有一套控制协议，这套协议对不同的条子大同小异，但是里面又有各种细节的区别，这些你都搞懂了吗？没搞懂？其实，你不需要搞懂。

现在的EDA设计不需要你从基础知识开始研究。

这个时代，你要生存要发展，最佳的办法是站在巨人的肩膀上，而不是亲自长成个巨人。

DDR设计太常用了，只要你在搞FPGA，自然有人给你搞定一套IP，免费的给你用。

你不会还想自己从底层写起吧？多花些时间在没有免费IP用的协议合算法上吧。

现在进入正题：我刚刚讲的免费IP，在哪里？怎么用的？（小白问题，IP是什么，IP地址吗？）这里的IP就是Intelligence Property说白了就是xilinx里的core gen（对应于altera里面的mega wizard）这个文档就举一个例子来讲，选哪家呢?本人是xilinx和altera都来一个？条子选啥？SDR?DDR1? 各种条子全都写一套？（你以为写这个文档容易吗，是不是要连chipscope怎么用也一起出个文档啊？全部都写一套可以，先往我账户上打五千块钱，然后我再考虑考虑。

记住这个世界上没有白吃的午餐，你要看白痴都能看会的DDR教程，你就得听我在这里唠叨）本教程选择一个例子来讲，那就是xilinx平台下用DDR3（常见的笔记本内存条）接下来是你玩转这个教程所必须要准备的工具：xilinx ISE 14.1或者更高版本（不好意思，比14.1还低的版本我没试过。

vivado当然也可以，不过我是用的ISE）modelsim SE 6.6a或者更高版本（更低版本我负责的告诉你不可以，因为无法正常生成编译库，所以，6.5版本或者更低的你干脆就别装了）有鉴于这个文档的面相对象设定为连chiscope都不太会用的人，就是那种刚毕业不到一两年甚至还在校的，我必须郑重的告诉你一下这两个工具上哪里去下载：网上下载，百度股沟搜索会不会？什么？你告诉我搜不到？我给你跪了，菜鸟兄XILINX ISE 14.4这里下载http://simplecd.me/entry/L1a0enD2/破解文件：/f/62469961.htmlmodelsim 6.6这里下载（要注册和花积分的）：/viewthread.php?tid=232457破解文件：/f/34760037.html（注意，时间长了以后这几个链接是可能失效的，比如你可能在2015年看到这个2013年11月写的文档，到时候可能只能自己找下载了）PPT翻了一页了，工具都装完了吗亲？已经装完了啊？很好哦，那我们就开始吧！你知道用ISE做DDR设计的第一步是啥吗？当然是打开工具了——我估计这你肯定知道打开工具之后做啥？当然是生成一个IP，对xilinx来说也就是core gen了我估计你即便是新手上路，这个也是知道的——因为我前面刚刚讲过了嘛那么core gen生成完了之后呢？是不是要仿真啊？仿真需要什么？当然是modelsim了——我还是刚刚讲过，哈哈那你知道用modelsim仿真DDR的core gen，是需要xilinx仿真库的吗？什么？你不知道啥叫仿真库？乖乖隆地洞，我还是给你讲讲啥叫仿真库吧先关于FPGA的仿真库本人不是学校里的学究，本人是工程师所以用工程师的语言告诉你啥叫仿真库FPGA本身是一种特定的芯片，这个芯片里有很多特定的基本电路单元。

DDR3 Layout Design

Freescale SemiconductorApplication NoteThe design guidelines presented in this application note apply to products that leverage the DDR3 SDRAM IP core, and they are based on a compilation of internal platforms designed by Freescale Semiconductor, Inc. The purpose of these guidelines is to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer.Freescale highly recommends that the system/board designer verify all design aspects (signal integrity, electrical timings, and so on) through simulation before PCB fabrication.Document Number:AN3940Rev. 1, 03/2010Contents1.Designer Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.Termination Dissipation . . . . . . . . . . . . . . . . . . . . . . . 73.V REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.VTT Voltage Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8yout Guidelines for the Signal Groups . . . . . . . . . . 86.Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127.Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfacesby Networking and Multimedia GroupFreescale Semiconductor, Inc.Austin, TXDesigner Checklist1Designer ChecklistIn the following checklist, some of the items are phrased as question, others as requirements. In all cases, it is recommended to consider the line item and check it off in the rightmost column of Table1.Table1. DDR3 Designer’s ChecklistItem Description Yes/NoSimulation1.Have optimal termination values, signal topology, trace lengths been determined through simulation for eachsignal group in the memory implementation? If on-die termination is used at both the memories and the controller,no additional termination is required for the data group.The following unique groupings exist:1.Data Group: MDQS(8:0), MDQS(8:0), MDM(8:0), MDQ(63:0), MECC(7:0)2.Address/CMD Group: MBA(2:0), MA(15:0), MRAS, MCAS, MWE.3.Control Group: MCS(3:0), MCKE(3:0), MODT(3:0)4.Clock Group: MCK(5:0) and MCK(5:0)These groupings assume a full 72-bit data implementation (64-bit + 8 bits of ECC). Some products may onlyimplement 32-bit data and may choose to have fewer MCS, MCKE, and MODT signals. Some products supportthe optional MAP AR_OUT and MAP AR_ERR for registered DIMMs. In such cases, MAP AR_OUT should betreated as part of the ADDR/CMD group and MAPAR_ERR can be treated as an asynchronous signal.2.Does the selected termination scheme meet the AC signaling parameters (voltage levels, slew rate, andovershoot/undershoot) across all memory chips in the design?Termination SchemeIt is assumed that the designer is using the mainstream termination approach as found in commodity PC motherboards. Specifically, it is assumed that on-die termination is used for the data groups and that external parallel resistors tied to VTT are used for the Address/CMD and the control groups. Consequently, differing termination techniques may also prove valid and useful. However, they are left to the designer to validate through simulation.3.Is the worst case power dissipation for the termination resistors within the manufacturer’s rating for the selecteddevices? See Section2, “Termination Dissipation.”4.If resistor packs are used, have data lanes been isolated from the other DDR3 signal groups?Note: Because on-die termination is the preferred method for DDR3 data signals, external resistors for the datagroup should not be required. This item would only apply if the ODT feature is not used.5.Have V TT resistors been properly placed? The R T terminators should directly tie into the V TT island at the end ofthe memory bus.6.Is the differential terminator present on the clock lines for discrete memory populations? (DIMM modules containthis terminator.) Nominal range => 100–120 Ω.7.Recommend that an optional 5pF cap be placed across each clock diff pair. If DIMM modules are used, the capshould be placed as closely as possible to the DIMM connector. If discrete devices are used, the cap should beplaced as closely as possible to the discrete devices.V TT Related Items8.Has the worst case current for the V TT plane been calculated based on the design termination scheme? SeeSection2, “T ermination Dissipation.”9.Can the V TT regulator support the steady state and transient current needs of the design?Designer ChecklistTable1. DDR3 Designer’s Checklist (continued)Item Description Yes/No 10.Has the V TT island been properly decoupled with high frequency decoupling? At least one low ESL cap, or twostandard decoupling caps for each four-pack resistor network (or every four discrete resistors) should be used. Inaddition, at least one 4.7-μF cap should be at each end of the V TT island.Note: This recommendation is based on a top-layer V TT surface island (lower inductance). If an internal split isused, more capacitors may be needed to handle the transient current demands.11.Has the V TT island been properly decoupled with bulk decoupling? At least one bulk cap (100–220μF) capacitorshould be at each end of the island.12.Has the V TT island been placed at the end of the memory channel and as closely as possible to the last memorybank? Is the V TT regulator placed in close proximity to the island?13.Is a wide surface trace (~150 mils) used for the V TT island trace?14.If a sense pin is present on the V TT regulator, is it attached in the middle of the island?V REF15.Is V REF routed with a wide trace? (Minimum of 20–25 mil recommended.)16.Is V REF isolated from noisy aggressors? In addition, maintain at least a 20–25 mil clearance from V REF to othertraces. If possible, isolate V REF with adjacent ground traces.17.Is V REF properly decoupled? Specifically, decouple the source and each destination pin with 0.1uf caps.18.Does the V REF source track variations in V DDQ, temperature, and noise as required by the JEDEC specification?19.Does the V REF source supply the minimal current required by the system (memories + processor)?20.If a resistor divider network is used to generate V REF, are both resistors the same value and 1% tolerance?Routing21.The suggested routing order within the DDR3 interface is as follows:1.Data address/command2.Control3.Clocks4.PowerThis order allows the clocks to be tuned easily to the other signal groups. It also assumes an open critical layeron which clocks are freely routed.22.Global items are as follows:•Do not route any DDR3 signals overs splits or voids.•T races routed near the edge of a reference plane should maintain at least 30–40 mil gap to the edge of the reference plane.•Allow no more than 1/2 of a trace width to be routed over via antipad.23.When routing the data lanes, route the outermost (that is, longest lane first) because this determines the amountof trace length to add on the inner data lanes.24.The max lead-in trace length for data/address/command signals, are not longer than 7 inches?25.Are the clock pair assignments optimized to allow break-out of all pairs on a single critical layer?Designer ChecklistTable1. DDR3 Designer’s Checklist (continued)Item Description Yes/No 26.The DDR3 data bus consists of 9 data byte lanes (assuming ECC is used). All signals within a given byte laneshould be routed on the same critical layer with the same via count.Note: Some product implementations may only implement a 32-bit wide interface.Byte Lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS(0)Byte Lane 1—MDQ(15:8), MDM(1), MDQS(1), MDQS(1)Byte Lane 2—MDQ(23:16), MDM(2), MDQS(2), MDQS(2)Byte Lane 3—MDQ(31:24), MDM(3), MDQS(3), MDQS(3)Byte Lane 4—MDQ(39:32), MDM(4), MDQS(4), MDQS(4)Byte Lane 5—MDQ(47:40), MDM(5), MDQS(5), MDQS(5)Byte Lane 6—MDQ(55:48), MDM(6), MDQS(6), MDQS(6)Byte Lane 7—MDQ(63:56), MDM(7), MDQS(7), MDQS(7)Byte Lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS(8)T o facilitate fan-out of the DDR3 data lanes (if needed), alternate adjacent data lanes onto different critical layers.See Figure1 and Figure2.Note: If the device supports ECC, Freescale highly recommends that the user implement ECC on the initialhardware prototypes.27.DDR3 data group—impedance range and spacingOption #1 (wider traces—lower trace impedance)•Single-ended impedance = 40 Ω. The lower impedance allows traces to be slightly closer with less cross-talk.•Utilize wider traces if stackup allows (7–8mils)•Spacing to other data signals = 1.5x to 2.0x•Spacing to all other non-DDR signals = 4xOption #2 (smaller traces—higher trace impedance)•Single-ended impedance = 50 Ω.•Smaller trace widths (5–6mil) can be used.•Spacing between like signals should increase to 3x (for 5mil) or 2.5x (for 6mil) respectively28.Check the following across all DDR3 data lanes:•For MPC8572 and MPC8536, are all the data lanes matched to within 0.1 inch?•For all other devices, are all the data lanes matched to within 2.0 inch?29.Is each data lane properly trace matched to within 20 mils of its respective differential data strobe? (Assumeshighest frequency operation.)30.When adding trace lengths to any of the DDR3 signal groups, ensure that there is at least 25 mils betweenserpentine loops that are in parallel.Designer ChecklistTable1. DDR3 Designer’s Checklist (continued)Item Description Yes/No 31.MDQS/MDQS differential strobe routingNote: Some product implementations may support only the single-ended version of the strobe.•Match all segment lengths between differential pairs along the entire length of the pair. T race match the MDQS/ MDQS pair to be within 10 mils.•Maintain constant line impedance along the routing path by maintaining the required line width and trace separation for the given stackup.•Avoid routing differential pairs adjacent to noisy signal lines or high speed switching devices such as clock chips.•Differential 75–95 Ω•Diff Gap = 4–5 mils (as DQS signals are not true differential...aka pseudo differentialOption #1 (wider traces—lower trace impedance)•Single-ended impedance 40 Ω. The lower impedance allows traces to be slightly closer with less cross-talk.•Utilize wider traces if stackup allows (7–8mils)•Spacing to other data signals = 2x.•If not routed on the same layer as its associated data, then 4x spacingOption #2 (smaller traces—higher trace impedance)•Single-ended impedance = 50 Ω.•Smaller trace widths (5–6mil) can be used.•Spacing between like signals (other data) should increase to 3x (for 5mil) or 2.5x (for 6mil) respectively.•Do not divide the two halves of the diff pair between layers. Route MDQS/MDQS pair on the same critical layer as its associated data lane.32.DDR3 address/command/control group—impedance range and spacing•Daisy chain from chip to chip. The routing should go from chip 0 to chip n, where chip 0 is the one that has the lower data bits DQ[0:7]… and chip n has the upper data bits. The daisy chain should end at the terminationresistors that are after chip n.•With regards to physical/spacing propertiesOption #1 (wider traces—lower trace impedance)•Single-ended impedance = 40 Ω. The lower impedance allows traces to be slightly closer with less cross-talk.•Utilize wider traces if stackup allows (7–8mils)•Spacing to other like signals = 1.5x to 2.0x•Spacing to all other non-DDR signals =3–4xOption #2 (smaller traces—higher trace impedance)•Single-ended impedance = 50 Ω.•Smaller trace widths (5–6mil) can be used.•Spacing between like signals should increase to 3x (for 5mil) or 2.5x (for 6mil) respectively•Spacing to all other non-DDR signals =3–4x•With regards to tuning•T une signals to 20 mil of the clock at each device.33.DDR3 differential clocksRoute as diff pair. With regards to diff properties, recommendations are as follows:•P-to-N tuning = 10 mils•T arget single-ended impedance 40–50 Ω. The lower impedance reduces cross-talk.•Differential 75–95 Ω•Diff Gap = set per stackupOption #1 (wider traces—lower trace impedance)•Attempt to utilize wider traces if stackup allows (7–8mils)•Spacing to other signals = 4x.Option #2 (smaller traces—higher trace impedance)•Single-ended impedance = 50 Ω.•Smaller trace widths (5–6mil) can be used.•Spacing to other signals = 4x.Designer ChecklistTable1. DDR3 Designer’s Checklist (continued)Item Description Yes/No34.Are all clock pairs routed on the same critical layer (one referenced to a solid ground plane)?35.Are all clock pairs properly trace matched to within 25 mils of each other?36.The space from one differential pair to any other trace (this includes other differential pairs) should be at least 25mils.37.If unbuffered DIMM modules are used, are all required clock pairs per DIMM slot connected?Note: Single ranked DIMM requires 1 clock pair and dual ranked DIMM requires 2 clock pairsMODT/MDIC Related Items38.Are the MODT signals connected correctly?•MODT(0), MCS(0), MCKE(0) should all go to the same physical memory bank.•MODT(1), MCS(1), MCKE(1) should all go to the same physical memory bank.•MODT(2), MCS(2), MCKE(2) should all go to the same physical memory bank.•MODT(3), MCS(3), MCKE(3) should all go to the same physical memory bank.39.Is MDIC0 connected to ground via an 40-Ω precision 1% resistor? Is MDIC1 connected to DDR power via an 40-Ωprecision 1% resistor?Miscellaneous Items40.Are the power-on reset config pins properly set for the correct DDR type?Note: Not all Freescale products support external power-on reset configuration pins for selecting the DDR type.Therefore, this item does not apply to all Freescale products.Registered DIMM Topologies (All items above still apply)41.For memory implementations that use registered DIMM modules, the board designer should attach a reset signalto the DIMM sockets. This reset signal should be derived from a ‘power good’ monitor status circuit.Note: The reset pin to the DRAM is 1.5V LVCMOS.42.Though registered DIMMs require only a single clock per bank, all DDR3 clock pairs at the DIMM connectorshould be attached (analogous to unbuffered DIMMs) so the design can also support unbuffered DIMMs withminimal changes.43.If the controller supports the optional MAPAR_OUT and MAPAR_ERR signals, ensure that they are hooked upas follows:•MAP AR_OUT (from the controller) => P AR_IN (at the RDIMM)•ERR_OUT (from the RDIMM) => MAPAR_ERR (at the controller)44.MAP AR_ERR is an open drain output from registered DIMMs. Ensure that a 4.7K pull-up to 1.5 V is present onthis signal.Discrete Memory Topologies (All items above still apply with exception of registered DIMM items)45.Construct the signal routing topologies for the groups like those found on unbuffered DIMM modules (that is,proven JEDEC topologies).46.When placing components, optimize placement of the discretes to favor the data bus (analogous to DIMMtopologies).Optional: Pin-swap within a given byte lane to optimize the data bus routes further.Caution: Do not swap individual data bits across different byte lanes.Termination Dissipation2Termination DissipationSink and source currents flow through the parallel R T resistors on the address and control groups. The worst case power dissipation for these resistors is as follows:Power =I 2×R T =(13mA)2×(47Ω)=7.9mW.Small resistors that provide dissipation of up to 1/16 W are ideal. See Section 4, “VTT V oltage Rail ,” for assumptions made for current calculations.3V REFThe current requirements for V REF are relatively small, at less than 3 mA. This reference provides a DC bias of 0.75V (V DD /2) for the differential receivers at both the controller interface and the DDR devices. Noise or deviation in the V REF voltage can lead to potential timing errors, unwanted jitter, and erratic behavior on the memory bus. To avoid these problems, V REF noise must be kept within the JEDEC specification. As such, V REF and the V TT cannot be the same plane because of the DRAM V REF buffer sensitivity to the termination plane noise. However, both V REF and V TT must share a common source supply to ensure that both are derived from the same voltage plane. Proper decoupling at each V REF pin (at the controller, at each DIMM/discrete, and at the V REF source) along with adhering to the simple layout considerations enumerated in the checklist in Table 1 prevents potential problems .Numerous off-the-shelf power IC solutions are available that provide both the V REF and V TT from acommon source. Regardless of the generation technique, V REF must track variations in V DDQ over voltage, temperature, and noise margins as required by the JEDEC specifications.47.If a single bank of x16 devices is used, let the DDR3 clocks be point-to-point. Place the series damping resistor (R S ) close to the source and the differential terminator (R DIFF ) at the input pins of the discretes.If more than five discretes are used, construct the clocks like those on unbuffered DIMM modules. Alternatively, place an external PLL between the controller and the memory to generate the additional clocks.48.If multiple physical banks are needed, double stack (top and bottom) the banks to prevent lengthy and undesirable address/cmd topologies.49.Properly decouple the DDR3 chips per manufacturer recommendations. T ypically, five low ESL capacitors per device are sufficient. For further information, see article entitled Decoupling Capacitor Calculation for a DDR Memory Channel, located on Micron’s web site.50.T o support expandability into larger devices, ensure that extra NC pins (future address pins) are connected.51.Ensure access/test points are available for signal integrity probing. This is especially critical if using blind and buried vias within the memory channel. If through-hole vias are used under the BGA devices, then generally these sites can be used for probing.52.Ensure R T , resistors on the address and control groups are located after the last DRAM chip in the-fly-by topology.53.Ensure the reset pin has been considered and connected to the proper reset logic. Note: The reset pin to the DRAM is 1.5V LVCMOS.Table 1. DDR3 Designer’s Checklist (continued)Item DescriptionYes/NoVTT Voltage Rail4V TT Voltage RailFor a given topology, the worst case V TT current should be derived. Assuming the use of a typical R T parallel termination resistor and the worst case parameters given in Table 2, sink and source currents can be calculated.The driver sources (V TT plane would sink) the following based on this termination scheme:(V DD_max –V TT_min )/(R T + R DRVR )=(1.575–0.702 V)/(47+20)=13 mA The driver sinks (V TT plane would source) the following based on this termination scheme:(V TT_max – V OL / (R T + R S + R DRVR )=(0.798–0 V)/(47+20)=12 mAA bus with balanced number of high and low signals places no real demand on the V TT supply. However, a bus with all DDR address/command/control signals low (~ 28 signals) causes a transient current demand of approximately 350 mA on the V TT rail. The V TT regulator must provide a relatively tight voltage regulation of the rail per the JEDEC specification. Besides a tight tolerance, the regulator must also allow V TT along with V REF (if driven from a common IC), to track variations in V DDQ over voltage, temperature, and noise margins.5Layout Guidelines for the Signal GroupsTo help ensure the DDR interface is properly optimized, Freescale recommends the following sequence for routing the DDR memory channel:1.Route data2.Route address/command/control3.Route clocks The data group is listed before the command, address, and control group because it operates at twice the clock speed, and its signal integrity is of higher concern. In addition, the data group constitutes the largest portion of the memory bus and comprises most of the trace matching requirements (those of the data lanes). The address/command, control, and data groups all have a relationship to the routed clock.Therefore, the effective clock lengths used in the system must satisfy multiple relationships. The designer should perform simulation and construct system timing budgets to ensure that these relationships are properly satisfied.Table 2. Worst Case Parameters for V TT Current Calculation ParameterValuesCommentV DDQ (max) 1.575 V From JEDEC spec V TT(max)0.798 V From JEDEC spec V TT(min)0.702 V From JEDEC specR DRVR 20 ΩNominally, full strength is ~ 20Ωs R T 47 ΩCan vary. T ypically 25–47Ωs.V OL0 VAssumes driver reaches 0V in the low state.Layout Guidelines for the Signal Groups 5.1Data—MDQ[0:63], MDQS[0:8], MDM[0:8], MECC[0:7]The data signals of the DDR interface are source-synchronous signals by which memory and the controller capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the strobe are used to achieve the 2x data rate.An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit signal lane relationship is crucial for routing, and Table3 depicts this relationship. When length matching, the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching across all bytes lanes is also important and must meet the t DQSS parameter as specified by JEDEC. This is also commonly referred to as the write data delay window. Typically, this timing is considerably more relaxed than the timing of the individual byte lanes themselves.Table3. Byte Lane to Data Strobe and Data Mask MappingData Data Strobe Data Mask Lane NumberMDQ[0:7]MDQS0, MDQS0MDM0Lane 0MDQ[8:15]MDQS1, MDQS1MDM1Lane 1MDQ[16:23]MDQS2, MDQS2MDM2Lane 2MDQ[24:31]MDQS3, MDQS3MDM3Lane 3MDQ[32:39]MDQS4, MDQS4MDM4Lane 4MDQ[40:47]MDQS5, MDQS5MDM5Lane 5MDQ[48:55]MDQS6, MDQS6MDM6Lane 6MDQ[56:63]MDQS7, MDQS7MDM7Lane 7MECC[0:7]MDQS8, MDQS8MDM8Lane 8NOTEWhen routing, each row (that is, the 11-bit signal group) must be treated asa trace-matched group.5.2Layout RecommendationsFreescale strongly recommends routing each data lane adjacent to a solid ground reference for the entire route to provide the lowest inductance for the return currents, thereby providing the optimal signal integrity of the data interface. This concern is especially critical in designs that target the top-end interface speed, because the data switches at 2x the applied clock. When the byte lanes are routed, signals within a byte lane should be routed on the same critical layer as they traverse the PCB motherboard to the memories. This consideration helps minimize the number of vias per trace and provides uniform signal characteristics for each signal within the data group.To facilitate ease of break-out from the controller perspective, and to keep the signals within the byte group together, the board designer should alternate the byte lanes on different critical layers (see Figure1 and Figure2).Layout Guidelines for the Signal GroupsFigure 1. Alternating Data Byte Lanes on Different Critical Layers —Part 1Data Lane 7Data Lane 5Data Lane 3Data Lane 1Layout Guidelines for the Signal GroupsFigure 2. Alternating Data Byte Lanes on Different Critical Layers—Part 2Data Group 6Data Group 4Data Group 8Data Group 2Data Group 0Simulation6SimulationThis application note provides general hardware and layout considerations for hardware engineers implementing a DDR3 memory subsystem.The rules and recommendations in this document can serve as an initial baseline for board designers to begin their specific implementations. The fly-by memory topology and many interface frequencies are possible from the DDR3 interface, so it is highly recommended that the board designer verify that all aspects (signal integrity, electrical timings, and so on) are addressed through simulation before board fabrication.In tandem with memory vendors, Freescale provides IBIS models for simulation. The board designer can realize a key advantage in the form of extra noise and timing margins by taking the following actions:•Optimizing the clock to signal group relationships to maximize setup and hold times•Optimizing termination values. During board simulation, verify that all aspects of the signal eye are satisfied, which includes at a minimum the following:—A sufficient signal eye opening meeting both timing and AC input voltage levels—Vswing max not exceeded (or alternatively max overshoot/max undershoot)—Signal slew rate within specificationsFigure3 shows the SSTL signal waveform.Figure3. SSTL Signal WaveformFurther Reading 7Further ReadingFollowing is a list of documentation that may be useful:•DDR3 chapter of the corresponding PowerQUICC or QorIQ processor reference manual•Micron web site: . For example, Design Guide for DDR3-1066 UDIMM systems: TN_41_08•JEDEC web site: . For example, the DDR3 SDRAM specification8Revision HistoryTable4 provides a revision history for this application note.Table4. Document Revision HistoryRev.Date Substantive Change(s)Number103/2010In T able1, for item# 28, changed the second bulleted sentence as follows:For all other devices, are all the data lanes matched to within 2.0 inch?001/2010Initial public releaseDocument Number:AN3940 Rev. 103/2010Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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LayoutGuide_DDR3

ISSI DDR3 SDRAM Layout GuildRevision 0A. May 4, 2012.IntroductionThis is a general PCB layout guideline for ISSI DDR3 SDRAM, especially targeting for point to point application. Chipset companies may require for a special or additional guideline for DDR3. ISSI recommends following the chipset company’s rule first.PCB Layout GuidelinesFR-4 is commonly used for the dielectric material. And its thickness and trace width and thickness should be adjusted for matching the impedance. Trace lengths are also important that should be determined through simulation for each signal group.In general, ISSI recommends the minimum rules for trace in PCB as below for the crosstalk. These rules are based on the assumption of signal slew rate of 1V/1ns. In slower application, crosstalk issue would be less and closer spacing may be allowed.1.Signals from the same net group should be routed on the same layer.2.Signals from Byte group, such as DQS, DM and 8 bits of DQ, must be routed in the same layer3.The deviation of signal propagation delay is dependent on the timing budget on the application. Following value in thetable is a good example for the beginning of design.4.Minimum trace width is 0.13mm(5mil).5.Intranet spacing, the distance between two adjacent traces within a net, is 0.2mm(7mil).6.Internet spacing, the distance between the two outermost signals of different signal group is 15mil. Same rule appliesbetween one clock pair and another clock pair.7.Differential clocks should be routed in parallel and keep the trace length short.8.Differential clocks must be routed on the same layer and placed on an internal layer minimize the noise.9.Keep some distance between CKE and CK/CK#V REF controlSetup and hold time margin will be reduced when V REF has a noise. V REF should be designed by the user to provide optimum noise margin in the system. V REF is expected to track variations in V DDQ and the pick to pick noise should be met with specification.1.1KΩ±1%/1KΩ±1%/ from V DDQ power panel.2.Place a 0.1uF capacitor between V REF and V DDQ3.Place a 0.1uF capacitor between V REF and V SSQ4.V REF should have a minimum trace to reduce inductance.5.V REF should have a wide trace. Min 20 mil is recommended.6.V REF should keep a distance from other signals to reduce decoupling effect. At least, 25 mil is recommended.EMI and termination.The DDR3 SDRAM uses a programmable impedance output buffer. The output drive strength is calibrated during initialization. And this feature minimizes any process variation present in the driver. To calibrate output driver impedance, RZQ needs to be located between the ZQ ball and VSSQ. The value of RZQ must be 240Ω ±1%. RZQ can’t be shared. Each DDR3 should have its own RZQ. The drive strength setting is selected by programming the memory mode register setting defined by mode register 1 (MR1). And the default strength is RZQ/6(=40Ω). In layout, the impedance for all single ended data group should be close to 40Ω and that for differential should be close to 80Ω. Refer to the design guidelines of DRAM controller vendor for the detail restriction and recommendation.DDR3 SDRAM also introduces a new feature “Dynamic ODT” and allows different ODT setting depending on the operation state. This feature increases flexibility to optimize termination values for different loading conditions. However, the result of enabling this feature can be different depending how ODT of DRAM controller behavior. User should follow DRAM controller guideline.LAND patternFollow IPC-SM-782A, keep size of land pattern to be equal to 80% of the ball size of BGA.For any questions, please contact the following individuals from ISSI’s applicatio n.Anderson Zhang(Anderson_Zhang@), Jiff Lee(jiff_lee@), Jiho Kim(jhkim@)。

A20A10DDR3设计与调试V1.0_20130424

A20A10DDR3设计与调试V1.0_20130424A20&A10DDR3设计V1.02013-04-24Revision HistoryVersion Date Changes compared to previous issue1.020130424目录1.概述 (4)1.1.目的 (4)1.2.适用范围 (4)2.DRAM设计差异 (5)2.1.硬件设计 (5)2.2.软件配置 (5)3.Declaration (8)1.概述1.1.目的本文档对A20平台和A10平台在DRAM部分的软硬件设计进行阐述，并对它们的差异进行对比，对使用A20、A10平台的客户进行DRAM设计指导，减免设计错误。

1.2.适用范围本文档仅适用于全志科技的A20、A10平台。

2.DRAM设计差异2.1.硬件设计编号A20A101时钟线上串联的电阻为0R时钟线上串联的电阻为25R 2地址线为16位地址线为15位3主控端的DRAM电压参考和DDR3的电压参考使用同一分压电路主控端的DRAM电压参考和DDR3的电压参考使用独立的分压电路4DRAM端的DRAM-REF公用一个滤波电容DRAM端的DRAM-REF每个PIN使用一个滤波电容5*DRAM端每个芯片的DRAM-VCC滤波电容精简为4个，具体见标案图DRAM端每个芯片的DRAM-VCC滤波电容为7个，具体见标案图*均以8bit DRAM设计为参考，16bit DRAM详细设计请参考标案图。

表1A20&A10硬件电路差异2.2.软件配置2.2.1.A20平台[dram_para]dram_baseaddr=0x40000000dram_clk=360dram_type=3dram_rank_num=0xffffffffdram_chip_density=0xffffffffdram_io_width=0xffffffffdram_bus_width=0xffffffffdram_cas=9dram_zq=0x7bdram_odt_en=0dram_size=0xffffffffdram_tpr0=0x42d899b7dram_tpr1=0xa090dram_tpr2=0x22a00dram_tpr3=0x0dram_tpr4=0x0dram_tpr5=0x0dram_emr1=0x4dram_emr2=0x10dram_emr3=0x02.2.2.A10平台[dram_para]dram_baseaddr=0x40000000 dram_clk=360dram_type=3dram_rank_num=dram_chip_density=dram_io_width=dram_bus_width=dram_cas=6dram_zq=0x7bdram_odt_en=0dram_size=dram_tpr0=0x30926692 dram_tpr1=0x1090 dram_tpr2=0x1a0c8 dram_tpr3=0x0dram_tpr4=0x0dram_tpr5=0x0dram_emr1=0x0dram_emr2=0x0dram_emr3=0x02.2.3.差异有2.2.1和2.2.2可以看出，A20平台和A10平台在DDR配置参数有些差异，如下：dram_rank_num=0xffffffffdram_chip_density=0xffffffffdram_io_width=0xffffffffdram_bus_width=0xffffffffdram_size=0xffffffffdram_tpr0=0x42d899b7dram_tpr1=0xa090dram_tpr2=0x22a00dram_emr1=0x4dram_emr2=0x10以上差异禁止客户更改，如果需要更改，请联系全志科技股份有限公司的技术支持部进行确认。

经典DDR3PCB设计指导

经典DDR3PCB设计指导DDR3（Double Data Rate 3）是一种高速、大容量的随机存取存储器（RAM）技术，被广泛应用于各种计算机系统中。

在设计DDR3 PCB时，需要考虑信号完整性、EMI、布局、电源管理等因素，以确保系统的稳定性和性能优化。

以下是经典的DDR3PCB设计指导：1.保持信号完整性：-使用合适的信号走线宽度和间距，根据DDR3规范进行引脚布局和布线。

-控制信号的线长匹配，特别是对于时钟和命令/控制信号，通过控制线长来减小延迟。

-使用差分对来传输数据和时钟信号，并保持差分对长度相等，以最小化信号的失真和串扰。

2.使用层次布局：-使用多层PCB设计，将信号和电源/地线分开布局在不同的层次上，以减少干扰和串扰。

-高速信号层应该位于内层或表层以提高信号完整性，电源/地线可以位于内层。

3.地线规划：-根据信号引脚布局的特性，在有需要的地方增加避雷阻抗到地线。

-在信号回流点上使用地孔，以确保地线的连续性和稳定性。

-用足够的地区域保持良好的接地电流路径，以防止信号引脚之间的环形回流。

4.电源管理：-确保DDR3模块的电源电压稳定性，以避免信号和时序问题。

-确保电源管脚的降压滤波电容足够，以提供稳定的电源。

-使用布线良好的电源平面，以减少噪声和电流环路。

5.EMI控制：-在高速信号线周围添加地层和电源层，以提供屏蔽和隔离。

-使用过滤电容和磁珠来抑制电磁干扰。

-使用有源和被动的EMI抑制技术，如电磁屏蔽罩和衰减器。

6.综合考虑布局：-在布局时考虑信号走线和连接器的位置，以便在PCB上布线并连接到其他组件。

-将信号线走向控制在最短的长度，以最小化时延和损耗。

-尽量避免信号线的交叉和平行布线，以减小串扰和信号失真。

-对于高速和敏感信号，使用较短的连接线和更紧密的布局。

综上所述，经典的DDR3PCB设计指导涵盖了信号完整性、EMI控制、布局和电源管理等方面的要点。

通过遵循这些指导原则，可以最大程度地提高DDR3系统的稳定性和性能优化。

DDR3的相关设计规范

DDR3的相关设计规范DDR3是一种常见的内存技术，广泛用于计算机系统中。

在使用DDR3内存时，必须遵循一系列的设计规范，以确保系统稳定性和性能。

以下是关于DDR3的相关设计规范的一些重要内容。

一、电气特性：1.电压要求：DDR3的标准电压为1.5V，但也支持1.35V的低电压操作。

设计时必须保证提供准确的电压并控制其稳定性。

2.时钟频率：DDR3支持不同的时钟频率，包括800、1066、1333、1600等。

设计中需要根据具体需求选择合适的频率，并确保时钟信号的完整性。

3. 数据传输速率：DDR3的数据传输速率通常以MBps（兆字节每秒）为单位。

设计中需要考虑数据传输的稳定性和效率。

二、时序特性：1.存取延迟：DDR3内存的存取延迟包括列地址延迟(CL)和行地址延迟(RL)，设计时需要正确配置这些延迟参数，以确保数据传输的准确性和高效性。

2.刷新周期：DDR3内存需要定期进行刷新操作，以保持存储数据的完整性。

设计中需要合理配置刷新周期，以满足DDR3内存的要求。

三、布局和信号完整性：1.PCB布局：DDR3内存的设计需要合理布局PCB，包括安排存储器芯片和其他电路元件的位置、规划数据和时钟信号的传输线路等。

良好的PCB布局可以有效减少信号干扰和传输延迟，提高系统性能。

2.连接器和插槽设计：DDR3内存的连接器和插槽设计也需要满足相关规范，以确保良好的接触和信号传输。

四、时序分析和调整：1.检查时序完整性：在DDR3设计中，需要进行时序分析以确保各个信号的时序关系。

通过综合考虑时钟、数据和控制信号，可以避免时序冲突，提高系统性能。

2.时序调整：如果时序分析发现了冲突或不稳定的信号，可以通过调整内存控制器或相关参数来解决。

时序调整需要综合考虑电气特性和时序要求，以确保稳定的数据传输。

总结起来，DDR3内存的设计规范涉及到电气特性、时序特性、布局和信号完整性等多个方面。

在设计时，必须严格遵守这些规范，以确保DDR3内存的稳定性和性能。

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龙芯CPU DDR3布线设计指导及软件调试说明产品型号：龙芯3A2013年1月龙芯中科技术有限公司阅读指南本手册是龙芯3A、3B及2G芯片的内存软硬件设计指导，分为两部分，第一部分为硬件设计的指导及布线约束文件，第二部分为软件调试说明，适用于针对龙芯3A、3B及2G处理器的主板设计。

修订历史目录第一部分DDR3硬件设计指导 (5)1. 说明 (5)2. 电源设计要求 (5)3、PCB布局及走线要求 (5)3.1 信号分组（DDR3 signal groups） (6)3.2 叠层和布线层使用 (6)3.3 参考平面 (8)3.4 时钟信号组布线要求 (8)3.5 控制信号 (9)3.6 命令信号 (10)3.7 数据信号 (12)3.8 数据选通信号 (13)第二部分DDR3软件调试说明 (15)4. 内存基础知识 (15)5. 龙芯芯片的访存流程 (16)6. Pmon内存初始化代码介绍（3A/B、2G/H） (16)7. 内存故障诊断 (18)第一部分 DDR3硬件设计指导1. 说明本文档为基于龙芯3A、3B及2G芯片的主板设计提供内存设计及layout指导，根据我们针对现有的开发系统的信号测试结果及龙芯CPU的特点，给出了目前我们认为比较合理的内存设计方案。

本方案针对采用DDR3 DIMM插槽的主板设计方案，其它情况我们后续会补充完善，现阶段请跟我们技术人员联系。

2. 电源设计要求Vref信号，该信号电流较小，但是该信号的不稳定会导致时序误差、产生比较大的jitter 等问题，所以需要保证Vref电压值稳定，波动范围小于+-2%。

对于Vref的走线要求：1）走线宽度30mils，推荐走在表层2）距离其它信号走线距离大于20mil，距其它干扰源（power switch，晶振等）250mil 以上3）Vref通过1%的电阻对DIMM_VDD分压产生，在DIMM插槽的每一个Vref引脚和CPU 的每个Vref引脚附近至少放置0.01uF和0.1uF电容各一个，在分压电阻附近放置1个0.1uF 电容。

VTT电压的设计及走线要求1）VTT瞬间电流需求较大，请采用专用的电源芯片产生，禁止使用电阻分压方式2）VTT铺铜走在表层，产生VTT的电源电路距DIMM插槽上的VTT引脚尽量近3）VTT的铺铜平面上靠近DIMM插槽的位置放置4个0.1uF电容，另外需再放1~2个10~22uF的电容。

时钟、命令和控制信号线在内存条上以MEM_VDD作为参考平面，而在Loongson 3A上参考平面为GND。

为解决信号线跨分割带来的信号完整性问题，需要在DIMM条附近增加连接MEM_VDD和GND的电容。

3、PCB布局及走线要求本节主要包括DDR3接口PCB设计指导。

任何偏离该指导中给定的信号拓扑和走线均需要通过仿真和验证，以确定满足DDR3 SDRAM和系统时序要求。

DDR3接口的PCB设计主要包括信号线的线宽/线距、叠层与阻抗控制、走线的长度限制等方面，本文档对于这几个方面都有详细的说明。

对于每个DDR控制器连接2个DIMM插槽的设计，推荐使用下面的信号连接方式：DIMM0 CLK0&1；SCSN0&1；ODT0&1；CKE0DIMM1 CLK2&3；SCSN2&3；ODT2&3；CKE13.1 信号分组（DDR3 signal groups）DDR3接口信号分为4个信号组：时钟、控制、命令、数据和数据选通信号，表1.1 对信号的分组情况进行了说明。

表1.1 DDR3信号分组数据和数据选通组中的每个Byte Lane（Lane0~Lane8）均可和时钟、控制、命令一样，布线时作为一个单独的同组信号看待。

3.2 叠层和布线层使用PCB设计推荐采用6层PCB叠层结构，叠层如图1.1所示图1.1 推荐的六层PCB板叠层结构图（DIMM）表1.2 推荐的六层PCB板叠层信息表（DIMM）3.3 参考平面龙芯3A/3B芯片内部所有DDR信号参考地平面，所以建议板上DDR走线参考地平面，内存条附近增加电源到地平面的电容以解决信号完整性问题。

3.4 时钟信号组布线要求图1.3 时钟信号布线拓扑（DIMM）表1.3 时钟信号组布线指导加一片IDT 公司的DDR3 Clock Zero Delay Buffer 专用芯片，订货型号是ICS671AGI-28LF ，该器件是TSSOP8封装，适用于PCB 空间密集的应用。

3.5 控制信号图1.4 控制信号布线拓扑（DIMM ）表 1.4 控制信号组布线指导3.6 命令信号图1.5 命令信号布线拓扑（DIMM）表 1.5 命令信号组布线指导3.7 数据信号图1.6 数据信号布线拓扑（DIMM）表 1.6 数据信号组布线指导3.8 数据选通信号图1.7 数据选通信号布线拓扑（DIMM ）表 1.7 数据选通信号组布线指导注：按照以上走线规范，我们测试内存控制器工作在296MHz（33MHz外部晶振）时比较稳定，其它频率没有做过多的测试，如果需要其它条件下的走线规范，请等待后续我们的发布的设计指导文件或者直接与我们联系。

第二部分 DDR3软件调试说明4. 内存基础知识内存颗粒组成内存设备的基本单元，也就是我们在内存条上看到的规格相同的一个个小黑块。

目前主流的类型为SDRAM（Synchronized Dynamic RAM）。

SDRAM根据技术发展又分为DDR、DDR2、DDR3等几代产品。

目前主流的是DDR2和DDR3。

内存颗粒的技术规范见JEDEC标准（JESD79-2和JESD79-3）。

该文档可到jedec官网免费下载（）。

下面对关于颗粒的一些重要、易混的概念做一个简单介绍。

1.地址线。

SDRAM使用行列地址线复用技术。

即行地址和列地址共用同一组地址线，因此要分两次发送，先发行地址，再发列地址。

2.颗粒容量：一个颗粒包含的bit位数。

比如：512Mb、1Gb、2Gb等。

3.位宽。

位宽是颗粒中可寻址的最小单元的bit位数，也是一个颗粒的数据线的个数。

目前常见的位宽有x4,x8,x16。

4.Bank。

Bank是颗粒内部的概念，一个颗粒内有多个bank（目前主要是4和8），一组行列地址寻址的是一个bank内的一个存储单元，因此一次完整的寻址还需要提供bank地址。

Bank地址是和行列地址同时发送的。

5.CS（ChipSelect）片选信号。

每个颗粒都有一个CS信号引脚，只有当该信号为低时，颗粒才会接收命令。

6.Rank。

Rank是DIMM条的概念。

一个rank相当于DIMM条的一组SDRAM颗粒，一般也就是DIMM条的一个面。

一个DIMM条可以包含2个Rank，也就是双面的DIMM条。

一个Rank对应一个CS信号，该CS信号用来控制该组的所有SDRAM颗粒。

内存条目前的主流内存条为DIMM（Dual In-line Memory Module，双列直插内存模块）。

内存条分为SO-DIMM（笔记本用的）、UDIMM（Unbuffered DIMM，台式机用的、市面上常见的内存条）、RDIMM（Registered DIMM，多用于服务器）等很多种。

内存条其实就是将多个SDRAM 颗粒拼装在一起，这些颗粒的地址、控制线串连在一起，而数据线并在一起形成DIMM的数据线。

目前的DIMM条数据线个数一般为64位。

因此对于x8的颗粒，需要8个才能形成一组存储单元，对DIMM条寻址时，这8个颗粒都会被命中，因此一次寻址会命中8个字节，这8个字节根据所在的数据线位置来区分。

5. 龙芯芯片的访存流程图1 龙芯2G/H 及龙芯3号芯片的访存流程6. Pmon 内存初始化代码介绍（3A/B 、2G/H ）Pmon 中内存相关部分的代码包含在start.S 中。

内存初始化需要在cache 初始化之后进行。

内存初始化的代码被封装起来了，封装在loongson*_ddr[2]_config.S 中，使用时只需要正确设置输入参数（64位的寄存器s1）。

下面详细介绍s1的设置方法。

s1的低4位（bit[3:0]），用来设置节点ID 和控制器选择。

bit[1:0]对应节点ID ；bit[3:2]对应控制器选择：2’b01---只使用MC0；2’b10---只使用MC1；2’b00---MC0/1都使用。

对于2G/H 、3B 来说，只有MC0，因此bit[3:2]总是应该设置为2’b01.s1的其他位用来设置内存信息。

s1的设置分两种情况：一种是使用内存条上的SPD 自动检测内存条信息，一种是直接手动设置内存信息，包括颗粒类型（DDR2还是DDR3）、行列地址线个数等等。

两种模式，通过配置文件的AUTO_DDR_CONFIG 选项选择。

在前一种自动检测内存信息的情况下，s1的作用是告诉自动检测代码SPD 所在的I2C 总线的地址。

一个节点最多有2个（3A ）内存控制器，每个内存控制器最多连接2个内存条，因此每个节点最多连接4个内存条。

此时使用s1的bit[31:16]来存放4个内存条所连接的I2C 总线的地址（SA2:SA0）。

每4bit 表示一个内存条。

有效值为0x0～0x7，0x8～0xf 表示没有连接内存条。

s1的bit[31:16]分别对应MC1的Slot1（MC1的CS3/2）、MC1的Slot0（MC1的CS1/0）、MC0的Slot1（MC0的CS3/2）、MC0的Slot0（MC0的CS1/0）。

在后一种手动设置内存信息的情况下，共使用24bit 来设置一个控制器的内存信息。

s1的bit[63:40]对应MC1，bit[31:8]对应MC0.这24位的含义可以通过查看ddr_config_define.h 中的注释来具体了解。

下面对常用的一些设置进行说明。

比如，一个常用的设置为0x c1e30404（红色部分），表示常见的DDR3双面2GB UDIMM 内存条。

下面将这24位分为几个位域来说明。

位域划分如下：0x c 112 e 3 34 045 04。

位域的值都用十六进制表示。

（1）对于相应容量的x16颗粒，右边的域值增加1. （2）如果使用32位的数据宽度，右边的域值增加8. 对于位域3（bank 数、地址mirror 、列地址数），（1）颗粒bank 数为4时，右边的域值减去8. 对于位域4（cs_map ），这个位域的4个bit （3～0）分别表示MC 的片选信号CS3～CS0上面是否连接有内存颗粒。

这个域值与PCB 的走线相关。

下面以使用内存条的主板为例来据正反面是否都有内存颗粒来判断。

但华芯的一种DDR3 2GB RDIMM内存条，正反面都有颗粒，但仍属于单面内存条。

512M字对于位域5（内存容量），表示这个控制器可以使用的内存容量大小，单位为龙芯2H、3A/B使用软件训练的方法（ARB_level）来设置控制器需要的一些延时参数，一般不需要手动调整。