哈工大数字逻辑第5章

Some Examples
A device with majority judge function
ABC 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F 0 0 0 1 0 1 1 1 +5V
majority judge
A BC 00 01 11 10
Find the shared term by AND
operation; Use the shared
term for minimization !
＝ C＋ ABC ＋ABC
＝ C ＋ ABC
Design of Multiple-Output Circuits
F1
A BC 00 01 11 10 0 0 1 1 1 1 1 1 0 0 A
Unit 5 Multi-Level Gate Circuits

Multi-Level Gate Circuits Design of Two-Level Circuits Design of Multiple-Output Circuits Some Examples
Example 1
Design of Two-Level Circuits
2. Design a minimum two-level NOR-NOR circuit Given: a minimum sum-of-products expression
• Method 1： (FD)D
F=AC+BC+AB FD = (A+B) • (B+C) • (A+C) =ABC+ABC
×
F F +
0 0 1 0
0 1
1 1
0 1
F=AB+AC+BC
A B AC
BC
Example 2
Some Examples
Weight Lifting Competitions Evaluation System


one chief referee and two deputy umpires
F
+
A B C
=ABC • ABC
F=(FD)D=(A+B+C)+ (A+B+C)
A B C
+
Design of Two-Level Circuits
Given: a minimum product-of-sums expression • Method 2:
1. Find a minimum sum-of-products expression for F. 2. Draw the corresponding two-level OR-AND circuit. 3. Replace all gates with NOR gates leaving the gate interconnections unchanged. If the output gate has any single literals as inputs, complement these literals.


Design of Two-Level Circuits
Design of Multiple-Output Circuits Some Examples
Multi-Level Gate Circuits
Assume: all variables and their complements are available as circuit inputs. The number of levels of gates—— The maximum number of gates cascaded in series between a circuit input and the output 1. AND-OR circuit : a two-level circuit. 2. OR-AND circuit : a two-level circuit. 3. OR-AND-OR circuit : a three-level circuit. 4. Circuit of AND and OR gates:
Multi-Level Gate Circuits F = X1Y1 +X2Y1Y2 +X1X2Y2
Y1Y2 X1X2
00 01 11 0
1 1 1
10 0 0
1
00 01 11 10
0 0
1 1
0 0 0 0
0
Multi-Level Gate Circuits ③ And-Or gates F = X1Y1 +X2Y1Y2 +X1X2Y2
no particular ordering of the gates; the output gate may be either AND or OR.
Example 4
Multi-Level Gate Circuits
Three levels, Five gates, 12 gate Inputs
F=AC+BC+AB =ABC+ABC F =ABC+ABC F F
+
A B C A B C
Unit 5 Multi-Level Gate Circuits

Multi-Level Gate Circuits


Design of Two-Level Circuits
Design of Multiple-Output Circuits

Some Examples
Design of Multiple-Output Circuits
Design: two-level NAND-NAND circuit F2
F1 ＝C＋AB, F2 ＝BC＋ABC
F1
F1
F2
ABC
B C
A B
C
C ABC
B C
F1 ＝C ＋ AB ＝ C ＋ AB（C＋ C）
F X ,Y , Z XYZ 1,6,7 XYZ 0,2,3,4,5
F X ,Y , Z XYZ 0,2,3,4,5 XYZ 1,6,7
NAND and NOR gates: be generally faster and use fewer components than AND or OR gates.
Design of Two-Level Circuits
1. Design a minimum two-level NAND-NAND circuit Given: a minimum sum-of-products expression
• Method 1： (F' )'
F=AB+AB
=AB+AB A B A B
① Input：
X1, X2, Y1, Y2
Output: F
F=1 while X>Y
Multi-Level Gate Circuits ② Truth table
X1 X2 Y1 Y2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 F 0 0 0 0 1 0 0 0 X1 X2 Y1 Y2 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 F 1 1 0 0 1 1 1 0
Result is shown by a green light and a red light

Both of them are lighted : Success
Only the red one is lighted : Discuss


Otherwise: Unsuccess
Some Examples Rules: 1. If all the referees press their buttons, both of the two lamps will be lighted. 2. If there are two referees (one of them must be the chief referee ) press their buttons，both of the two lamps will be lighted 3. If there are two referees (both of them are deputy umpires) press their buttons，or only the chief referee presses his button, the red lamp will be lighted 4. Otherwise, both of the lights go out.
——Multi-Level Gate Circuits NAND and NOR Gates
张彦航
School of Computer Science Zhangyanhang@
Unit 5 Multi-Level Gate Circuits

Multi-Level Gate Circuits
X1 Y1 X2 Y2 F
Multi-Level Gate Circuits
④. Nand-Nand gates：
F = X1Y1 +X2Y1Y2+X1X2Y2 = (X1Y1) (X2Y1Y2 ) (X1X2Y2)
X1 Y1 X2 Y2 F
Unit 5 Multi-Level Gate Circuits