数字预失真关键技术-Part3-V5

• DSP Builder
– Works with MATLAB/Simulink to provide an FPGA development environment that is ideal for systems engineers
– Works with SOPC Builder to give a C-based DSP design flow
6
用DSPbuilder设计FIR滤波器
7
基于FIR的记忆多项式预失真器设计
x(n)
FIR0 Z-1 Z-1
a1,0 ×
a1,1
×
∑
× a1,2
x(n)|x(n)|
FIR1
z(n) ∑
x(n)|x(n)|11
FIR11
基于FIR的记忆多项式预失真器由无记忆多项式子系统、FIR滤波器 群和加法器组成。
局限1 无法处理非线性模型
wM−1, wM−2,...,w1, w0
局限2 线性阵列的吞吐量有限 ，实时性差
新脉动阵列---三角部分
// //
P*M-1
N-M+1 预加阵列
0 0 0 0 0 x(N) x(M-1) x(M)
x(2)
R00
9注意此处是 P=3,M=2的特 例
0 0 0 0 0 x(N-M+1)
temp = λ * x2 + Rin 2
R = temp s = Rin / temp c = λ1/2 * R / temp
初始化 : cin = 1 sin = 0 R=0
新阵列的三角阵列和功能函数
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新脉动阵列-逆向阵列部分
Wout2
Wout1
R
Uin = 0时，Wout1 = Word Core
13
x(n),x(n−1),...,x(M −1),x(M) x(n),x(n −1),...,x(M −2),x(M −1) x(n), x(n − 1),..., x(2), x(1) y(n), y(n−1),...,y(M +1), y(M)
传统脉动阵列
Software Implementation (Nios)
Programmable Logic
Implementation
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RF 板 – 全面解决方案
From Ch. Card (LVDS w/ CDR)
Input Fmt &
Gain Cntrl
I
RRC Filter
Interpolation
~100 entries 12 bit Wordlength
Adaptive Est.
Altera MegaCore IP
Delay Matching
R
S
Compare & Estimate
Embedded Processor
FFT
Loop Delay Estimator
I&Q Demodulator
Q1
In
Qn
Cmplx
Mult
Delay Matching
.. .. Update I1 Q1
LUT
In
Qn
Sn+1=Sn-α*escale Rn+1=Rn-α*erotate
α= tan-1 (.)
Verror
数据流
From PA
DDC
FFT
Loop Delay
Meas
(.) __ Gain
H/W Accelerator
Uin
Wout1 = Wout 2 = Uin / R
Wout Uout
R
Uin = 0 Win = 0时，Uout = 0 Uin Uout = Uin − R *Win
Win
Wout = Win
新阵列的逆向阵列结构图和功能函数 16
新脉动阵列的记忆项式模型实现
三角阵列QR分解所实现的结果 R00*w0 +R01*w1 +R02*w2 +R03*w3 +R04*w4 +...+R0n*wn =U0 R11*w1 +R12*w2 +R13*w3 +R14*w4 +...+R1n*wn =U1 R22*w2 +R23*w3 +R24*w4 +...+R2n*wn =U2 R33*w3 +R34*w4 +...+R3n*wn =U3 R44*w4 +...+R4n*wn =U4 # Rnn*wn =Un
0 0 0 0 0 y(N) y(M+1) y(M)
y(2)
U0
U1
U2
U3
U4
U5
x(n),in
初始化 :
x(n)in x(n)out
x(n)in x(n),in = 0
x(n)in = 0
x(n)out
=
x(n)
, in
* x(n)in
Rin cout Rout = c * Rin − λ1/ 2 * s * Rin
第四节 非线性建模及预失真性能快速评估软件介绍
实施数字信号处理算法的DSP/FPGA平台
自适应数字基带预失真功率放大器框图
数字预失真器开发平台
• DSP Board: – Dual processors Tiger-Sharc TS201: – Core clock : 500MHz – Internal data memory:
逆向阵列实时处理权值的依据
UM−1 w = M−1
RM−1,M−1
∑ wk
=1 Rkk
(Uk
n
− Rkjwj)
j=k+1
k =M−2,M−3,..0.
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I Altera NiosII DPD参数提取解决方案
-
I
To DUC
Q Q
Table Address
Calc (I2 +Q2)1/2
Q
I
LUT (I & Q)
– Simple/less hardware required
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第三章 数字预失真电路设计及实现
第一节 基于FPGA电路的预失真电路设计 第二节 预失真器参数的实时提取及实现 第三节 基于ASIC电路的数字预失真器设计及实现
1. Intersil数字预失真线性化解决方案介绍 2. PMC-Sierra数字预失真线性化解决方案介绍 3. TI数字预失真线性化解决方案介绍 4. Optichron数字预失真线性化解决方案介绍
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Optional FIFO, Memory, Other Logic
Nios Processor
Integer Mult / Complex Mult
定制指令实例
Example
ALU Only
ALU +
Intgr Mult
ALU + Cmplx Mult
Loop Time (us)
11.190 0.560
• Leverage Large Existing Code
100
Soft Core Advantages
Base
• Flexibility
• Low Cost
50
• Portable Design
• Scalability
• Obsolescence Proof
20
• Fits Broad Range of Altera PLD Families
Calc (I2 +Q2)1/2
Arctan
I Delay
Matching
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主要实现部分
• Forward path: I,Q multipliers • Lookup table: Dual port memory • Feedback path
– Nios with custom instructions – CORDIC acceleration – Multiply acceleration
第四节 非线性建模及预失真性能快速评估软件介绍
12
自适应算法实现预失真器参数的提取
Performance (Dhrystone MIPS 2.1)
Hard Core Advantages
• High Performance 922TDMI
200
• Time-to-Market
• Lots of On-Chip Memory
– Trigonometric – Hyperbolic – Logarithmic
• Iterative solution that uses only shifts and adding/subtracting
– High performance as no multiplications and divisions
Q
RRC Filter
Interpolation
Stratix MAC Block Stratix Tri-Matrix Altera MegaCore IP H/W Accelerator
To Channel Card (LVDS w/CDR) Q
Resampler Resampler
Table Address
R = λ1/2 * c * R + s* * Rin
Rout sout cout = c
sout = s
初始化 : c =1 s=0 R=0
x(n)in
x(n)in 初始化 :
Rin
xM −1 (n)out
x(n)in = 0 xM −1 (n)out = x(n)in