自动控制毕业论文中英文资料外文翻译--模块化安全铁路信号计算机联锁系统

中文2570字

外文文献翻译

院、部：电气与信息工程学院

学生姓名：

指导教师：职称讲师

专业：自动化

班级： 09级01班

完成时间： 2013.06.06

出处：Computing, Communication, Control, and Management, 2008. CCCM'08. ISECS International Colloquium on. IEEE, 2008, 1: 538-541

Component-based Safety Computer of Railway Signal

Interlocking System

1 Introduction

Signal Interlocking System is the critical equipment which can guarantee traffic safety and enhance operational efficiency in railway transportation. For a long time, the core control computer adopts in interlocking system is the special customized high-grade safety computer, for example, the SIMIS of Siemens, the EI32 of Nippon Signal, and so on. Along with the rapid development of electronic technology, the customized safety computer is facing severe challenges, for instance, the high development costs, poor usability, weak expansibility and slow technology update. To overcome the flaws of the high-grade special customized computer, the U.S. Department of Defense has put forward the concept：we should adopt commercial standards to replace military norms and standards for meeting consumers’demand [1]. In the meantime, there are several explorations and practices about adopting open system architecture in avionics. The United Stated and Europe have do much research about utilizing cost-effective fault-tolerant computer to replace the dedicated computer in aerospace and other safety-critical fields. In recent years, it is gradually becoming a new trend that the utilization of standardized components in aerospace, industry, transportation and other safety-critical fields.

2 Railways signal interlocking system

2.1 Functions of signal interlocking system

The basic function of signal interlocking system is to protect train safety by controlling signal equipments, such as switch points, signals and track units in a station, and it handles routes via a certain interlocking regulation.

Since the birth of the railway transportation, signal interlocking system has gone through manual signal, mechanical signal, relay-based interlocking, and the modern computer-based Interlocking System.

2.2 Architecture of signal interlocking system

Generally, the Interlocking System has a hierarchical structure. According to the function of equipments, the system can be divided to the function of equipments; the system can be divided into three layers as shown in figure1.

Man-Machine Interface layer

Interlocking safety layer

Implementation layer

Outdoor

equiptments

Figure 1 Architecture of Signal Interlocking System

3 Component-based safety computer design

3.1 Design strategy

The design concept of component-based safety critical computer is different from that of special customized computer. Our design strategy of SIC is on a base of fault-tolerance and system integration. We separate the SIC into three layers, the standardized component unit layer, safety software layer and the system layer. Different safety functions are allocated for each layer, and the final integration of the three layers ensures the predefined safety integrity level of the whole SIC. The three layers can be described as follows:

(1) Component unit layer includes four independent standardized CPU modules. A hardware “SAFETY AND” logic is implemented in this year.

(2) Safety software layer mainly utilizes fail-safe strategy and fault-tolerant management. The interlocking safety computing of the whole system adopts two outputs from different CPU, it can mostly ensure the diversity of software to hold with design errors of signal version and remove hidden risks.

(3) System layer aims to improve reliability, availability and maintainability by means of redundancy.

3.2 Design of hardware fault-tolerant structure

As shown in figure 2, the SIC of four independent component units (C11, C12, C21, C22). The fault-tolerant architecture adopts dual 2 vote 2 (2v2×2) structure, and a kind of high-performance standardized module has been selected as computing unit which adopts Intel X Scale kernel, 533 MHZ.

The operation of SIC is based on a dual two-layer data buses. The high bus adopts the