第四章静态功耗优化技术

A cached CPU subsystem can typically be dormant or inactive for long periods, making power gating attractive. But there are some trade-offs that must be considered:
• Floor planning, power planning, grids. Multiple power domains require more careful and detailed floorplanning. The power grids become more complex. • Board level issues. Multi-voltage designs require additional resources on the board – additional regulators to provide the additional supplies. • Power up and power down sequencing. There may be a required sequence for powering up the design in order to avoid deadlock.

In any event, we are faced with architectural trade-offs between • the amount of leakage power savings that is possible • the entry and exit time penalties incurred • the energy dissipated entering and leaving such leakage saving modes • the activity profile (proportion and frequency of times asleep or active)
• The device driver may be required to explicitly load/restore key state or initiate hardware sequencer control as part of the sleep/wakeup sequence, but this places a significant burden on software. • A better approach may be for the peripheral to store key state internally during sleep mode, but this requires special circuitry and additional control.
4.3 Level Shifter Placement
•高推低时，Level Shifter使用低电压，故 一般放在低电压域，因其使用低电压
•两电压域的模块距离较远时 ，可插入 Buffer，BUFFER使用高电压
•低推高时，Level Shifter一般放在高电压域，但因其
使用高、低两个电压 ，低压要象信号线一样连出 Since the output driver requires more current than the input stage, we place the level shifter in the 1.2V domain. placing the level shifters in the destination domain
A peripheral subsystem may have a much better defined profile than a CPU. But there are still some trade-offs. In particular, it may be necessary to restore state quickly on wake-up to maximize power savings:
4.4 多电压设计时的时序问题
•Clock Skew •静态时序分析：都要针对多电压域进行
第五章 漏电流控制技术
The Power Crisis from Intel
1200 15 mm Die 1000
Power (W)
800 600 400 200 0
Leakage Active
0.25u 0.18u 0.13u 90nm
• Dynamic Voltage and Frequency Scaling (DVFS): an extension of MVS where a larger number of voltage levels are dynamically switched to follow changing workloads. • Adaptive Voltage Scaling (AVS): an extension of DVFS where a control loop is used to adjust the voltage.
就是最简单的 multi-voltage设计（SVS）也 给设计增加了难度 • Level shifters. Signals that go between blocks that
use different power rails often require level shifters • Characterization and STA. With a single supply for the entire chip, timing analysis can be done at a single performance point. The libraries are characterized for this point, and the tools perform the analysis in a straight-forward manner. With multiple blocks running at different voltages, and with libraries that may not be characterized at the exact voltage we are using, timing analysis becomes much more complex
Clock-Gating 只关断时钟，节省动态功耗，静态功 耗不变。Power-Gating是关断电源，动态、静态功 耗都不存在（还存在开关管的漏电）
2、Power Gating 的适用性、问题及解 决的途径概述


power gating is more invasive than clock-gating in that it affects inter-block interface communication and adds significant time delays to safely enter and exit power gated modes. Shutting down power to a block of logic may be scheduled explicitly by control software as part of device drivers or operating system idle tasks. Alternatively it may be initiated in hardware by timers or system level power management controllers.
第四章 多电压域设计技术 （Multi-Voltage Domain）
4.1 多电压域设计
VLSI发展的一个重要趋势是SOC 工艺的进步使SOC成为可能； 设计复杂度的提高需要新的设计方法 SOC中各部分性能要求不尽相同，可工作在不同电 压下，性能要求高的工作的高电压域，反之。。。 同一部分根据其工作负荷也可工作在不同电压
低压设计的问题：漏电流
为什么要低电压设计？

小尺寸器件的要求
漏端热载流子退化临界电场 Em<0.2MV/cm
0.35um击穿电压6V左右 一般要求工作电压为击穿电压的1/3~1/2 一般按恒定电场Scale Down

低功耗设计的要求
5.2 漏流主要来源
PN Reverse-Bias Current (I1) Weak Inversion (I2)（亚域电流） Gate-Induced Drain Leakage (I3) Gate Oxide Tunneling (I4)
• Power gating the entire CPU provides very good leakage power reduction. But wake-up-time response to an interrupt has significant system level design implications. • If the cache contents are lost every time the CPU is powered down then there is likely to be a significant time and energy cost in all the bus activity to refill the cache when it is powered up. • The net energy savings depend on the sleep/wake activity profile as to how much energy was saved when power gated versus the energy spent in reloading state.