LTSpice学习笔记精编版

LTspice

1.变压器仿真的简单步骤：

A.为每个变压器绕组绘制一个电感器

B.采用一个互感(K) 描述语句通过一条SPICE 指令对其实施耦合：

K1 L1 L2 1

K 语句的最后一项是耦合系数，其变化范围介于0 和1 之间，1 代表没有漏电感。对于实际

电路，建议您采用耦合系数= 1 作为起点。

每个变压器只需要一个K 语句；LTspice 为一个变压器内部的所有电感器应用了单一耦合系数。

下面所列是上述语句的等效语句:

K1 L1 L2 1

K2 L2 L3 1

K3 L1 L3 1

C.采用“移动” (F7)、“旋转” (Ctrl + R) 和“镜像” (Ctrl + E) 命令来调节电感器位置以与变压器的

极性相匹配。添加K 语句可显示所含电感器的调相点。

D.LTspice 采用个别组件值(在本场合中为个别电感器的电感) 而非变压器的匝数比进行变压器

的仿真。电感比与匝数比的对应关系如下：

电感至匝数比

例如：对于1:3 和1:2 的匝数比，输入电感值以产生1:9 和1:4 的比值：

2.一般来说压是对地，如果你想知某元件俩端的电压该如何呢？设一参考点，先点小人，然后在电路图

的空白处点右键，找黑白电笔Set probe reference，也可从VIEW找。按键盘上ESC可去黑白电笔。

3.Die Impulsantwort 脉冲响应。

4.To create an LTspice model of a given MOSFET, you need the original datasheet and the pSPICE model of

that MOSFET.

The parameters needed to define a MOSFET in LTspice are as follows:

Rg Gate ohmic resistance

Rd Drain ohmic resistance (this is NOT the RDSon, but the resistance of the bond wire)

Rs Source ohmic resistance.

Vto Zero-bias threshold voltage.

Kp –Transconductance coefficient

Lambda Change in drain current with Vds

Cgdmax Maximum gate to drain capacitance.

Cgdmin Minimum gate to drain capacitance.

Cgs Gate to source capacitance.

Cjo Parasitic diode capacitance.

Is Parasitic diode saturation current.

Rb Body diode resistance.

Rg, Rd and Rs are the resistances of the bond wires connecting the die to the package.

Vto is the turn on voltage of the MOSFET.

Kp is the transconductance of the MOSFET. This determines the drain current that flows for a given gate source voltage.

Lambda is the change in drain current with drain source voltage and is used with Kp to determine the

RDSon.

Cgdmax and Cgdmin are the minimum and maximum values of the gate drain capacitance and are normally graphed in the MOSFET datasheet as Crss. The capacitance of a capacitor is inversely proportional to the distance between its plates. When the MOSFET is turned on, distance between the gate and the conducting channel of the drain is equal to the thickness of the insulating gate oxide layer (which is small) so the gate drain capacitance is high. When the MOSFET is turned off, the gate drain region is large, making the gate drain capacitance low. This can be seen on the plot of Crss.

Cgs is the gate source capacitance. Although it changes slightly with gate source voltage, LTspice assumes it is constant.

Is is the parasitic body diode saturation current.

Rb is the series resistance of the body diode.

The Fairchild FDS6680A MOSFET is defined in LTspice by the line

.model FDS6680A VDMOS(Rg=3 Rd=5m Rs=1m Vto=2.2 Kp=63 Cgdmax=2n Cgdmin=1n Cgs=1.9n Cjo=1n Is=2.3p Rb=6m mfg=Fairchild Vds=30 Ron=15m Qg=27n)

Note: the characteristics Vds, Ron and Qg are actually ignored by LTspice. These are only added to aid the user to compare MOSFETs.

Therefore an example template MOSFET model is

.model XXXX VDMOS(Rg= Rd=5 Rs=1 Vto= Kp= Cgdmax= Cgdmin= Cgs= Cjo= Is= Rb= )

We are now going to construct a MOSFET model for the SUM75N06 and SUM110N04 low ON resistance MOSFETs from Vishay

.model SUM75N06-09L VDMOS(Rg=1.5 Rd=0m Rs=25m Vto=2.0 Kp=75 Cgdmax=1.2n Cgdmin=150p Cgs=2n Cjo=1.2n Is=1p Rb=0)

.model SUM110N04 VDMOS(Rg=1.5 Rd=0m Rs=0.86m Vto=1.85 Kp=180 Cgdmax=3n Cgdmin=900p

Cgs=14.5n Cjo=4.9n Is=33.4p Rb=0)

The SPICE models can then be testing using these test jigs: