台湾清华RTlab实验室BellagioOpenMax的Code_Trace

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多尺度特征融合的脊柱X线图像分割方法

脊柱侧凸是一种脊柱三维结构的畸形疾病，全球有1%~4%的青少年受到此疾病的影响[1]。

该疾病的诊断主要参考患者的脊柱侧凸角度，目前X线成像方式是诊断脊柱侧凸的首选，在X线图像中分割脊柱是后续测量、配准以及三维重建的基础。

近期出现了不少脊柱X线图像分割方法。

Anitha等人[2-3]提出了使用自定义的滤波器自动提取椎体终板以及自动获取轮廓的形态学算子的方法，但这些方法存在一定的观察者间的误差。

Sardjono等人[4]提出基于带电粒子模型的物理方法来提取脊柱轮廓，实现过程复杂且实用性不高。

叶伟等人[5]提出了一种基于模糊C均值聚类分割算法，该方法过程繁琐且实用性欠佳。

以上方法都只对椎体进行了分割，却无法实现对脊柱的整体轮廓分割。

深度学习在图像分割的领域有很多应用。

Long等人提出了全卷积网络[6]（Full Convolutional Network，FCN），将卷积神经网络的最后一层全连接层替换为卷积层，得到特征图后再经过反卷积来获得像素级的分类结果。

通过对FCN结构改进，Ronneberger等人提出了一种编码-解码的网络结构U-Net[7]解决图像分割问题。

Wu等人提出了BoostNet[8]来对脊柱X线图像进行目标检测以及一个基于多视角的相关网络[9]来完成对脊柱框架的定位。

上述方法并未直接对脊柱图像进行分割，仅提取了关键点的特征并由定位的特征来获取脊柱的整体轮廓。

Fang等人[10]采用FCN对脊柱的CT切片图像进行分割并进行三维重建，但分割精度相对较低。

Horng等人[11]将脊柱X线图像进行切割后使用残差U-Net 来对单个椎骨进行分割，再合成完整的脊柱图像，从而导致分割过程过于繁琐。

Tan等人[12]和Grigorieva等人[13]采用U-Net来对脊柱X线图像进行分割并实现对Cobb角的测量或三维重建，但存在分割精度不高的问题。

以上研究方法虽然在一定程度上完成脊柱分割，但仍存在两个问题：（1）只涉及椎体的定位和计算脊柱侧凸角度，却没有对图像进行完整的脊柱分割。

恒基生物 Betaine Solution 用户指南说明书

B0300ug Rev 04/231User GuideBetaine Solution5 M, PCR ReagentB0300Product DescriptionBetaine, also called trimethylglycine orN,N,N-triethylammonium acetate, is an analog of glycine with three methyl groups.1 Betaine is a PCR enhancing reagent that is widely used for improving the yield and specificity of PCR products, especially for the amplification of targets rich in GC content or those that form secondary structures resulting in poor yield. Betaine facilitates DNA strand separation and decreases secondary structure of GC-rich regions.2 Betaine has been broadly used to optimize multiplex and ‘long and accurate′ polymerase chain reaction (LA-PCR). The addition of 1.0-1.7 M aqueous betaine to a PCR mixture has been reported to reduce the base pair composition dependence on DNA strand melting.3Quality Specifications•Suitable for molecular biology applications with high GC content. Upon addition of BetaineSolution to 1.2 M, a 994 bp human gene target with 64% GC content is amplified via PCR with JumpStart™ Taq DNA Polymerase, while no amplification is detected in the absence of Betaine Solution.•DNase free: No degradation of HindIII-digested lambda phage DNA detected after incubation with 1.2 M Betaine Solution for 16 hours at 37 °C. •RNase free: No degradation of tRNA detected after incubation with 1.2 M Betaine Solution for 16 hours at 37 °C.•Endonuclease free: No nicking or linearization of pBR322 plasmid DNA detected after incubation with 1.2 M Betaine Solution for 16 hours at 37 °C. Applications• Loop-mediated isothermal amplification (LAMP)4 • PCR for genomic DNA amplification 5 •Quantitative PCR (qPCR)6 and RT-qPCR• PCR amplification of CGG repeats in genomic DNA 7•Reverse transcription for single cell cDNA library preparation via Smart-seq-total 8Intended UseThis product is for R&D use only. Not for drug,household, or other uses. Please consult the Safety Data Sheet for information regarding hazards and safe handling practices.StorageStore at 2-8 °C.Directions for UseAdd Betaine to a final concentration of 1.0 – 1.7 M in a nucleic acid amplification mixture prior to initiation of thermocycling/heating.References1. Day CR and Kempton SA. Biochim biophys acta.,1860(6):1098-106 (2016). 2. Jensen MA, et al. PLoS ONE, 5(6):e11024.(2010). 3. Rees WA, et al. Biochem., 32(1):137-44. (1993). 4. Kostic T, et al. Appl Microbiol Biotechnol.,99(18): 7711–7722. (2015). 5. Azaiez H, et al. Hum Mutat., 24(4):305-11.(2004). 6. Milte CM, et al. Eur J Nutr., 57(1):363-372.(2018). 7. Saulto A, et al. J Mol Diagn., 7(5):605-12.(2005). 8. Isakova A, et al. Proc Natl Acad Sci USA.,118(51):e2113568118. (2021).The life science business of Merck operatesas MilliporeSigma in the U.S. and Canada.Merck and Sigma-Aldrich are trademarks of Merck KGaA, Darmstadt, Germany or its affiliates.All other trademarks are the property of their respective owners. Detailed information on trademarks is available via publicly accessible resources.© 2023 Merck KGaA, Darmstadt, Germany and/or its affiliates. All Rights Reserved.B0300ug Rev 04/232Product OrderingOrder products online at .Description Catalogue NumberJumpStart™ Taq DNAPolymerase D4184Deoxynucleotide (dNTP)Mix, containing 10 mMeach of dATP, dCTP, dGTP,and dTTP sodium saltsD7295 Nuclease-free water W1754Custom ordered primersspecific to gene target OLIGO GenElute™-E Single SpinDNA Cleanup Kit EC600 GenElute™ PCRClean-Up Kit NA1020 GenElute™ GelExtraction Kit NA1111Precast Agarose Gels P6222 P5472 P6097 P5972 P57221 kb DNA Ladder D0428 Water, Microbial DNA-free MBD0025 Nuclease-Free Water,for Molecular Biology W4502 JumpStart™ Taq Ready Mix P2893 RED Taq® Ready Mix P0982 Glycerol-free JumpStart™Taq DNA Polymerase D9310 DMSO D8418 Single strandbinding protein S3917 BST Max DNA Polymerase SRE0113 NoticeWe provide information and advice to our customers on application technologies and regulatory matters to the best of our knowledge and ability, but without obligation or liability. Existing laws and regulations are to be observed in all cases by our customers. This also applies in respect to any rights of third parties. Our information and advice do not relieve our customers of their own responsibility for checking the suitability of our products for the envisaged purpose. The information in this document is subject to change without notice and should not be construed as a commitment by the manufacturing or selling entity, or an affiliate. We assume no responsibility for any errors that may appear in this document. Technical AssistanceVisit the tech service page at/techservice.Terms and Conditions of SaleWarranty, use restrictions, and other conditions of sale may be found at /terms. Contact InformationFor the location of the office nearest you, go to /offices.。

FPGA_验证流程综述

FPGA验证流程综述张勇陈逸韬深圳市国微电子有限公司广东深圳 518000摘要：现场可编程门阵列（Field-Programmable Gate Array，FPGA），也被称为FPGA芯片，在通信、安防、工业等领域有着举足轻重的作用。

随着FPGA芯片的规模不断扩大、性能不断提升，其模块数量、电路网表规模、连接复杂度也随之增加。

在此趋势下，如何有效地提升大规模FPGA电路的验证效率与验证完备性变得更为重要。

一个完整的、有针对性的、结构性的验证流程方法，能更全面地对电路设计情况进行覆盖性检查，确保FPGA芯片功能的正确性。

详细叙述从底层到顶层（模块级、子系统级、全芯片级）的FPGA芯片验证方式，包括它们各自的验证方法、流程与侧重等细节，探讨了这种方式是如何帮助FPGA验证工作进行的。

关键词：FPGA芯片验证效率验证流程方法全芯片级验证中图分类号：TN40;TN791文献标识码：A 文章编号：1672-3791(2024)04-0020-03 An Overview of the FPGA Verification ProcessZHANG Yong CHEN YitaoShenzhen State Microelectronics Co., Ltd., Shenzhen, Guangdong Province, 518000 China Abstract:The field-programmable gate array (FPGA) is also known as the FPGA chip, and it plays a crucial role in fields such as communications, security and industry. As the scale of FPGA chips continues to expand and their performance continues to improve, their number of modules, size of circuit netlists and connection complexity also increase. In this trend, how to effectively improve the verification efficiency and completeness of large-scale FPGA circuits has become more important. A complete, targeted and structured verification process method can compre⁃hensively check the coverage of circuit design and ensure the correctness of the function of FPGA chips. This paper detailedly describes the verification method of FPGA chips from the bottom layer to the top layer (module-level, subsystem-level, full chip-level), including details such as their respective verification methods, processes and em⁃phases, and explores how this method helps FPGA verification work.Key Words: FPGA chip; Validation efficiency; Validation process method; Full chip-level validation1 FPGA分层级验证1.1 验证层级分类根据验证侧重点，验证分为3个层级：模块级、子系统级与全芯片级。

LMS Test.Lab中文操作指南全

LMS b中文操作指南比利时LMS国际公司北京代表处2009年　６月内容¾ Desktop桌面操作¾ Geometry几何建模¾ Signature信号特征测试分析¾ Impact锤击法模态测试¾ Spectral Testing谱分析¾ Modal Analysis模态分析¾ Modification Prediction模态修改预测¾ ODS工作变形分析¾ OMA运行模态分析LMS b中文操作指南— Desktop桌面操作比利时LMS国际公司北京代表处2009年2月LMS b中文操作指南— Desktop桌面操作目录1.开始 (2)2.浏览数据 (3)3.显示数据 (4)3.1.测试的数据 (4)3.2.图形拷贝 (8)3.3.几何图形显示 (8)4.数据调理 (10)5.搜索功能 (11)6.Documentation 界面 (13)6.1.添加附件 (13)6.2.添加模板 (14)6.3.添加用户属性 (15)7.导入外部数据 (17)1. 开始¾ 启动 LMS b Desktop 从开始菜单 Æ 所有程序 Æ LMS b 9AÆ Desktop 或者通过桌面的快捷图标软件打开后，通过底部的导航条，可以看到两个界面：Documentation 和 Navigator 。

默认会打开一个空白的Project ，软件激活“Navigator”页面中的“Data Viewing”子页面。

可以浏览数据，图形显示数据。

页面在LMS b 资源管理器中可以看到Project ，另外还有：My Computer: 资源管理器最后一个项目。

可以浏览您电脑中的数据。

My Links: 此处可以链接常用Project 的快捷方式，首先从“My Computer”找到Project ，右键单击Copy ，然后到 “My Links”右键单击Paste as link 。

实验室专业术语中英文翻译对照

实验室专业术语中英文翻译对照自动化实验室Automation Lab语言实验室Language Lab现代产品设计与制造技术实验室Modern Product Design & Manufacturing Tec hnology Lab计算机集成制造实验室Computer Integrated Manufac turing Sy stem Lab先进设计技术实验室Adv anced Design Tec hnology Lab机械设计基础实验室Machine Design Lab包装工程实验室Pac k ing Engineering Lab机械制造技术实验室Machine Manufacturing Lab精密机械测量技术实验室Precise Mac hine M easuring Tec hnology Lab数控技术与传动控制实验室NC Technol ogy & Trans mission C ontrol Lab设计创新实验室Innov ati on & Practic e Lab机械CAD中心Mechanic al CAD Center工作设计与时间研究实验室Job Design & Time Study Lab企业资源规划实验室Enterprise Resource Planning Lab系统仿真与设施规划实验室Sy s tem Si mulation & Facility Layout Lab人因工程实验室Human Fac tors & Ergonomics Lab液压与气动实验室Hy draulic & Pneumatic Lab汽车性能和结构实验室Auto Performanc e & C onstruc tion Lab发动机性能实验室Engine Perfor mance Lab汽车电子电气实验室Auto Elec tronic & Electric Lab数字媒体技术实验室Digital Media Technolog y Lab数字媒体技术基础实验分室Digital Media Technolog y Foundati on Lab数字影视实验分室Digital TV & Film Lab计算机动画与虚拟现实实验室Computer Animation & Virtual Reality Lab先进控制技术实验室Adv anced Control Tec hnology Lab楼宇智能化实验分室Intelligent Buildi ng Lab智能测控实验分室Intelligent Meas urement & Control Technolog y Lab运动控制与图象识别系统实验分室Motion C ontrol & Image R ecognition Sy stem Lab控制网络实验分室Control Network Lab自动控制系统实验分室Automatic Control System Lab自动控制原理实验分室Automatic Control Principl e Lab自动化学科创新实验室Automation Subject Innovation Lab电力电子技术分室Power El ectronics Technolog y Lab计算机控制技术实验分室Computer Control Technolog y Lab高压实验室High Voltage Technolog y Lab电机与控制实验室Electrical Machi ner y & C ontrol Lab电路与系统实验室Circuitry & Sy stem LabIC设计实验室IC Design LabESDA 与嵌入式技术实验室ESDA & Embedded Technolog y Lab微机原理实验室Microcomputer Principle Lab电力系统继电保护实验室Power Sy s tem Relay Protection Lab供配电技术实验室Power Supply Lab电力系统仿真实验室Power Sy s tem Emul ation Lab基础化学实验室Basic Chemistr y Lab无机化学分室Inorganic Chemistry Lab有机化学分室Organic Chemistry Lab基础分析化学分室Basic Analytical Chemistr y Lab物理化学分室Phy sical Chemistr y Lab综合仪器实验室Instrumental Lab化工原理实验室Chemic al Engineering Principle Lab化学工程与工艺实验室Chemic al Engineering & Tec hnology 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tem Lab数字电视实验室Digital TV Lab微机测控技术实验室Microcomputer Measurement & Control Tec hnology Lab单片微机与嵌入式系统实验室Single Chip-Microcomputer & Embedded Sy stem Lab 动态测试与控制实验室Dy namic Test & Control Lab传感器与检测技术实验室Sens or & Measurement Technolog y Lab精密仪器与光电工程实验室Precise Instrument & Optoel ectronic Engineering Lab信息技术基础实验室IT Foundation Lab高频技术实验室High Frequenc y Tec hnol ogy Lab道路与桥梁工程实验室Highway & Bridge Engineering Lab给水排水工程实验室Water Suppl y & Was te Water Lab土木工程材料实验室Civ il Engineering Materials Lab唯雅诺自动化网建筑设备工程实验室Building Equipment Lab建筑学实验室Architectural Lab交通运输工程实验室Communic ation & Trans portation Lab结构工程实验室Structural Engineering Lab控制测量实验室Control Sur v ey Lab力学实验室Mechanics Lab流体力学实验室Hy drody namics Lab"S"技术实验室S Technolog y Lab岩土工程实验室Geotechnical Engineering Lab城市规划实验室Urban Pl anning Lab工程管理模拟实验室Engineering Management Si mulating Lab电子商务专业实验室Electronic C ommerc e Lab企业管理实验室Enter prise Management Lab地理信息系统实验室Geographic Information Sy stem Lab信息系统基础实验室Infor mati on Sy stems Lab会计手工模拟实验室Hand Acc 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Lab材料成型及控制实验室Material Proc essing & Control Lab模具技术实验室Die & Moul d Tec hnology Lab功能材料的制备与应用技术实验室非晶态材料分室Amor phous Materials Lab表面工程分室Surfac e Engineering Lab热型连铸分室Heated Mold Continuous C asting Lab储能材料分室Energy Storage M aterials Lab先进材料结构与性能分室Adv anced Materials Structure & Properties Lab 环境工程实验室Env ironmental Engineering Lab水污染控制工程分室Water Polluti on Control Lab大气污染控制工程分室Air Pollution Control Lab固体废物处理工程分室Solid Waste Treatment Lab噪声污染控制工程分室Noise Pollution Control Lab环境监测分室Env ironment Monitoring Lab环境科学实验室Env ironmental Scienc e Lab环境信息分室Env ironmental Information Sy stem Lab环境化学分室Env ironmental C hemistry Lab环境生物实验室Env ironmental Biolog y Lab大型精密仪器室Exactitude Apparatuses Room信息与计算科学实验室Infor mati on & Computati on Scienc e Lab光电技术实验室Optoelectronic Tec hnology Lab光信息技术实验室Technolog y of Optical Information Lab微电子技术实验室Microelectronic Tec hnology Lab电子技术综合实验室Electronic Technolog y Lab工业设计实验室Industrial Design Lab服装设计与工程实验室Apparel Design Lab基础造型实验室Fundamental Design Lab摄影分室Photography Lab陶艺设计与制作分室Pottery Design & F acture Lab环境艺术设计实验室Env ironment Design Lab视觉传达设计实验室Visual Communic ation Design Lab家具设计实验室Furniture D ecorati on Lab模拟法庭Mock Trial Room数码钢琴室Digital Piano Room社会工作实验室Social Wor k Lab工程训练实验教学示范中心Engineering Training Demons tration Center 铸造实习室Casting铣刨磨实习室Milling/ Planer/Grinder数控加工实习室CNC Machining数控编程实习室Programmi ng普通车床实习室Turning Lathe焊接实习室Welding钳工实习室Benc h Work热处理/金相分析实习室Heat Treatment & Microstructure压力加工实习室Forging测量实习室Measurement唯雅诺自动化网大学物理基础实验室College Phy sics F oundation Lab大学物理综合实验室College Phy sics Sy nthesized Lab电工电子实验中心Electrical & Electronic Ex perimental C enter电工基础实验室Electronic F oundation Lab电子技术实验室Electrical Technol ogy Lab电工与电子技术实训室Electrical & Electronic Training计算机基础实验中心Computer Ex perimental Center计算机基础实验室Computer Foundation Lab计算机组装实验室Computer Assembling Lab计算机组网实验室Computer Networ k Lab实验仪器名称中英文对照表仪器中文名称仪器英文名称英文缩写原子发射光谱仪Atomic Emission Spectrometer AES电感偶合等离子体发射光谱仪Inducti v e C oupl ed Plas ma Emission Spectrometer ICP直流等离子体发射光谱仪 Direct Current Pl asma Emission Spec trometer DCP紫外-可见光分光光度计 UV-Visible Spec trophotometer UV-Vis微波等离子体光谱仪 Microwave Induc tive Pl asma Emission Spectrometer MIP原子吸收光谱仪Atomic Absorption Spec troscopy AAS原子荧光光谱仪Atomic Fluoresc enc e Spectroscopy AF S傅里叶变换红外光谱仪FT-IR Spectrometer FTIR傅里叶变换拉曼光谱仪FT-Raman Spectrometer FTIR-Raman气相色谱仪 Gas Chromatograph GC高压/效液相色谱仪High Pressure/Performance Liquid Chr omatography HPLC离子色谱仪 Ion Chromatograph凝胶渗透色谱仪Gel Per meation Chromatograph GPC体积排阻色谱 Size Ex cl usion Chromatograph SECX射线荧光光谱仪 X-Ray Fluoresc enc e Spectrometer XRFX射线衍射仪X-Ray Diffractomer XRD同位素X荧光光谱仪Isotope X-Ray Fluoresc enc e Spectrometer电子能谱仪 Elec tron Energy Disperse Spectroscopy能谱仪 Energ y Disperse Spec troscopy ED S质谱仪 Mass Spec trometer MSICP-质谱联用仪ICP-MS IC P-MS 气相色谱-质谱联用仪 GC-MS GC-MS 液相色谱-质谱联用仪 LC-MS LC-MS 核磁共振波谱仪Nuclear Magnetic R esonanc e Spectrometer NMR电子顺磁共振波谱仪 Electron Paramagnetic Resonance Spectrometer ESR极谱仪 Polarograph伏安仪 Voltammerter自动滴定仪 Automatic Titrator电导仪 Conducti v ity MeterpH计 pH Meter水质分析仪 Water Tes t Kits电子显微镜 Elec tro Microscopy光学显微镜 Optical Microscopy金相显微镜 Metallurgical Microscopy扫描探针显微镜Sc anning Probe Microscopy表面分析仪 Surface Anal y z er无损检测仪 Ins trument for N ondestructi ve Testi ng物性分析Phy sical Property Anal y sis热分析仪Thermal Anal y zer粘度计 Visc ometer流变仪 Rheometer粒度分析仪 Particle Size Anal y zer热物理性能测定仪 Ther mal Phy sical Property Tester电性能测定仪 Electrical Property Tester光学性能测定仪Optical Property Tester机械性能测定仪Mechanic al Property Tes ter燃烧性能测定仪Combustion Property Tester老化性能测定仪Aging Property Tes ter生物技术分析 Biochemic al anal y sisPCR仪Instrument for Pol ymeras e Chain R eaction PCR DNA及蛋白质的测序和合成仪 Sequencers and Synthesizers for DNA and Protein传感器 Sens ors其他 Other/Miscellaneous流动分析与过程分析 Fl ow Anal y tic al and Pr ocess Anal y tical C hemistry气体分析Gas Anal y sis基本物理量测定Basic Phy sics样品处理Sample Handling金属/材料元素分析仪 Metal/material el emental anal y sis环境成分分析仪CHN Anal y sis发酵罐 F ermenter生物反应器 Bio-reactor摇床 Shak er离心机 Centrifuge超声破碎仪 Ultrasonic Cell Disruptor超低温冰箱 Ultra-low Temper ature Freezer恒温循环泵 Cons tant Temperature Circulator超滤器 Ultrahigh Purity Filter冻干机 Freeze Dr y ing Equipment部分收集器 Fraction Collector氨基酸测序仪 Protei n Sequenc er氨基酸组成分析仪 Ami no Acid Anal y z er多肽合成仪 Peptide s ynthesizerDNA测序仪 DNA SequencersDNA合成仪 DNA synthesizer紫外观察灯 Ultrav iolet Lamp唯雅诺自动化网化学发光仪 Chemiluminesc enc e Apparatus紫外检测仪 Ultrav iolet Detec tor电泳 Electr ophoresis酶标仪 ELIASACO2培养箱 CO2 Incubators倒置显微镜 Inverted Microscope超净工作台 Bechtop流式细胞仪 Flow C y tometer微生物自动分析系统 Automatic Analy z er for Microbes生化分析仪 Bioc hemical Anal y zer血气分析仪 Blood-gas Anal y zer电解质分析仪 Electrol y tic Anal y zer尿液分析仪 Urine Anal y zer临床药物浓度仪Anal y zer for Clinic Medicine Conc entration 血球计数器 Hematoc y te Counter实验室家具laborator y/lab fur niture威盛亚wilsonart台面countertop/wor k top实验台laborator y cas ewor k/cabinet中央台island bench边台wall benc h试剂架reagent s helf/rac k天平台balance tabl e仪器台instrument table通风系统v entilati on s y s tem通风柜/橱fume hood/c upboard药品柜medical (storage) c abinet/c upboard器皿柜v ess el cabinet气瓶柜gas cy linder (storage) c abinet实验凳laborator y/lab stool实验椅lab chair配件accessories。

OpenMax IL Bellagio 代码分析 - 台湾清华RTlab实验室 OpenMax IL 代码分析

RTLAB
Free
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到目前為止還OK嗎？

STn8815採用多核分布式架構，並在視頻編碼效率上展現一系列突破，實現了多種創新算法，使智能手機、多功能多媒體設備及播放器、手持網絡電視、便攜導航儀和移動電視能夠播放電視廣播，拍照錄像，以及與其它系統進行實時雙向可視電話通信。在STn8815的軟硬件平台內預裝業內主流的OS和應用框架，有助於手機制造商加快產品上市時間，降低開發移動多媒體消費產品的成本。 STn8815包含一個ARM9核心及四個多媒體加速器，並增加了L2快取記憶體。
omx_base_port_Constructor()

omx_base_constructor()

RTLAB
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Bellagio – IL Core functions omxcore.c

OMX_SetupTunnel()
Establish a
tunnel between two ports of two components. ㄧ定要在StateLoaded執行
RTLAB
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Bellagio work flow
RTLAB
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Bellagio – Video application

Video decoder component

Mpeg4 , H.264 OMX_COLOR_Format24bitRGB888 (default format) OMX_COLOR_Format24bitBGR888 OMX_COLOR_Format32bitBGRA8888 OMX_COLOR_Format32bitARGB8888 OMX_COLOR_Format16bitARGB1555 OMX_COLOR_Format16bitRGB565 OMX_COLOR_Format16bitBGR565 If requested, then play the video directly.

基于区块链的健康链系统设计与实现

收稿日期：2020年6月13日，修回日期：2020年7月26日基金项目：科技部重点研发项目“现代服务可信交易理论与技术研究（面向服务可信交易的新型区块链分布式架构）”（编号：2018YFB1402701）资助。

作者简介：雷志伟，男，工程师，研究方向：区块链、游戏引擎开发。

李加福，男，高级工程师，研究方向：区块链、图像处理。

张桂刚，男，博士，副研究员，研究方向：区块链和人工智能。

赵旭，男，硕士，研究方向：区块链、机器翻译。

张勇，男，博士，副研究员，研究方向：数据管理、云存储、海量信息处理。

邢春晓，男，博士，研究员，研究方向：数据库和数据仓库，大数据和知识工程、人工智能，软件工程，区块链技术，智慧城市、智慧医疗、数字图书馆和电子政务关键技术等。

∗1引言在抗击新冠肺炎疫情初期，各地各部门企业纷纷贡献己力，自主开发疫情防控信息系统。

一方面能加强政府部门的管理，另一方面简化现实中人力物力消耗［1］。

在人员进出公共场所的跟踪管理方面，相应有应用于广西地区的“扫码抗疫情”、云南地区的“云南抗疫情”等。

它们都是基于微信小程基于区块链的健康链系统设计与实现雷志伟1李加福1张桂刚2赵旭3张勇3邢春晓3（1.清华大学行业可信区块链应用技术联合研究中心北京100084）（2.中国科学院自动化研究所北京100190）（3.清华大学信息国家研究中心，计算机系，互联网产业研究院北京100084）摘要新冠疫情在全球范围肆虐，公共场合中的体温测量和行踪登记是控制疫情蔓延的关键手段，目前的信息记录主要依赖人工纸张录入的方式。

纸张录入的方式不仅效率低下，而且还面临着易损易丢失的存档风险，同时难以对过往人员与行踪进行快速筛查。

该系统基于微信小程序的开发框架，实现了扫码快速注册以及信息登记的功能，同时基于区块链技术来实现底层数据存储和优化，保证数据的不可篡改和快速溯源，最后通过Nginx 服务器进行数据通信。

关键词比特币；区块链；微信小程序；健康链；Nginx中图分类号TP393DOI ：10.3969/j.issn.1672-9722.2020.12.016Design and Implementation of Health Chain System Based onBlockchainLEI Zhiwei 1LI Jiafu 1ZHANG Guigang 2ZHAO Xu 3ZHANG Yong 3XING Chunxiao 3（1.Joint Research Center for Industry Trust Blockchain Application Technology ，Tsinghua University ，Beijing100084）（2.Institute of Automation ，Chinese Academy of Sciences ，Beijing100190）（3.Institute of Internet Industry ，Department of Computer Science and Technology ，Beijing National Research Center forInformation Science and Technology （BNRist ），Tsinghua University ，Beijing100084）AbstractDuring the COVID-19，temperature measurement and whereabouts registration in public are the key to control thespread of the virus.Current information recording mainly relies on manual paper entry which is not only inefficient ，but also fragileand easy to lose ，and it is difficult to retrieve the past data.This system is based on the Wechat Mini Program ，the information re⁃cording is implemented easily by scanning QR codes to improve efficiency.Moreover ，managing the storage and optimization of the underlying data based on blockchain technology ensure the data security and fast traceability.Finally ，the data communication is performed through the Nginx server.Key Words Bitcoin ，blockchain ，Wechat mini program ，health chain ，NginxClass NumberTP3932020年第12期计算机与数字工程序开发，其功能和使用方式大抵相同，群众以个人身份注册，另一个则是公共场所的工作人员以公共场所的身份进入系统并生成二维码进行张贴，进出人员手动扫码实现数据上传，从而减免了手工登记流程。

openlab操作规程

OpenLab操作规程1. 引言本文档旨在规范OpenLab的操作流程，确保操作过程的规范化和高效性。

OpenLab是一个开放式实验室，为研究人员和学生提供一个共享资源的平台。

为了保障实验室的良好运行和实验室成员的安全，制定本操作规程。

2. 实验室入场和离场流程2.1 入场流程1.实验室成员到达实验室前应仔细阅读实验室规则，并确保已完成所有必要的培训和考核。

2.刷卡进入实验室。

每个实验室成员都需使用个人专属的门禁卡进行刷卡，以记录入场时间和身份验证。

3.检查个人物品。

进入实验室后，实验室成员需要将衣物、背包等个人物品存放在指定的存放区域。

禁止将任何个人物品放置在实验台上，以确保实验台干净整洁、安全有序。

4.穿戴个人防护装备。

根据实验的性质和要求，如需穿戴实验服、手套、安全鞋等个人防护装备，务必佩戴到位。

2.2 离场流程1.装备归还。

使用完实验室提供的设备或工具后，需要妥善归还到指定的位置。

2.清理实验台。

离开实验室之前，需要将实验台上的实验器材、试剂等归位，并保持实验台的整洁。

3.离场刷卡。

在离开实验室时，实验室成员需要再次使用个人门禁卡进行刷卡，以记录离场时间。

3. 设备使用规定3.1 设备预约1.预约流程。

在需要使用实验室设备时，成员需要提前向相关责任人提出预约申请，并在预约时间之前进行确认。

2.预约取消。

如需取消已预约的设备使用时间，应提前通知相关责任人并取消预约。

3.2 设备操作指南1.设备操作前的准备工作。

在操作设备前，应认真阅读设备操作手册和安全指南，并确保已理解设备的工作原理和操作流程。

2.设备操作流程。

按照设备操作手册的指导进行操作，严禁擅自调整设备参数和操作方法。

3.设备故障处理。

如遇设备故障或异常情况，应立即停止操作，并及时向责任人报告。

4. 安全操作规定4.1 实验室安全教育1.新成员培训。

新加入实验室的成员需要接受实验室安全教育培训，并通过考核后方可参与实验室的操作。

2.定期安全培训。

Microchip Technology PIC32微控制器的MPLAB Harmony开发平台说明

2017 Microchip Technology Inc.page 1STANDARD FEATURES•MPLAB ® Harmony is a flexible, abstracted, fully integrated firmware development platform for PIC32 microcontrollers •Broad range of Middleware Stack/Libraries, including: USB, TCP/IP , Wi-Fi™, File System, Graphics, Bootloaders, Bluetooth™, Audio, DSP , Math, Cryptography, Drivers, System Services, and more•Over 160 Application Demonstrations with up to 600 application configurations to accelerate application development•Seamlessly integrates third-party solutions (RTOS, Middleware, Drivers, etc.) into the software framework•RTOS support, which includes: FreeRTOS™, OPENRTOS, Express Logic Thread X, SEGGER embOS ®, Micriµm ® µC/OS-II™, Micriµm µC/OS-III™•Middleware support, which includes: SEGGER emWin ®, InterNiche Technologies, Inc., wolfSSL, and PubNub ®•Both free and enabling license terms providedFor a detailed list of features, please visit the MPLAB Harmony Web page at:/harmonyFrom the landing page, scroll down and select the Features tab.DESCRIPTIONMPLAB Harmony is a flexible, abstracted, fully integrated firmware development platform for PIC32 microcontrollers.MPLAB Harmony's modular architecture allows drivers and libraries to work together with minimal effort. It is scalable across PIC32 Microchip devices to custom fit customers’requirements.MPLAB Harmony takes key elements of modular and object oriented design, adding an Operating System Abstraction Layer (OSAL) that provides the flexibility to use a Real-Time Operating System (RTOS) or work without one, and provides a framework of software modules that are easy to use, con-figurable for your specific needs, and that work together in complete harmony.In addition, the MPLAB Harmony Configurator (MHC) and code development format allows for maximum reuse and reduces time to market.COMPLIANCECompliant with MISRA-C:2012 Mandatory Standards:•MPLAB Harmony Peripheral Libraries •TCP/IP LibraryDEVELOPMENT TOOLS•MPLAB X IDE v4.20 is required•MPLAB XC32 C/C++ Compiler v2.10 (ISO 26262) •MPLAB X IDE plug-ins:-MPLAB Harmony Configurator (MHC) v2.0.6.0THIRD-PARTY DEVELOPERSMicrochip offers a range of documentation to assist you with the design of your own software offerings for MPLAB®Harmony. These documents, which are provided with the installation Help, are also available for download from the MPLAB Harmony website (see “Download Information” for details). •MPLAB Harmony Overview•MPLAB Harmony Compatibility Guide•MPLAB Harmony Creating Your First Project Tutorial •MPLAB Harmony Driver Development Guide •MPLAB Harmony Configurator User's Guide•MPLAB Harmony Graphics Composer User's Guide •MPLAB Harmony Test Harness User's GuideS o f t w a r e F r a m e w o r kIntegrated Software Framework v2.06MPLAB HARMONY v2.06page 2 2017 Microchip Technology Inc.v2.06 FEATURE UPDATES AND ADDITIONSMPLAB Graphics Composer:•Added string table import / export •Added scheme import / export •Added DDR memory manager•Improved accuracy of heap estimator •Added new widgets to toolboxAria Graphics User Interface Library:•Added arc drawing primitive •Added circular gauge widget •Added circular slider widget •Added bar graph widget •Added line graph widget •Added pie chart widget •Added image plus widget •Added radial menu widget •Improved list wheel widget •Improved keypad widget•Added multi-line text support to widgets •Improved RTOS integration (PIC32MZ DA)•Improved GPU driver performance (PIC32MZ DA)Touch Functionality:•Added multi-finger gesture support•Added Input system service (performance enhancement)•Deprecated touch system service•Added resistive touch to input system service •Added resistive touch calibration exampleNew Applications:•Aria Adventure graphic (parallax animation)•Aria Image Viewer graphics (2-finger pinch gesture/zoom)•Aria Showcase Reloaded (new widget examples)•Aria Radial Menu (radial menu views)•Aria Touch ADC Calibrate•Real-time FFT (audio inputs, FFT DSP , display)•Smart speaker (echo cancellation example)•Data voice control (Bluetooth SPP to Google voice cloud recognition)•Example for third party display port (external control / third party touch)•Resistive touch calibration•Added Speex encoder to universal audio encoders Audio:•Added examples for Google voice•Added example for acoustic echo cancellation •Updated AK4954 audio codec driver•Updates PIC32MZ DSP fractional math library •Added Speex encoder APIMPLAB Harmony TCP/IP Stack:•TFTP server support added to the stack •Added ICMP support for broadcast pings•Added two new FTP commands - DELETE and NOOP •Added announce console command•Added heap high watermark functionality•The mail SMTPC module has been added to the standard demonstrations. The old SMTP module has been marked as deprecated.New Tutorial:•Creating a MPLAB Harmony Graphics Application Using a Third-Party Display.New Example:•Graphics Event Testbed (./apps/examples/events_testbed)•Remote Device Symmetric Key Authentication with secure element ATECC608A. (./apps/crypto/ecc_symmetric)•Remote Device Asymmetric Key Authentication with secure element ATECC608A. (./apps/crypto/ecc_asymmetric)DOWNLOAD INFORMATIONMPLAB Harmony, including the current release notes and Software License Agreement, is available for download by visiting:/mplabharmonyADDITIONAL RESOURCESMPLAB Harmony TV offers a wide range of getting started and training videos. The video content is available by scrolling to the bottom of the MPLAB Harmony webpage at:/mplabharmonyThe Microchip Developer Site provides short introductory videos, self-paced training modules, and answers to frequently asked questions./harmony:startNote the following details of the code protection feature on Microchip devices:•Microchip products meet the specification contained in their particular Microchip Data Sheet.•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.•Microchip is willing to work with the customer who is concerned about the integrity of their code.•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.。

LookOut Mycoplasma PCR Detection Kit 产品说明书

User GuideLookOut®One-Step Mycoplasma PCR Detection Kit MP0050-25TST (25 reactions)MP0050-100TST (100 reactions)Storage Temperature 2–8 °CProduct DescriptionThe LookOut® Mycoplasma PCR Detection Kit utilizes the polymerase chain reaction (PCR), which was established as the method of choice for highest sensitivity in the detection of Mycoplasma and Acholeplasma contamination in cell cultures and other culture-derived biologicals. Detection requires as little as 10-20 fg of mycoplasma DNA corresponding to10-20 mycoplasma per sample volume.The primer set is specific to the highly conserved rRNA operon, or the 16S rRNA coding region in the mycoplasma genome. This allows for detection of all Mycoplasma, Acholeplasma, and Ureaplasma species tested so far, which are typically encountered as contaminants in cell cultures.Eukaryotic and bacterial DNA are not amplifiedby this kit.Just one protocol is needed for the detection of all mycoplasma species. The detection procedure can be performed within 3 hours. The PCR mix also provides internal control DNA, which results in a 190 bp band on the agarose gel to indicate a successfully performed reaction.Precautions and DisclaimerThis product is for R&D use only, not for drug, household, or other uses. It is not for clinical diagnostics or testing of human samples. Please consult the Material Safety Data Sheet for information regarding hazards and safe handling practices. ComponentsDescription QuantityCatalogueNumberPCR Mix, aliquotedfor 25 reactions:1 vial MP0050-25TST4 vials MP0050-100TST Lyophilized Taq polymerase, primers and deoxynucleotide triphosphates dATP,dCTP, dGTP and dUTPReaction Buffer,1.3 mL1 vial MP0050-25TST2 vials MP0050-100TST Positive Control DNA 1 vialLyophilized syntheticDNA, non-infectiousWater, 2 mL 1 vialStorage/StabilityKit components are stable during shipping at ambient temperature. Upon receipt, store at 2-8 °C. After rehydration of the PCR mix, the positive control, and the internal control, store below –18 °C and avoid repeated freezing and thawing. For repeated testing of a few samples at a time, PCR mix and controls should be aliquoted after rehydration. By following these recommendations, the kit is stable until the expiration date stated on the label.Rehydration Buffer PCRMixWater PositiveControl DNAQuick Start GuideThis procedure overview is not a substitute for the detailed instructions.Reagent PreparationCentrifuge PCR Mix and Positive Control DNAPreparationof PCR ReactionsLoad the test tubes Aliquot 23 µL PCR MixCentrifuge brieflyStart PCR Reaction1 cycle 94 °C for2 min 39 cycles 94 °C for 30 sec 55 °C for 30 sec 72 °C for 30 sec Hold at 4-8 °CIncubate for 5 min at room temperatureVortex brieflyCentrifuge for 5 seconds600 µL300 µLAdd 2 µL Sample Add 2 µL Sample Add 2 µL Positive Control DNA Add 2 µL Fresh CellCultureMediumProcedurePreparation of Sample MaterialCell lines should be pre-cultured in the absence of antibiotics for several days to maximize test sensitivity. Samples should be derived from cultures that are at 90–100% confluence. PCR-inhibiting substances may accumulate in the medium of older cultures. For these sample materials a DNA extraction is strictly recommended prior to testing.To avoid false positive results, it is recommended to use deionized, DNA-free water, aerosol-preventive filter pipette tips, and gloves.Templates for PCR analysis are prepared by boiling the supernatant of cell cultures or other biologicals for 10 minutes as follows:1.Transfer 100 µL of supernatant from the test culture to asterile microcentrifuge tube (T0447). The lid should be tightly sealed to prevent opening during heating.2.Heat the sample supernatant at 95 °C for10 minutes.3.Briefly centrifuge (5 seconds) the sample supernatant to pelletcellular debris before adding to the PCR mixture. Rehydration of the Reagents1.Before rehydrating the tubes, centrifuge the tubes to ensurethat the lyophilized components are spun down (5 seconds at maximum speed).2.Add the appropriate amount of Rehydration/Reaction Buffer(blue cap)PCR Mix, 300 µL per portion of 25 reactions 3.Add the appropriate amount of Water (white cap) to PositiveControl DNA, 600 µL4.Incubate for 5 minutes at room temperature.5.Vortex and centrifuge again.6.Keep reagents on ice and store below -18 °Cafter rehydration. Thermal ProfileThe programming process of your cycler is explained in the instrument’s manual.Thermal Cycle Program1 cycle 94 °C for2 minutes39 cycles 94 °C for 30 seconds55 °C for 30 seconds72 °C for 30 secondscool down to 4–8 °CThe PCR MastermixTotal volume per reaction is 25 µL. When setting up reactions, calculations should also include positive and negative controls.1.The rehydrated PCR Mix can be prepared for25 reactions, aliquoted as needed, and stored b elow –18 °C forup to 3 months. Aliquot 23 µLof the rehydrated PCR Mix into each PCRreaction tube.2.Add 2 µL of deionized, DNA-free water as a negative controlinto negative control reaction tubes and seal t o avoidcontamination.3.Add 2 µL of sample (as previously described)to PCR reaction tube per sample being testedand seal.4.Pipette 2 µL of positive control DNA into positive controlreaction tube.5.Proceed to thermal cyclingAgarose Gel Rune 1.5% standard agarose gel (A9539)with 5 mm comb.2.Load 5 µL of each PCR reaction, mixed with gel trackingloading solution (G7654) per lane.3.Stop electrophoresis after 2 cm run distance (depending onthe electrophoresis chamber used e.g., run for 25 minutes at100 V).ResultsGel Evaluation1. A distinct 190 bp band should appear in every lane indicating asuccessfully performed PCR. This band may fade out with increased amounts of amplicons formed, caused by mycoplasma DNA loads of 5 × 106 copies/ml. 2. No amplification of positive control DNA maybe due to the following reasons:• positive control DNA tube has not been spun down before rehydration • programming mistake •pipetting mistake.3. Before rerun of a negative and a positivecontrol, please check thermocycler protocol and pipetting scheme.4. Nonspecific bands on the gel are extremely rare. Possibleprimer self-annealing produces another (primer dimer) band of 80-90 bp but does not affect the precision or results of the test. 5. If the PCR of a sample is inhibited, PCR inhibitors can easily beremoved from the sample by performing a DNA extraction with a commercially available kit (G1N10, G1N70, or NA2000).Sample Data← 270 bp positive control ← 190 bp internal controlR a i n b o w l a d d e rN e g a t i v e c o n t r o lP o s i t i v e c o n t r o lC o m p l e t e l y i n h i b i t e dI n h i b i t e dT y p i c a l c o n t a m i n a t i o nS t r o n g c o n t a m i n a t i o nR a i n b o w l a d d e rRelevant amplicon sizesInternal control 190 bpMycoplasma sp.(see Detectable Species)∼270 bpResults of successfully performed PCRPCR sample Band pattern Negative control Band at 190 bpPositive control Band at 267 bp,possibly an additionalband at 190 bp Interpretation of possible band patterns Band pattern InterpretationBand at 190 bp Negative sample Bands at 270 bpand 190 bpMycoplasma-positivesample with weakcontaminationStrong band at 270 bp Mycoplasma-positivesample with strongcontaminationNo band PCR inhibitionDetectable SpeciesA large number of Mollicutes sequences have been published. The primers of the kit were aligned againstthe NCBI data and scrutinized for homologies within the target region of the 16S rRNA. At least 1 Ureaplasma, 7 Acholeplasma and 85 Mycoplasma show highly relevant sequence homologies and are presumably detected as positive.Positive (Mollicutes)NegativeEP 2.6.7 listed bacteria Other microorganisms MammalsAcholeplasma laidlawii Clostridium acetobutylicum Chlamydia trachomatis Vero-B4 Mycoplasma arginini Lactobacillus acidophilus Legionella pneumophila Per.C6 Mycoplasma arthritidis Streptococcus pneumoniae Micrococcus luteus RK13 Mycoplasma fermentans Candida albicans CHO-K1 Mycoplasma gallisepticum Enterococcus faecalis Murine genomic DNA Mycoplasma genitalium Enterobacter aerogenes Calf thymus DNA Mycoplasma hominis Escherichia coli Proteus Fetal bovine serum Mycoplasma hyorhinis Proteus mirabilisMycoplasma orale Bacillus cereusMycoplasma penetransMycoplasma pneumoniaeMycoplasma salivariumMycoplasma synoviaeSpiroplasma citriUreaplasma urealyticumThe life science business of Merck operates as MilliporeSigma in the U.S. and Canada.Merck LookOut and Sigma-Aldrich are trademarks of Merck KGaA, Darmstadt, Germany or its affiliates. All other trademarks are the property of their respective owners. Detailed information on trademarks is available via publicly accessible resources.NoticeWe provide information and advice to our customers on application technologies and regulatory matters to the best of our knowledge and ability, but without obligation or liability. Existing laws and regulations are to be observed in all cases by our customers. This also applies in respect to any rights of third parties. Our information and advice do not relieve our customers of their own responsibility for checking the suitability of our products for the envisaged purpose.The information in this document is subject to change without notice and should not be construed as a commitment by the manufacturing or selling entity, or an affiliate. We assume no responsibility for any errors that may appear in this document.Technical AssistanceVisit the tech service page at /techservice .Terms and Conditions of SaleWarranty, use restrictions, and other conditions of sale may be found at /terms .Contact InformationFor the location of the office nearest you, go to /offices .。

MyLab辅助功能最佳实践指南说明书

MyLab Accessibility Best Practices GuideStriving to ensure every learner succeeds MyLab course materials Alternative course materials Accessible eTextbooks Alternate format text AccessText Network Braille and large print MyLab accessibility features Turning on Accessibility Platform and navigation Assignments and assessments Question bank for homework and tests Custom Question Builder Microsoft PowerPoint decks Alternate text Videos Discipline-specific media In your MyLab course: New considerations Support and documentation VPATs and other accessibility status documents Table of Contents112222344456789910101010Introduction/OverviewStriving to ensure every learner succeedsMyLab course materialsEmpowering learners will always be central to Pearson’s mission and values. That includes designing instructional content for MyLab® to be fully accessible to students with disabilities while continually improving usability.By honoring the following best practices together, we can enable a wider array of students to thrive through their learning journey — and prepare everyone to prosper.Pearson’s investment in accessible product design and remediation is significant and ongoing as we strive to meet and exceed Web Content Accessibility Guidelines (WCAG 2.1 AA standards) for all our educational materials including those designed for MyLab courses.If for any reason any Pearson eTextbook doesn’t meet a student’s need, Pearson is prepared to provide other course material options. To save everyone time and effort, we’ve partnered with top providers and accessibility experts to expand our capabilities.Alternative course materialsAccessible eTextbooksPearson’s newest eTextbook platform, Pearson+, supports the majority of WCAG 2.1 AA standards and we are continuously updating to improve both accessibility and usability as well as compatibility with assistive technologies. Keep in mind that the most recent edition of each title will provide the most accessible user experience.Pearson+ eTextbooks can be accessed in two ways:1. Using a MyLab courseIf your course uses Pearson MyLab online learning platforms, students may already have access to an accessible eTextbook. To open, go to the MyLab course menu in your browser and select the eTextbook option.2. Logging in to Pearson+ directlyFor classes that do not use MyLab, students can log in to Pearson+ to access eTextbooks from a computer or mobile device (iOS and Android), even when offline.Please email us at ****************************** for title-specific details or if you encounter any issues.Alternate format textIf a Pearson+ eTextbook is not fully accessible for a student based on their needs, an alternate format text can be found within the Pearson VitalSource accessible digital textbooks library.You may purchase Pearson titles as eTextbooks from VitalSource and get instant access to eTextbooks through the VitalSource Bookshelf platform.Learn more about accessible digital eTextbooks from Pearson and get answers to common questions about them.AccessText NetworkPearson partners with the AccessText Network to ensure that students with print-based disabilities that would be better addressed by a non-digital textbook also have that option. Upon request and at no added cost, additional Pearson titles are available for qualified students who buy or rent our print or eTextbook versions through AccessText Network, a clearinghouse for files from all major higher education publishers.A disability services representative must make these title requests from the school who must register with the AccessText Network. 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Order textbooks in braille or reflowed large print by emailing Allyant at: **************** or calling: 1-800-563-0668.Platform and navigationAll MyLab website pages are screen reader and keyboard-accessible including student pages like Calendar, Homework and Tests, Results, Announcements, and Study Plan.The platform’s interface works with common screen magnifiers. Browser- or device-based contrast settings are respected.*Note: When the student is using keyboard-only navigation or assistive technology within MyLab, the Accessibility Mode is required to complete assignments. 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RTLAB使用说明书

RTLAB使用说明书一、硬件连接本系统有如下设备：1.OP5600，仿真主机，内含CPU及ML605（FPGA板卡）、数字量&模拟量I/O板卡；2.OP7000，可扩展的FPGA仿真单元，本系统中内嵌两块FPGA板卡（OP7161）；3.开发主机（笔记本&台式机）连接框图如下：PC机TCP/IP(以太网线系统开关机说明：1.开机：先开OP7000，启动后再开OP5600（注：OP5600有两个开关，先开电源开关，再开POWER启动）。

2.关机：点击RT-LAB界面的RESET与OP5600断开，再关OP5600（先长按关POWER健，再按电源），再关OP7000。

二、软件安装1.PC机要求：XP或者32位WIN7（暂不支持Vista与WIN7 64位系统）2.安装流程：MATLAB ------->RTLAB(包括ARTEMIS等)-------> Xilinx ISE Design Suite以下软件安装目录不可出现中文，另：PS-CAD可能会与MATLAB冲突，请注意此问题。

1). MATLAB可为RTLAB所支持的所有版本，推荐09b以上版本（注：MATLAB安装时Simulink模块不可删减）2). RTLAB 安装：a．打开光盘1，找到Setup.exe,采用默认设置Next一直到如下界面，选择Development,这个界面中，除了RT-LAB10.4.4.130与ARTEMIS不选外，其他的都选上。

这两个软件需要安装更新版本，稍后安装。

下一步后，出现如下界面,默认Node Locked选项，Next—>接下来就依次安装每个模块了，每安装完一个模块，提示重启，取消即可。

等所有的模块装完（包括接下来的RTLAB 10.4.8和ARTEMIS 6.2.2装完）。

b. 打开光盘2，正常安装RTLAB 10.4.8和ARTEMIS 6.2.2两个模块。

至此，RT-LAB等库已经安装完毕。

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7HFKQRORJ\ PDSSLQJ XVLQJ 6,6Laboratory 2in course “Logic synthesis”2002-versionWritten by Tomas Bengtsson and Shashi KumarÃÃ,QWURGXFWLRQ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB'RFXPHQWV QHHGHG IRU WKLV ODEBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB6KRUW LQWURGXFWLRQ WR )3*$V BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7DVNV BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHU BBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUN BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB$Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB'HVFULSWLRQ RI H[DPSOH BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB6RPH WLSVBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7KH H[DPSOH WKURXJK 6,6BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBDecomposition_____________________________________________97.3.1. Gate7.3.2. LUTMapping_________________________________________________11commands_______________________________________127.3.3. Post-processing7.3.4. Programmable Logic Block Generation_____________________________14ÃÃ,QWURGXFWLRQAfter a circuit has been optimized using Logic Optimization tools, the next step is to bring the circuit closer to implementation by using the available information about implementation technology. This step is called Technology Mapping. This step involves converting the abstract description (FSM or Boolean functions) of the circuit to a network of limited type of components, normally from a library of components. Due to this reason, Technology Mapping is also sometimes referred as Library Binding. This step involves, selecting components from the library and forming a network of these components. Normally the objectives in Technology Mapping are to have the final implementation using a minimum number of components or to minimize the area of the implementation.Technology mapping to an FPGA results in the final implementation suitable for a specific FPGA type from a specific company. This is because the internal architecture of FPGAs from different companies is quite different. The internal architectures of various FPGAs from the same company also differ depending on the component series. For example, XILINX 4000 series FPGA has different type of logic blocks as compared to 3000 series. There are two further steps after a circuit has been converted to a network of blocks of a FPGA. These steps are called 3ODFHPHQW and 5RXWLQJ. In the placement step, the logic blocks in the network are assigned specific physical blocks within the FPGA. In the routing step, the used logic blocks are connected using programmable interconnection resources.In this laboratory, we are only concerned with the first step, which is converting the abstract design to a network of logic blocks for Xilinx FPGA family.'RFXPHQWV QHHGHG IRU WKLV ODEAmong the documents from the first lab you will need the document from UCLA (University of California Los Angeles), which describes the extension of SIS for technology mapping. In this document we recommend you to skip the first part and start reading the part starting with a header “Commands provided by UCLA FPGA Mapping Package”. This documents can be found in Appendix A of this lab manual.A “hand-in” form that you have to fill in to pass the lab is also given. That hand in form and this lab manual can be found in Pingpong.5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODETo be able to use the lab time more efficient we recommend you to study the document from UCLA the part mentioned in section 2 “Documents needed for this lab”. It is also recommended that you complete the task described in section 6.1 “Task 1 Making scripts for technology mapping” before the lab.ÃÃ6KRUW LQWURGXFWLRQ WR )3*$VFPGAs are one family of programmable logic circuits. An FPGA contains programmable logic blocks and programmable interconnection between the blocks. The programmable blocks are called CLBs (Complex Logic Block). The CLBs contain one or more LUTs (Look Up Table). A LUT is a combinatory device with some inputs and one output. It can be programmed to realize any Boolean function. The CLB can be programmed so the output of the LUTs goes to the output of the CLB direct or via a flip-flop. This can be done individually for every LUT. The inputs to the CLB are connected to the inputs in the LUTs. If the CLB contains more than one LUT, some inputs to the CLB may be connected to inputs in more than one LUT.To connect outputs and inputs of CLBs to other CLBs and to the ports of a chip the programmable interconnection part is used. In this lab we are not going to deal with this. We are only going to map logic into fit CLBs. We will use some old FPGAs, Xilinx3000 – series and Xilinx4000 – series. For our purpose we don’t gain anything by using newer ones. The CLBs in both series has two LUTs. The LUTs in Xilinx3000 – series has four inputs and in Xilinx4000 – series they have five inputs.The picture below shows an example of a simple CLB. The CLBs we will use in this lab looks a little different.,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODEAs written in the previous section the LUTs in Xilinx 3000-series have four inputs each and in Xilinx 4000-series the LUTs have five inputs each. The parameter “-k” used in many technology-mapping commands should specify number of inputs to one LUT.ÃÃ7DVNV7DVN 0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJIn this task you should prepare scripts for technology mapping. Make one script containing technology-mapping commands, which makes optimization with respect to area minimization for mapping to Xilinx 3000-series. Make another script doing the same but for minimizing the depth of the circuit. Copy those scripts and modify the copies to work for Xilinx 4000-series. You don’t need to put the final commands “match_3k” and “match_4k” into the scripts. You can write those commands in the SIS-prompt when you need them instead.Fill in the scripts in the “hand-in” form.7DVN 7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUIn this task you should use your multiplier from the previous lab and make technology mapping in some different ways. In this lab you should alter the following parameters:• You can either use technology-independent optimization before you make technology mapping or you can skip technology-independent optimization. When you are making technology-independent optimization in this task you should use “rugged-script”• You can optimize for area or for depth. To do this you should use your scripts from the previous task.• You can technology-map for either Xilinx 3000-series or Xilinx 4000-series.The alternatives enumerated above makes eight different combinations of optimizations. Make those and fill in the required results in the “hand-in” form. There are also some questions in the “hand-in” form you should answer.7DVN 7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHUIn this task you should use the “Gray-code to binary converter” you have made in the previous lab. The task is to technology-map it so it fits into two CLBs in Xilinx 3000-series. Do this and answer the questions in the “hand-in” form!7DVN 7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUNIn this task you should technology-map the benchmark “t481.pla”. You should map it so that it only requires five LUTs in Xilinx 3000-series. This is the goal of this task and you decide what should be done to get there. Answer the questions in the “hand-in”-form!$Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJ'HVFULSWLRQ RI H[DPSOHTo describe an example of technology mapping, an FSM to control one traffic light is used. This traffic-light controller is nothing that can be used in traffic rather it can be used to show a traffic light fitting in a fair. The controller is made as a Moore-machine.ÃÃThe FSM has three inputs. The first input let the traffic-light run in normal mode if it’s “0”, and in a mode with twinkle amber (amber ≈ yellow) if it is “1”. In the normal mode the traffic light is red, green or it is on its way between. If the second input is “1”, when the traffic light is green, it is forced to red via amber. If the third input is “1”, when the traffic light is red, it is forced to green via red_amber.The outputs from the FSM are signals to the three lamps. It is in the order green, amber and red, and “1” means on.The state-diagram below shows the system.ÃÃA description of this in kiss-format is shown below:.start_kiss.i 3.o 300- green green 10001- green amber 1001-- green twinkle_amber 1000-- amber red 0101-- amber twinkle_dark 0100-0 red red 0010-1 red red_amber 0011-- red twinkle_amber 0010-- red_amber green 0111-- red_amber twinkle_amber 0110-- twinkle_amber red 0101-- twinkle_amber twinkle_dark 0100-- twinkle_dark amber 0001-- twinkle_dark twinkle_amber 000.end_kiss.endThis file is available as “/home/beto/public/logic_synthesis/traf.kiss” in the UNIX-system.6RPH WLSVIt’s good to use commands like “print_stats” and “print_level” to see what is happening between the different steps in the optimization and mapping process. Also remember that “write_blif” can give some useful information in some cases.7KH H[DPSOH WKURXJK 6,6First we make the technology independent optimization. (That is what the first laboratory was about.) We use “state_minimize”, “state_assign” and then run “rugged-script”. We then get: UC Berkeley SIS with UCLA FPGA Extension (compiled 2-Apr-98 at 11:09 PM) VLV! UHDGBNLVV WUDI NLVV.start_kissVLV! VWDWHBPLQLPL]HRunning stamina, written by June Rho, University of Colorado at Boulder Number of states in original machine : 6Number of states in minimized machine : 5VLV! VWDWHBDVVLJQRunning nova, written by Tiziano Villa, UC BerkeleyWarning: network ‘SISEAAa29918’, node "v0" does not fanoutWarning: network ‘SISEAAa29918’, node "v1" does not fanoutWarning: network ‘SISEAAa29918’, node "v2" does not fanoutVLV! VRXUFH UXJJHGVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1ÃÃ.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names OUT_0 LatchOut_v4 OUT_201 1.names v6.1 v6.2 LatchOut_v5 v6.011- 11-0 1.names IN_0 IN_1 OUT_1 OUT_2 LatchOut_v5 v6.10-1-- 10--1- 100--0 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_1ÃÃ10- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.endThe key-word “.exdc” means that the following blif-description is the don’t-care-set. The description above is the optimized description of the function where don’t-cares are forced to one and zero to make the function as small as possible.*DWH 'HFRPSRVLWLRQIn the description of technology mapping from UCLA, it’s written that command“tech_decomp” should be run before “dmig”-command is run. The parameter “-k 4” in the “dmig”-command is chosen to 4 because the plan is to map this to an FPGA with 4-input LUTs.VLV! WHFKBGHFRPS D RVLV! GPLJ NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_1ÃÃ00 1.names OUT_0 LatchOut_v4 OUT_201 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names [23] [24] v6.21- 1-1 1.names v6.1 LatchOut_v5 [21]10 1.names v6.1 v6.2 [22]11 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 [23]0011 1.names LatchOut_v4 LatchOut_v5 [24]00 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 OUT_2 [26]01 1.names IN_0 OUT_1 [27]01 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.endÃÃ/87 0DSSLQJWhen gate decomposition is done there are some commands to choose between, which map the function to LUTs (Look Up Tables).VLV! GDJPDS NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_201- 1-11 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.names LatchOut_v5 [25] [26] [27] [21]01-- 1ÃÃ0-1- 10--1 1.names v6.2 [25] [26] [27] [22]11-- 11-1- 11--1 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 LatchOut_v3 LatchOut_v4 LatchOut_v5 [26]001- 10-11 1.names IN_0 LatchOut_v3 LatchOut_v5 [27]000 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5.outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.end3RVW SURFHVVLQJ FRPPDQGVThe post-processing command “mpack” can for some cases merge two LUTs into one LUT. VLV! PSDFN NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 010ÃÃ0-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_201- 1-11 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.names LatchOut_v5 [25] [26] [27] [21]01-- 10-1- 10--1 1.names v6.2 [25] [26] [27] [22]11-- 11-1- 11--1 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 LatchOut_v3 LatchOut_v4 LatchOut_v5 [26]001- 10-11 1.names IN_0 LatchOut_v3 LatchOut_v5 [27]000 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1ÃÃ.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.end3URJUDPPDEOH /RJLF %ORFN *HQHUDWLRQIn our installation of SIS it is possible to map to Xilinx 3000 and 4000 –series.VLV! PDWFKB N Y##PI=3 #PO=3 #LUT=11 #CLB=6 #LEVEL=3#0001: ( OUT_2 , v6.2 )#0002: ( OUT_1 , [26] )#0003: ( OUT_0 , [27] )#0004: ( v6.1 , [21] )#0005: ( v6.0 , [25] )#0006: ( [22] ) sis> match_3k -vThe argument “-v” makes it print the list about which LUTs should be in the same CLB. $SSHQGL[$SSHQGL[ $+--------------------------------------------------------------------------+ | RASP_SYN: LUT-Based FPGA Technology Mapping Package (Release B 1.0) | | -- Synthesis Core of the UCLA RASP Systems | +--------------------------------------------------------------------------+ | Copyright (C) 1991-1997 the Regents of University of California | +--------------------------------------------------------------------------+ | Authors: Eugene Ding, VLSI CAD Lab, UCLA CS Dept. <eugene@> | | Yean-Yow Hwang, VLSI CAD Lab, UCLA CS Dept.<yeanyow@>| | Chang Wu, VLSI CAD Lab, UCLA CS Dept. <changwu@> | | Songjie Xu, VLSI CAD Lab, UCLA CS Dept. <sxu@> | | Project Director: Prof. Jason Cong, UCLA CS Dept. <cong@> | +--------------------------------------------------------------------------+ | This release includes the following mapping algorithms: | | DAG_Map version 1.0 | | FlowMap version 2.1 | | FlowMap-r version 2.0 | | FlowSYN version 2.0 | | CutMap version 1.2 | | ZMap version 1.0 | | TurboMap version 1.0+--------------------------------------------------------------------------+ -------------------<0> ACKNOWLEDGEMENTÃÃ-------------------The FlowMap and CutMap and TurboMap packages are integrated into the SIS system and uses many of the routines provided by SIS. The SIS system was developed in UC Berkeley Electronic Research Lab.--------------------------------------<1> RELEASE AGREEMENT AND CONTACT INFO--------------------------------------Please refer to "release.statement".-----------<2> CONTENT-----------sis -- binary of SIS compiled with FlowMap andCutMap packages.doc -- this file.release.statement -- to be read first.rasp_syn -- a csh script of FPGA mappingselect -- mapping result selectorThis release contains programs primarily developed by September 1997. More functions will be added to future release when they are stablized. It runs on Sun SPARCstation under SunOS 4.1.3 and Solaris.Some commands are not included in the release due to nondisclosure agreement.RASP_SYN package provides a complete solution to SRAM-based FPGA mapping engine. The entire flow of RASP_SYN is:1. gate decomposition to get K-bounded circuit, where K is thefanin limit of LUTs of the target architecture2. generic LUT mapping3. post-processing mainly for area reduction4. architecture specific mapping.RASP_SYN comes with a user-friendly csh script for the ease of use. However, you can modify the script or write your own based on your specific needs.------------------------<3> TECHNICAL REFERENCES------------------------J. Cong, Y. Ding, "An Optimal Technology Mapping Algorithm for DelayOptimization in Lookup-Table based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, Jan. 1994, pp. 1-12.J. Cong, Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, Vol 2., No. 2, June 1994,pp. 137-148.J. Cong, Y. Ding, T. Gao, K. Chen, "LUT-Based FPGA Technology Mappingunder Arbitrary Net-Delay Models," Computers & Graphics,Vol.18, No.4, 1994, 507-516.J. Cong, Y. Ding, "Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs," Proc. 1993 IEEE/ACM Int’l Conf. on CAD,Santa Clara, CA, Nov. 1993, pp. 110-114.K.Chen, J.Cong, Y.Ding, A.Kahng, P.Trajmar, "DAG-MAP: Graph-BasedÃÃFPGA Technology Mapping for Delay Optimization," IEEE Design & Testof Computers, Sept. 1992J. Cong, J. Peck, Y. Ding, "RASP: A General Logic Synthesis System forSRAM-based FPGAs," Proc. ACM 4th Int’l Symp. on FPGA, pp. 137-143, 1996J. Cong, Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-BasedFPGA Mapping," Proc. ACM 3rd Int’l Symp. on FPGA, Feb. 1995, pp. 68-74.J. Cong, Y. Hwang, "Structural Gate Decomposition for Depth-OptimalTechnology Mapping in LUT-based FPGA Designs," Proc. ACM/IEEE 33rdDesign Automation Conf., pp. 726-729, 1996.J. Cong, C. Wu, "An Improved Algorithm for Performance Optimal TechnologyMapping with Retiming in LUT-Based FPGA Design," Proc. IEEE InternalConference on Computer Design, pp. 572-578, 1996Xilinx, FPGA Data Book, 1994---------<4> USAGE---------4.1 Running with a super scriptSuper Script of UCLA FPGA MappingUsage: rasp_syn circuit -sis path -k k -device xc3k/xc4k -algo algo -relax r -objective area/delay/tradeoff/allRasp_syn is a csh script for an easy usage of UCLA FPGA Mapping algorithms.In default, the input is in EQN format with extension .eqn. The output isan LUT network with/without matching information in EQN format as well.Please keep the program "select" in the current directory.To use other data formats as BLIF or SLIF which are supported by SIS of UCB, please set FMT in rasp_syn script to blif or slif and use .blif or .slifas the name extension of the input file. The output format will be changed automatically, except the CLB matching file format, which will be keptin EQN format. For Xilinx XC3K/XC4K CLBs, the CLB clustering informationwill be presented as:#CLB_number: (lut1, lut2)lut1 = ..lut2 = ..There are two ways to run rasp_syn:1. Running with single given mapping algorithmThe algorithm must be specified with option -algo algorithm. The targetis K-LUT. The output circuit is in circuit.k in EQN format.2. Running with multiple algorithmsRasp_syn can run all the built-in algorithms automatically and returnthe best result (in terms of area or delay) or a set of resultsbased on area-delay tradeoff or all the results for you.To run multiple algorithms, you simply do not specify any algorithm with-algo option.OptionsÃÃ-sis Specify the path of sis. The default is sis and the pathmust be specified in the environment.-k Used only in single algorithm mode. K is the input numberof LUTs. The output is in circuit.k.-device Used only in multi-algorithm mode. This is the default mode. The current supported devices are:xc3k Xilinx XC3000 Familyxc4k Xilinx XC4000 Family-algo Specify the mapping algorithm in single algorithm mode.The current supported algorithms are:flowmap: FlowMapflowmap-r: FlowMap-rflowsyn: FlowSYNcutmap: CutMapzmap: ZMap for delayzma: ZMap for area-relax Used only in single algorithm mode with FlowMap-r.R is the depth relaxation.-objective Used only in multi-algorithm mode. The objective can be:area: Area first. This is the default objective.delay: Depth firsttradeoff: Area-delay tradeoffall: All the results4.2 Running SIS without the super scriptSIS is a complete logic synthesis package. All of the following commands have been built in SIS which can be run directly from SIS.Commands provided by UCLA FPGA Mapping Package--------------------------------------------------------------------1. Gate Decomposition Commands* dmig [ -k <K_value> ] [ -f ]Decompose a simple gate network into a K-bounded network(i.e. each gate has no more than K inputs), orcomplex gates into K-bounded gates with -f option.For obtaining a simple gate network, use sis command"tech_decomp -a 1000 -o 1000."-k specifies max. gate input size K, with a default value 2.-f decompose complex gates in the network* dogma [ -k <K_value> ]Decompose a simple gate network into a 2-bounded networksuch that flowmap, cutmap, or zmap can obtain a best (small) depth.-k specifies the LUT input size K, with a default value 5.--------------------------------------------------------------------2. LUT Mapping Commands* dagmap [ -k <K_value> ]Map a K-bounded network into a K-LUT network of small depthÃÃ(might not be optimal).-k specifies the LUT input size K, with a default value 5.* flowmap [ -k <K_value> ] [-r <R_value> ] [ -s <S_value> ]Map a K-bounded network into a K-LUT network of optimal depth,or within the optimal depth plus R.Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-r specifies the relaxed depth value R.If -r is not used, every node is at its optimal depth,-r 0 will trade depth on non-critical paths for a smaller area(the LUT network still has an optimal depth),-r R will allow depth to increase by R (then dfmap is called toreduce the area).-s specifies the cone input size S for which resynthesis of conesare performed for a smaller LUT network depth.* dfmap [ -k <K_value> ]Map a K-bounded network into a K-LUT network of optimal areaWITHOUT any node duplication.It is used after flowmap -r and mffc_shrink, and is followedby a LUT packing procedure. For example, we use dfmap in"flowmap -k 5 -r 1; mffc_shrink -k 5; dfmap -k 5; greedy_pack -k 5"-k specifies the LUT input size K, with a default value 5.* cutmap [ -k <K_value> ] [-x ]Map a K-bounded network into a K-LUT network of optimal depthwith simultaneous area minimization.Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-x specifies depth relaxation on non-critical paths.* zmap [ -k <K_value> ] [-c ]Map a K-bounded network into a K-LUT network of optimal depthwith simultaneous area minimization (cut enumeration approach).Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-c will minimize area only with no bound on depth* turbomap [ -k <K_value> ] [-c <clock_value> ] [ -a <area_reduction> ]Map a K-bounded network into a K-LUT network with the minimum clockperiod. Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K,default value: 5.-c specifies an upper-bound on the clock period,-1: no upper-bound, (default)。

ARM Cortex-M7核基于SAMV71Q21RT的辐射抗性微控制器说明书

SummaryThe SAMV71Q21RT is a radiation tolerant microcontroller (MCU) providing the best combination of connectivity interfaces along with highest processing levels. The SAMV71Q21RT is designed for enhanced radiation performances, extreme temperature and high reliability in aerospace application. It takes advantage of the powerful M7 core coupled with high-bandwidth communication interfaces such as CAN FD and Ethernet TSN.SAMV71Q21RT ARM ®MicrocontrollerKey FeaturesCore• ARM ® Cortex ®-M7 Core running up to 300 MHz, delivering 600 DMIPS• 16 Kbytes of ICache and 16 Kbytes of DCache with Error Code Correction (ECC)• Single- and double-precision hardware Floating Point Unit (FPU)• Memory Protection Unit (MPU) with 16 zones • DSP Instructions, Thumb ®-2 Instruction Set• Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU)Memory• 2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data• 384 Kbytes embedded Multi-port SRAM• Tightly Coupled Memory (TCM) interface with four configu -rations (disabled, 2 x 32 Kbytes, 2 x 64 Kbytes, 2 x 128 Kbytes)• 16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines• 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash with on-the-fly scrambling• 16-bit SDRAM Controller (SDRAMC) interfacing up to 256 MB and with on-the-fly scramblingSystem• Embedded voltage regulator for single-supply operation• Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation• Quartz or ceramic resonator oscillators: 3 to 20 MHz main oscillator with failure detection, 12 MHz or 16 MHz needed for USB operations. Optional low-power 32.768 kHz for RTC or device clock.• RTC with Gregorian calendar mode, waveform generation in low-power modes• RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations• 32-bit low-power Real-Time Timer (RTT)• High-precision main RC oscillator with 12 MHz defaultfrequency for device startup. In-application trimming access for frequency adjustment. 8/12 MHz are factory-trimmed.• 32.768 kHz crystal oscillator or slow RC oscillator as source of low-power mode device clock (SLCK)• One 500 MHz PLL for system clock, one 480 MHz PLL for USB high-speed operations • Temperature sensor•One dual-port 24-channel central DMA Controller (XDMAC)The Microchip name and logo and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated. All Rights Reserved. 5/18DS00002650ASpace Environment• Full wafer lot traceability• 144-lead hermetic ceramic package • Space-grade screening and qualification• Total ionizing dose: dose at least 20 Krad, QML and ESCC • Heavy ions and protons test• Single event latch-up LET > 62 Mev•SEU full characterization at SEU full caracterization for all functional block• Estimated SER: 1 event every 1400 days (Core measure on LEO)Other Aerospace Application• Full wafer lot traceability • 144-lead plastic package• Extended temperature range –55°C/125°C • QML-N/AQEC/AEC-Q100 equivalent• Unitary burn-in and temperature cycling (opt.)• Neutrons latch-up immune •SEU full characterizationSAMV71Q21RT Tools GuideProduct Selection GuideMemorySystemCortex -M7300 MHzConnectivitySecurity User Interface Control System Performance• Deterministic code execution using TCM • Complex calculation and coprocessing (FPU)• Communication threads parallelism (Hmatrix architecture)• Low latency memories access • Scalable power saving modes•Operating system free RTOS supportedOngoing Port: RTEMS and Xstratum。

融合元学习和PPO算法的四足机器人运动技能学习方法

第41卷第1期2024年1月控制理论与应用Control Theory&ApplicationsV ol.41No.1Jan.2024融合元学习和PPO算法的四足机器人运动技能学习方法朱晓庆†,刘鑫源,阮晓钢,张思远,李春阳,李鹏(北京工业大学信息学部,北京100020;计算智能与智能系统北京市重点实验室，北京100020)摘要:具备学习能力是高等动物智能的典型表现特征,为探明四足动物运动技能学习机理,本文对四足机器人步态学习任务进行研究,复现了四足动物的节律步态学习过程.近年来,近端策略优化(PPO)算法作为深度强化学习的典型代表,普遍被用于四足机器人步态学习任务,实验效果较好且仅需较少的超参数.然而,在多维输入输出场景下,其容易收敛到局部最优点,表现为四足机器人学习到步态节律信号杂乱且重心震荡严重.为解决上述问题,在元学习启发下,基于元学习具有刻画学习过程高维抽象表征优势,本文提出了一种融合元学习和PPO思想的元近端策略优化(MPPO)算法,该算法可以让四足机器人进化学习到更优步态.在PyBullet仿真平台上的仿真实验结果表明,本文提出的算法可以使四足机器人学会行走运动技能,且与柔性行动者评价器(SAC)和PPO算法的对比实验显示,本文提出的MPPO算法具有步态节律信号更规律、行走速度更快等优势.关键词:四足机器人;步态学习;强化学习;元学习引用格式:朱晓庆,刘鑫源,阮晓钢,等.融合元学习和PPO算法的四足机器人运动技能学习方法.控制理论与应用,2024,41(1):155–162DOI:10.7641/CTA.2023.20847A quadruped robot kinematic skill learning method integratingmeta-learning and PPO algorithmsZHU Xiao-qing†,LIU Xin-yuan,RUAN Xiao-gang,ZHANG Si-yuan,LI Chun-yang,LI Peng(Faulty of Information Technology,Beijing University of Technology,Beijing100020,China;Beijing Key Laboratory of Computational Intelligence and Intelligent System,Beijing100020,China) Abstract:Learning ability is a typical characteristic of higher animal intelligence.In order to explore the learning mechanism of quadruped motor skills,this paper studies the gait learning task of quadruped robots,and reproduces the rhythmic gait learning process of quadruped animals from scratch.In recent years,proximal policy optimization(PPO) algorithm,as a typical representative algorithm of deep reinforcement learning,has been widely used in gait learning tasks for quadruped robots,with good experimental results and fewer hyperparameters required.However,in the multi-dimensional input and output scenario,it is easy to converge to the local optimum point,in the experimental environment of this study,the gait rhythm signals of the trained quadruped robot were irregular,and the center of gravity oscillates.To solve the above problems,inspired by meta-learning,based on the advantage of meta-learning in characterizing the high-dimensional abstract representation of learning processes,this paper proposes an meta proximal policy optimization (MPPO)algorithm that combines meta-learning and PPO algorithms.This algorithm can enable quadruped robots to learn better gait.The simulation results on the PyBullet simulation platform show that the algorithm proposed in this paper can enable quadruped robots to learn walking pared with soft actor-critic(SAC)and PPO algorithms,the MPPO algorithm proposed in this paper has advantages such as more regular gait rhythm signals and faster walking speed.Key words:quadruped robot;gait learning;reinforcement learning;meta-learningCitation:ZHU Xiaoqing,LIU Xinyuan,RUAN Xiaogang,et al.A quadruped robot kinematic skill learning method integrating meta-learning and PPO algorithms.Control Theory&Applications,2024,41(1):155–162收稿日期:2022–09–27;录用日期:2023–05–06.†通信作者.E-mail:*******************.cn.本文责任编委:吴敏.国家自然科学基金项目(62103009),北京市自然科学基金项目(4202005)资助.Supported by the National Natural Science Foundation of China(62103009)and the Natural Science Foundation Project of Beijing(4202005).156控制理论与应用第41卷1引言近些年,移动机器人由于可在多种场景下完成任务受到广泛关注,移动机器人被分类为:轮式机器人、履带式机器人和足式机器人[1];由于结构问题,传统轮式机器人和履带式机器人可应用的场景范围较小,在非平坦地形上,存在越障能力差以及由于地形多变而造成重心不稳等问题[2].相反,足式机器人由于其仿生的腿部结构而拥有更高的灵活性和适应性,可以像动物一样在各种地形完成行走任务[3–4].根据足数量的不同可以将足式机器人进行分类,相较于双足机器人和六足机器人,四足机器人在结构上具备更稳定和更易控制的优点.正因此四足机器人在医疗、物资运输、环境勘探和资源采集等场景中具备很大的应用前景.通过人为指定运动速度的方式,使机器人具备像动物一样的行走姿态[5],这种方法需要人为设置控制器.然而,这种控制器的设计流程更为繁琐,特别是针对机器人的系统和腿部的控制器,不仅对设计者的专业知识水平有较高的要求,而且,在实际应用过程中,控制器的具体参数也需要反复调整和试验[6–7].强化学习[8]具备让智能体自己学习的能力,近年来该技术在各应用领域蓬勃发展[9–11].在机器人设计、操作、导航和控制等方面，也以此为基础不断拓展[12–13].为了解决传统的基于人工设计的控制器存在的问题,越来越多的研究使用强化学习来代替原有设计方式[14],Kohl和Stone[15]在底层控制器设计完善的基础上,通过强化学习调整控制器参数,训练出了四足机器人Aibo的行走控制策略,代替原有的手动设置参数的过程,并且由强化学习训练的步态行走速度快于当时手动调参可达到的最快步态;Peng等人[6]先对动物的动作进行捕捉,得到四足机器人目标动作,之后利用强化学习来让四足机器人完成目标动作,实现了让机器人通过模仿动物来学习运动技能;ETH团队[16]引用策略调整轨迹生成器(policies modulating trajectory generators,PMTG)架构,即设计一个轨迹生成器作为先验,再通过强化学习对前面轨迹生成器进行调整,其中应用了课程学习[17],教师策略中通过编码器将视觉信息和本体感知信息融合编码成隐变量,再让学生策略通过机器人的历史状态来提取隐变量得到机器人的控制策略,并通过在机器人建模时使用随机化处理和训练神经网络电机模型实现了将强化学习算法实际部署在物理机器人上,完成了多种地形上的鲁棒性行走[18–20].上述研究或通过良好的运动先验知识或通过精心设置的奖励函数实现了机器人步态学习和在物理机器人上的部署,然而如何在少量运动先验前提下,通过简单奖励函数快速有效地学会四足机器人步态仍是一个正在面临的挑战.本文在Shi等人的研究[21]基础上,提出一种基于生物启发的元近端策略优化(meta proximal policy opti-mization,MPPO)算法,在有运动先验知识的情况下,仅通过简单奖励函数来快速学习机器人行走技能,和现有强化学习算法柔性行动者评价器(soft actor-critic, SAC)和近端策略优化(proximal policy optimization, PPO)的对比试验结果来看,本文的算法具备一定程度的有效性.2算法设计2.1近端策略优化算法对于机器人系统,策略梯度(policy gradient)算法针对连续动作空间的任务,可取得显著成效,传统策略梯度算法的基本思想是通过最大化状态价值(value)函数Vπ(s)来更新策略(policy)函数,即直接去优化策略网络,更新策略函数的损失函数被定义为L(θ)=∑logπ(a|s;θ)f(s,a),(1)其中f(s,a)为在状态s下采取动作a的评估,策略的梯度表示为g(θ)=E[∞∑t=0φt∇θlogπθ(a t|s t)],(2)最后通过式(3)更新参数θθ←θ+αg(θ).(3)其中φt有多种计算方法,通常被表示为优势函数(adv-antage function),如式(4)所示,作为一个衡量当前动作好坏的标准,如结果为正,证明当前动作a在此策略下要更好,并且之后提高此动作的概率以优化策略,即Aπ(s t,a t)=Qπ(s t,a t)−Vπ(s t),(4)将式(4)代入式(2)得到g(θ)=E[∞∑t=0∇θlogπθ(a t|s t)Aπ(s t,a t)].(5)然而,传统的策略梯度算法在计算式(4)–(5)时会因偏差和方差的问题导致无法准确估计优势函数.以下考虑两种极端情况,以整条轨迹来估计优势函数时虽然不会有偏差,但是会有高方差的问题,即过拟合;假如以单步更新,虽然不会有方差,但会有很大的偏差,即欠拟合.因此,需要在这两种极端情况中间找到一个平衡,但是优势函数估计的偏差是无法避免的,导致算法性能对更新步长十分敏感,假如一次更新步长过大,将可能会导致下次采样完全偏离,也就导致策略偏离到新的位置,从而形成恶性循环.为了解决这个问题,PPO算法[22]在信任域策略优化(trust region pol-icy optimization,TRPO)[23]的基础上被提出.PPO算法在策略梯度这个同策略(on-policy)算法的基础上引入了重要性采样(importance sampling),将其变成了一个近–异策略(near off-policy)的算法.第1期朱晓庆等:融合元学习和PPO 算法的四足机器人运动技能学习方法157E x ∼p (x )[f (x )]=p (x )f (x )d x =q (x )p (x )q (x )f (x )d x =E x ∼q (x )[p (x )q (x )f (x )].(6)上式为重要性采样过程,将式(6)代入式(5)得到ˆg t =ˆEt [πθ(a t |s t )πθold (a t |s t )πθ(a t +1|s t +1)πθold (a t +1|s t +1)...πθ(a T |s T )πθold (a T |s T )∇θlog πθ(a t |s t )log ˆA t ],(7)只计算t 时刻的梯度公式就变为了ˆg t ≈ˆE t [πθ(a t |s t )πθold (a t |s t )∇θlog πθ(a t |s t )log ˆA t]=ˆEt [πθ(a t |s t )πθold (a t |s t )∇θπθ(a t |s t )πθ(a t |s t )ˆA t ]=ˆE t [∇θπθ(a t |s t )πθold (a t |s t )ˆA t ],(8)于是损失函数由式(1)变成了L (θ)=ˆEt [πθ(a t |s t )πθold (a t |s t )ˆA t ].(9)作为一个策略梯度算法的优化算法,PPO 算法核心思想是通过对式(9)引入截断(CLIP)限制更新幅度,让每次策略更新后落在一个信任域(trust region)里,以此解决了更新步长的问题,PPO 算法的损失函数如式(10)所示:L CLIP (θ)=ˆEt [min(πθ(a t |s t )πθold (a t |s t )ˆA t ,CLIP(πθ(a t |s t )πθold (a t |s t ),1−ϵ,1+ϵ)ˆA t )],(10)其中:ϵ是超参数,用来限制更新的大小;ˆAt 是优势函数在t 时刻的估计值.最终训练时的损失函数为L (θ)=ˆEt [L CLIP (θ)+c 1L VF (θ)−c 2S [πθ](s t )],(11)其中:c 1,c 2为系数,S 为熵,L VF (θ)是平方误差损失(V θ(s t )−V targ t )2.与TRPO 算法相比,PPO 的超参数较少,在计算上更易实施,且效果更好,因而受到广泛的关注和应用.2.2MPPOPPO 具有在大部分实验环境中有很好效果且具有较少超参数的优势,但是在多维输入输出场景下,如本文涉及的四足机器人步态学习任务实验环境中的呈现效果一般,且容易收敛到局部最优,表现为步态节律信号杂乱、重心震荡严重.为此,本文在融合元学习的基础上提出了MPPO 算法.不可知模型元学习(Model-agnostic meta-learning,MAML)[24–25]由元学习(meta learning)引出,元学习优势体现在可快速适应新任务且减轻过拟合现象.从特征学习角度看,元学习训练的模型参数通过少量梯度更新能在新任务上产生良好结果,这样的过程可被视为构建广泛适用于许多任务的模型本质表示.从系统角度看,元学习是最大化了新任务损失函数对参数的敏感性:灵敏度较高时,参数微小局部变化可导致任务损失的大幅改善.本文提出的MPPO 算法,融合元学习和强化学习思想,即不是找到当前观测下的最佳参数,而是希望找到可以广泛适应在不同观测上采样到的数据上的参数,让四足机器人遵循奖励函数学习到运动技能的本质,获得更高奖励值并达到更优步态.其算法伪代码和框图如表1和图1所示.表1算法1:MPPO 算法伪代码Table 1Pseudocode输入:49维观测向量.输出:12维动作向量.1初始化θ,θ′,设置α;2while 不收敛do3使用πθ策略和环境交互T 步,收集D =(s,a π(θ),r );4通过策略梯度下降方法更新参数得到预更新参数θ′,即θ′=θ−α∇θL (πθ),其中的L (πθ)使用式(2)计算;5使用πθ′策略和环境交互T 步,收集D =(s,a πθ′,r );6通过梯度策略下降法更新参数θ,即θ=θ−α∇θ′L (πθ′),其中的L (πθ′)使用式(2)计算.7end图1算法框图Fig.1Algorithmic ﬂowchart首先,使用全局策略πθ0和环境交互,并通过PPO算法流程更新参数得到预更新的参数θ′.由于PPO 策略的输出动作是一个高斯分布的采样结果,其训练方向会很多样.通过πθ′0和环境的交互收集到的D 0[s,a (πθ′0),r,s ′]作为数据用于更新策略πθ0,这步可以看作一个有预见性和兼顾性的预更新,对应了元学习中通过单个任务的训练误差更新一个中间策略,通过中间策略把当前任务上的测试误差作为元学习训练误差的更新方法,即不追求当前状态下的最优方向,转为追求下一状态下的优势方向,以此更新全局策略.在本文中,PPO 算法的演员(actor)和评判家(critic)网158控制理论与应用第41卷络都采用了长短期记忆网络(long short-term memory,LSTM)[26]网络,相比多层感知器(multilayer perce-ptron,MLP)网络,其对像机器人系统这样序列型的输入有更好效果.3实验3.1实验对象本文使用pybullet物理引擎[27]在gym环境中进行模拟实验,机器人为Laikago,它是一个12自由度的四足机器人,每条腿有3个自由度,分别为髋关节、摆动关节和膝关节,控制频率为38Hz,其身体参数即各关节活动范围如表2所示.表2四足机器人身体参数Table2Body parameters of quadruped robot身体参数数值正常站立尺寸/cm370×270×295整机质量/kg11关节自由度12髋关节活动范围/(◦)−46∼46摆动关节活动范围/(◦)−60∼240膝关节活动范围/(◦)−154.5∼−52.53.2实验设计为了验证本文MPPO算法有效性,将此算法和传统SAC[28]和PPO算法进行对比实验,实验设置如下.3.2.1奖励函数在强化学习问题中,奖励函数可以被视为智能体的目标,在智能体与环境交互的每一个时刻中,当遇到状态时,智能体会根据策略选择一个动作(action),同时由设定的奖励函数给出一个奖励值(reward),而智能体的目标就是学习到一个策略来最大化这个奖励,因此这个奖励函数的设置应与想达到的训练目标相匹配,通过奖励函数来教会智能体一个期望的技能或者说引导智能体的策略向期望的目标上发展.在本文使用的策略梯度算法中,首先通过设计奖励函数引导价值函数向其靠拢,再通过价值函数来引导策略进行学习,以此让机器人学习到期望的行走技能.为了让机器人学会平稳快速节能的行走,奖励函数被设计为r t=c1r vt +c2r et+c3r st,(12)其中c1,c2和c3为各部分奖励函数之间的系数.r v t =X t−X t−1t,(13)其中:X t代表机器人所处位置,t为根据控制频率计算的时间,这部分的奖励函数是为了鼓励机器人朝着期望的方向前进并且速度越快越好.r e t =E t,(14)其中E t代表能耗,这部分的奖励函数是通过负的系数来促使机器人兼顾能耗问题.r st=[1−tan(roll2+pitch2)],(15)其中:roll和pitch为机器人惯性运动单元(Inertial mo-tion unit,IMU)测得的俯仰角和横滚角,这部分的奖励通过一个双曲正切函数来引导机器人以更平稳的姿态行走.3个系数的大小影响了3个部分在奖励函数中的重要程度,通过这3部分奖励之间相互制约,机器人学会了一种兼顾速度稳定和低能耗的行走技能.3.2.2训练流程本文实验训练流程图如图2,为了加速训练过程,采用类似文献[14]的实验框架,受残差控制[29]启发,机器人输出由a cpg(t)和a mppo(t)两部分构成,a cpg(t)作为运动先验知识输出一个周期性的节律信号[30];a mppo(t)作为残差信号,其中a mppo(t)策略的输入即状态是49维的由3部分构成:1)12维的运动先验中枢模式发生器(Central pattern generators,CPG)参数;2)34维的机器人状态信息,其中24维是机器人的电机信息,包含4条腿的髋关节和2个膝关节的角度和速度,6维机器人质心姿态信息包含位姿(俯仰,横滚,偏航)与加速度(x,y,z3个方向)各3项,4维的足端接触检测信息(检测每条腿是否触地);3)3维机器人的位置信息(包括x,y,z3方向的位移).输出即动作是12维的期望位置,即每条腿髋关节和2个膝关节电机的期望位置,叠加成为机器人的动作输出.动作合成后,由比例微分控制(Proportion Differential,PD)控制器来跟踪实现对机器人腿部的控制.为了维持训练过程稳定性,两部分的动作网络采取分时训练[21]方法,即训练过程中先固定a cpg(t)网络的参数,并根据MPPO的算法流程更新a mppo(t)的参数,当交互够N步后,固定a mppo(t)的网络参数,通过进化算法对a cpg(t)进行更新,当一个网络参数进行训练的时候另一个网络就维持参数停止训练.图2训练流程图Fig.2Trainingﬂowchart4实验结果本实验使用笔记本电脑,训练过程中每2048步作为一个回合(episode),并在每个回合结束时进行一次第1期朱晓庆等:融合元学习和PPO 算法的四足机器人运动技能学习方法159评估.按照第3节设计的实验流程进行训练1,训练过程中四足机器人的行走步态和身体数据如图3–4所示.图3四足机器人行走步态学习过程截图,其中(a)–(c)为训练初期,(d)–(f)为训练末期Fig.3Screenshot of quadruped robot walking gait learningprocess.At the beginning of training,it appears as (a)–(c),and at the end of training,it appears as(d)–(f)图4训练前后机器人行走质心高度变化曲线Fig.4Height variation curve of robot walking centroid beforeand after training从图3(a)–(c)和图4可看出,在训练初期,四足机器人步态非常不稳定,身体上下晃动幅度在0.21到0.26之间,呈现较大且不规律的晃动,无法以正常姿态前进.随着训练进行300个回合时,机器人步态及身体数据如图3(d)–(f)和图4所示.可看出,在训练完成时,机器人的步态呈现出对角接触步态,行走过程中,身体的上下晃动幅度较小,在0.24到0.265之间,高于刚开始训练质心高度并呈现稳定的节律行走步态.该训练结果是由奖励函数中的r st 引导而来.对比上图训练开始时和训练结束时机器人行走质心高度的变化可看出,训练完成后机器人行走时更稳定且质心高度更高.图5是训练过程中的奖励值,从中可以看出,本文提出的MPPO 算法在四足机器人步态学习的任务中,奖励值可以从零开始迅速上升,大约到75个回合时,收敛于4000左右,75回合之间的过程是四足机器人从初始状态开始学习到可以初步完成行走任务的过程,训练回合超过75回合之后,奖励值缓慢上升至4500左右,并且策略趋于收敛,代表完成行走步态的学习.图5训练过程奖励值Fig.5Rewards during training图6和图7分别是机器人行走距离和行走偏移变化曲线,横坐标为回合数量,纵坐标分别为训练过程中机器人行走距离(每一次评估最多进行500步)和行走偏移量,虚线为期望前进方向即0偏移.图6中看出,本文提出的MPPO 算法在行走距离上从零开始迅速上升,在20个回合左右行走距离达到12左右,并在后续逐渐波动,最终在250个回合左右收敛至11.偏移量在100到150回合中逐渐变大,在150到200步逐渐变小,最终在300步时收敛到–0.1左右.这种笔直前进步态是由奖励函数中r vt 部分引导而来的.图6机器人行走距离变化曲线Fig.6Variation curve of robot walking distance1训练过程视频:https:///video/BV1Q24y117EQ/?vd source=4b5a3b89f1ef3731413895e73cb00b7e.160控制理论与应用第41卷图7机器人行走偏移变化曲线Fig.7Variation curve of robot walking deviation5讨论与总结5.1讨论为了验证本文算法的优势,本文将传统的PPO 算法和传统的SAC 算法与MPPO 算法进行了对比试验.在四足机器人步态的全部训练过程中,每2048步设置为一个回合,并且在每一个回合进行一次数据评估,实验结果如图8所示.图8机器人质心高度变化曲线Fig.8Height variation curve of robot centroid训练完成后分别对3种算法训练出的四足机器人步态进行行走测试2,图8为机器人行走测试中质心高度的变化,可看到本文提出的MPPO 算法训练结果相比较于传统PPO 算法和SAC 算法,行走步态质心起伏幅度更小,说明本文提出的MPPO 算法训练出的四足机器人步态有更好的稳定性;并且MPPO 算法训练的行走步态的质心高度整体高于传统的SAC 和PPO 算法,说明其行走步态使机器人在行走过程中拥有腿伸展程度更高,因此可以迈出更大的步伐.图9为训练过程中机器人行走的距离曲线,横坐标为回合数量,纵坐标为评估一次机器人行走的距离(每一次评估最多进行500步).从图中可看出,本文提出的MPPO 算法在行走距离上从零开始迅速上升,在20个回合左右行走距离达到12左右,并在后续逐渐波动,最终在250个回合左右收敛至11.相较于传统SAC 算法在20–50个回合行走距离从6上升至10,最终收敛至9.和传统PPO 算法在前100个回合有起伏最终收敛于6左右的实验结果.在相同上限步数的情况下,行走更远的距离就相当于拥有更大的步长和更快的速度,此实验结论和对比机器人行走时质心高度变化曲线得到结论相同,即本文提出的MPPO 算法训练出的行走步态有更大的行走步长和更好的稳定性.图9训练过程机器人行走距离曲线Fig.9Walking distance curve of robot during training从图10中可看出,本文提出的MPPO 算法在四足机器人步态学习的任务中,奖励上升幅度大,且最终收敛时的奖励值最高.图10训练过程奖励值Fig.10Rewards during training23种算法训练出的机器人步态对比视频:https:///video/BV17M411r7Ri/?vd source=4b5a3b89f1ef3731413895e 73cb00b7e.第1期朱晓庆等:融合元学习和PPO算法的四足机器人运动技能学习方法161而传统的SAC算法在有先验知识的基础上奖励值先降低后缓慢升高,大约到100回合的时候,奖励值收敛到3000左右,训练效果略低于本文提出算法;传统PPO算法在训练过程中奖励值略微升高后就急剧下降,收敛至2000左右陷入局部最优,训练效果远小于传统SAC算法和本文提出的MPPO算法,由上可知,本文所提出的算法在四足机器人步态学习的任务中效果优于传统的强化学习算法.5.2总结为阐明复现高等生物的运动技能学习机理,本文以四足机器人为研究对象,基于强化学习框架探究四足机器人技能学习算法,鉴于元学习具有刻画学习过程高维抽象表征优势,本文将元学习引入了PPO算法,提出了一种MPPO算法.以四足机器人行走步态作为任务进行学习训练,仿真实验结果验证了该算法可行性.本文提出的算法,仅需简单设计的奖励函数即可使得四足机器人学会走起来,并且相比较于SAC算法和PPO算法,本文的MPPO算法不仅在训练速度上有一定的优势,并且训练出的步态也呈现更佳效果,如其质心姿态更加平稳,震荡小.对比实验结果表明本文提出的MPPO算法具有兼顾性和预见性优势,可以解决四足机器人步态学习过程中出现的局部最优问题,学习到更优步态.后续将继续在MPPO算法中引入动态奖励函数,以获得更快的收敛速度以及更稳健的更新方向,并且在多地形任务上进行实验.在完成仿真实验后,将进行实物实验.参考文献:[1]MENG X G,WANG S,CAO Z Q,et al.A review of quadruped robot-s and environment perception.The35th Chinese Control Conference (CCC).Chengdu,China:IEEE,2016:6350–6356.[2]RUBIO F,V ALERO F,LLOPIS A C.A review of mobile robots:Concepts,methods,theoretical framework,and applications.Inter-national Journal of Advanced Robotic Systems,2019,16(2):1–22.[3]ZHONG Y H,WANG R X,FENG H S,et al.Analysis and researchof quadruped robot’s legs:A comprehensive review.International Journal of Advanced Robotic Systems,2019,16(3):1–15.[4]ZHUANG H C,GAO H B,DENG Z Q,et al.A review of heavy-dutylegged robots.Science China Technological Sciences,2014,57(2): 298–314.[5]GONC¸ALVES R S,CARV ALHO J C M.Review and latest trends inmobile robots used on power transmission lines.International Jour-nal of Advanced Robotic Systems,2013,10(12):408.[6]PENG X B,COUMANS E,ZHANG T N,et al.Learning agile robot-ic locomotion skills by imitating animals.ArXiv Preprint,2020:arX-iv:2004.00784.[7]CHEN Guangrong,GUO Sheng,HOU Bowen,et al.Motion controlof redundant hydraulic driven quadruped robot based on extended Ja-cobian matrix.Control Theory&Applications,2021,38(2):213–223.(陈光荣,郭盛,侯博文,等.基于扩展雅可比矩阵的冗余液压驱动四足机器人运动控制.控制理论与应用,2021,38(2):213–223.)[8]SUTTON R S.Introduction:The challenge of reinforcement learn-ing.Reinforcement Learning.Boston,MA:Springer,1992:1–3.[9]WEN Jianwei,ZHANG Li,DUAN Yanduo,et al.Activeﬂoor controlin data center based on model deep reinforcement learning.Control Theory&Applications,2022,39(6):1051–1056.(温建伟,张立,段彦夺,等.基于模型深度强化学习的数据中心主动地板控制.控制理论与应用,2022,39(6):1051–1056.)[10]QIN Rui,ZENG Shuai,LI Juanjuan,et al.Parallel enterprise re-source planning based on deep reinforcement learning.Acta Auto-matica Sinica,2017,43(9):1588–1596.(秦蕊,曾帅,李娟娟,等.基于深度强化学习的平行企业资源计划.自动化学报,2017,43(9):1588–1596.)[11]YU Shengping,HAN Xinchen,YUAN Zhiming,et al.Dynamic trainscheduling method for high speed rail based on strategy gradient rein-forcement learning.Control and Decision,2022,37(9):2407–2417.(俞胜平,韩忻辰,袁志明,等.基于策略梯度强化学习的高铁列车动态调度方法.控制与决策,2022,37(9):2407–2417.)[12]KHAN M A,KHAN M R J,TOOSHIL A,et al.A systematic re-view on reinforcement learning-based robotics within the last decade.IEEE Access,2020,8:176598–176623.[13]ZOU Qijie,LIU Shihui,ZHANG Yue,et al.Rapid exploration ofrandom tree path reprogramming algorithm based on reinforcemen-t learning in special environments.Control Theory&Applications, 2020,37(8):1737–1748.(邹启杰,刘世慧,张跃,等.基于强化学习的快速探索随机树特殊环境中路径重规划算法.控制理论与应用,2020,37(8):1737–1748.)[14]WANG J Y,HU C X,ZHU Y.CPG-based hierarchical locomotioncontrol for modular quadrupedal robots using deep reinforcement learning.IEEE Robotics and Automation Letters,2021,6(4):7193–7200.[15]KOHL N,STONE P.Policy gradient reinforcement learning for fastquadrupedal locomotion.Proceedings of the IEEE International Con-ference on Robotics and Automation.New Orleans,LA:IEEE,2004: 2619–2624.[16]ISCEN A,CALUWAERTS K,TAN J,et al.Policies modulating tra-jectory generators.ArXiv Preprint,2019:arXiv:1910.02812.[17]CHEN D,ZHOU B,KOLTUN V,et al.Learning by cheating.ArXivPreprint,2019:arXiv:1912.12294.[18]HWANGBO J,LEE J,DOSOVITSKIY A,et al.Learning agile anddynamic motor skills for legged robots.Science Robotics,2019, 4(26):eaau5872.[19]LEE J,HWANGBO J,WELLHAUSEN L,et al.Learning quadrupe-dal locomotion over challenging terrain.Science Robotics,2020, 5(47):eabc5986.[20]MIKI T,LEE J,HWANGBO J,et al.Learning robust perceptive lo-comotion for quadrupedal robots in the wild.Science Robotics,2022, 7(62):eabk2822.[21]SHI H J,ZHOU B,ZENG H S,et al.Reinforcement learning withevolutionary trajectory generator:A general approach for quadru-pedal locomotion.IEEE Robotics and Automation Letters,2022,7(2): 3085–3092.[22]SCHULMAN J,WOLSKI F,DHARIWAL P,et al.Proximal policyoptimization algorithms.ArXiv Preprint,2017:arXiv:1707.06347.。

RT-LAB中文使用手册

RT-LAB8.1版用户手册介绍1.1关于RT-LABRT-LAB是一个分布式实时平台，它能够在很短的时间内、以很低的花费，通过对进行工程仿真或者是对实物在回路的实时系统建立动态模型，使得工程系统的设计过程变的更加简单。

他的可测量性使得开发者能够把计算机使用到任何需要他的地方；充分的灵活性使得它能够应用于最复杂的仿真和控制问题，而不论是应用于实时硬件在回路还是快速模型，控制和测试中。

为了达到理想的性能，RT-LAB为分布式网络下分立目标机对高度复杂的模型进行仿真、通过超低反应时间通讯，提供了丰富的工具。

此外，RT-LAB的模型化设计使得用户仅仅提供应用所需的模型就能完成经济的系统、最小化经济要求、并满足用户的价格目标。

这在大量的嵌入式应用中尤其显得重要。

1.2主要特征完全集成MATLAB/Simulink，以及MATRIXx/SystemBuild所有为RT-LAB准备的模型都能够在已有的动态系统模型环境中完成，通过使用这些工具，用户的经验也会相应的提高。

分布式处理的专业化块设计，内部节点通讯以及信号I/ORT-LAB提供的工具能够方便的把系统模型分割成子系统，使得在目标机上能够并行处理（标准的PC上可以运行QNX实时操作系统，或者RedHawk Linux）。

通过这种方法，如果你不能在单处理器上运行实时模型，RT-LAB提供多个处理器共享一个负载的方法来实现的。

完全集成第三方建模环境以及用户代码库RT-LAB支持StateFlow，StateMate，CarSimRT，GT-PowerRT，AMESim，Dymola的模型，以及C，C++，FORTRAN的合法代码。

丰富的API为开发自己的在线应用使用诸如LabVIEW、C、C＋＋、Visual Basic、TestStand、Python and 3D virtual reality等工具可以轻松的创建定制的功能和自动测试界面。

非定制技术RT-LAB是第一个完全可测量的仿真和控制包，使得你能够分割模型，并在标准PC，PC/104s 或者SMP（对称式多处理器）组成的网络上并行运行。

MyLab 操作手册说明书

Rev. 02Mayo de 2018MyLabOPERACIONES AVANZADASSECCIÓN MYLIBRARY350025840Índice1MyLibrary.....................................................................................1-1 Activación de MyLibrary...........................................................................1-2 Organización de MyLibrary......................................................................1-6Capítulo11.MyLibraryMyLab incorpora el concepto de MyLibrary.MyLibrary proporciona la posibilidad de visualizar de manera integrada variosprocedimientos de acuerdo con los médicos de referencia. La información seestructura según un enfoque común, es decir: una imagen de la estructuraanatómica en cuestión, una imagen que muestra la posición sugerida de lasonda en el punto anatómico específico, la imagen clínica por ultrasonidosque se suele obtener del examen en el punto anatómico específico y algúntexto explicativo. MyLibrary está diseñado para su uso en formación, comorevisión o como recordatorio. Toda la información que se presenta enMyLibrary se ha elaborado bajo la completa autoridad del médico dereferencia que se menciona en la página de créditos. Antes de utilizar lainformación que se proporciona en MyLibrary es necesario tener un nivelbásico de conocimiento en exámenes por ultrasonido.MyLibrary es un entorno de software con un número limitado de imágenesde ejemplo que pueden ayudar al usuario a llevar a cabo el examen, ya que, si seutilizan correctamente, pueden servir de ayuda para interpretar correctamente lasimágenes y reconocer las principales estructuras anatómicas. MyLibrary sedebe utilizar prestando atención a las advertencias siguientes para evitar cualquierposible daño al paciente debido a la mala interpretación de las imágenes, aluso inadecuado del equipo de ultrasonidos o a la ejecución incorrecta de unprocedimiento.ATENCIÓN Los ejemplos solo representan un número limitado de casos o imágenes, no se incluyen todas las variaciones anatómicas posibles ni todos losresultados patológicos de distintas personas.Los procedimientos que se muestran se basan en procedimientos porultrasonidos definidos por el especialista de referencia de MyLibrary y losprocedimientos locales pueden ser diferentes de estos. El nombre delespecialista de referencia de MyLibrary se indica en la ventana de créditosde MyLibrary.Una mala interpretación de las imágenes de MyLibrary puede representarel riesgo de colocar una sonda en un punto equivocado.Para llevar a cabo procedimientos por ultrasonido es necesario contar conun nivel básico de conocimientos en exámenes médicos por ultrasonido,interpretación de imágenes de ultrasonido y manipulación de sondas deultrasonido.Se recomienda que el usuario tenga en cuenta esta advertencia para interpretar co-rrectamente las imágenes por ultrasonido y realizar el examen y los procedi-mientos teniendo en consideración las condiciones específicas del pacienteexaminado.NOTA MyLibrary requiere una licencia específica.Activación de MyLibraryMyLibrary es una herramienta opcional que proporciona ayuda para laaplicación y consejos para el uso del sistema durante los procedimientos.Para activar MyLibrary, toque MYLIBRARY en la sección de herramientas de lapantalla táctil y, a continuación, el tema que le interese. A continuación, seabrirá la página de aceptación.Esta página recuerda al usuario la importancia de utilizar MyLibrary según lasindicaciones de este manual y de acuerdo con las limitaciones inherentes deMyLibrary, y proporciona al usuario la información siguiente:MYLIBRARY ES UN ENTORNO DE SOFTWARE CON UN NÚMEROLIMITADO DE EJEMPLOS DE IMÁGENES QUE PUEDEN AYU-DAR AL USUARIO A LLEVAR A CABO EL EXAMEN, YA QUE, SISE UTILIZAN CORRECTAMENTE, PUEDEN SERVIR DE AYUDAPARA INTERPRETAR CORRECTAMENTE LAS IMÁGENES Y RECO-NOCER LAS PRINCIPALES ESTRUCTURAS ANATÓMICAS. MYLI-BRARY SE DEBE UTILIZAR PRESTANDO ATENCIÓN A LASSIGUIENTES ADVERTENCIAS PARA EVITAR CUALQUIER POSI-BLE DAÑO AL PACIENTE DEBIDO A LA MALA INTERPRETA-CIÓN DE LAS IMÁGENES, AL USO INADECUADO DEL EQUIPO DEULTRASONIDOS O A LA MALA EJECUCIÓN DE LOS PROCEDI-MIENTOS.∙LOS EJEMPLOS SOLO REPRESENTAN UN NÚMERO LIMITADO DE CASOS O IMÁGENES. NO SEINCLUYEN TODAS LAS V ARIACIONES ANATÓMICASO PATOLOGÍAS POSIBLES NI TODOS LOS RESULTA-DOS PATOLÓGICOS DE DISTINTAS PERSONAS.∙ESAOTE SUBRAYA LA IMPORTANCIA DE QUE EL USUARIO OBTENGA, MEDIANTE CURSOS DEFORMACIÓN ADECUADOS, LOS CONOCIMIENTOSY HABILIDADES ADECUADOS PARA EL USO DEEQUIPOS DE ULTRASONIDOS, LA INTERPRETACIÓNDE LAS IMÁGENES DE ULTRASONIDOS Y LOSPROCEDIMIENTOS.∙MYLIBRARY NO PUEDE SUSTITUIR LA FORMACIÓN ADECUADA DEL USUARIO EN GESTIÓN DELEQUIPO DE ULTRASONIDOS, INTERPRETACIÓN DELAS IMÁGENES DE ULTRASONIDOS Y EJECUCIÓNDE PROCEDIMIENTOS.ADEMÁS DE ESTAS ADVERTENCIAS, EL USUARIO DEBE LEER Y SEGUIR LAS INSTRUCCIONES Y LAS ADVERTENCIAS DEL MANUAL DE USUARIO PARA UTILIZAR MYLIBRARY DE MODO SEGURO. DEPENDERÁ DEL USUARIO INTERPRETAR CORRECTAMENTE LAS IMÁGENES POR ULTRASONIDO Y REALIZAR EL EXAMEN Y LOS PROCEDIMIENTOS TENIENDO EN CONSIDERACIÓN LAS CONDICIONES ESPECÍFICAS DEL PACIENTE EXAMINADO.Para continuar y activar MyLibrary, el usuario debe pulsar ACCEPT.El usuario solo deberá pulsar este botón si ha alcanzado el nivel adecuado de conocimientos leyendo este Manual del Usuario sobre las funciones y las limitaciones de la herramienta MyLibrary, y es capaz de interpretar correctamente la información proporcionada en MyLibrary.Después de la aceptación, se abre la pantalla de créditos con la versión de MyLibrary y el autor de la biblioteca.Fig. 1-1: Pantalla de créditosEn dicha pantalla aparece también el mensaje siguiente sobre exención de responsabilidad:MYLIBRARY ES UNA HERRAMIENTA DE REFERENCIA QUE PROPORCIONA INFORMACIÓN Y SUGERENCIAS QUE NO PRETENDEN ANULAR NI MODIFICAR EN NINGÚN CASO EL PROCEDIMIENTO DE OPERACIÓN ESTÁNDAR LOCAL. LOS PROCEDIMIENTOS QUE SE MUESTRAN SE BASADOS EN PROCEDIMIENTOS POR ULTRASONIDOS DEFINIDOS POR EL ESPECIALISTA DE REFERENCIA DE MYLIBRARY Y LOS PROCEDIMIENTOS LOCALES PUEDEN SER DIFERENTES DE ESTOS. ESAOTE NO ES RESPONSABLE DE LOS RESULTADOS NI DE LAS CONSECUENCIAS DE NINGÚN PROCEDIMIENTO REALIZADO. EL USUARIO DEBE LEER Y OBSERVAR LAS ADVERTENCIAS DEL MANUAL DEL USUARIO PARA UTILIZAR CORRECTAMENTE LA HERRAMIENTA MYLIBRARY.La pantalla táctil está organizada con botones que representan varios puntos anatómicos relacionados con el tema de la biblioteca seleccionada (por ejemplo, JOINT o WRIST en Reumatología). Si selecciona un punto anatómico, aparecen botones adicionales para que poder seleccionar una de las vistas disponibles (es decir, DORSAL, LATERAL o VOLAR).Los botones siguientes adicionales de la pantalla táctil están presentes en todos los puntos anatómicos y todas las vistas:MODO BARR permite visualizar la imagen completa en tiempo real. PulseMYLIBRARY para volver al entorno MyLibrary.PAN CRÉDITOS abre la pantalla de créditos.TIPO VISTA cambia la vista del examen.Vista previa1La tecla VIS PREV DIR activa la imagen en tiempo real en el entorno de MyLibrary para que el usuario pueda compararla con la imagen por ultrasonidosde ejemplo de la base de datos de MyLibrary.ATENCIÓN La función Vista previa permite visualizar la imagen en tiempo real en MyLibrary para compararla con los ejemplos de imágenes disponibles.El entorno de visualización no es adecuado para realizar ningunainterpretación de las imágenes por ultrasonido.NOTA En Vista previa no se puede cambiar la configuración de la imagen en tiempo real. Vista previa no está disponible en EE.UU.Organización de MyLibrary Fig. 1-2: MyLibrary Después de seleccionar una biblioteca, en el entorno MyLibrary aparece una imagen dividida en cuatro partes:1.Una imagen de la estructura anatómica.2.Una imagen con un ejemplo de examen en la aplicaciónespecífica, con la ubicación sugerida de la sonda marcada enel punto anatómico concreto. imagen clínica por ultrasonidos de ejemplo obtenida conel examen en el punto anatómico específico.4.En el área superior derecha puede aparecer texto o la Vista previa .1234。

伯克利大学纳米实验室设备手册 Alpha-Step IQ Surface Profiler - 副本

Marvell NanoLab Member login Lab Manual Contents MercuryWeb Berkeley MicrolabChapter 8.11Alpha-Step IQ Surface Profiler(asiq - 584)1.0 TitleAlpha-Step IQ Surface Profiler2.0 PurposeThe Alpha-step IQ is a mechanical, stylus-based step profiler that can measure step heights up to 2 millimeters, save programs for later use, and provide data analysis and image capture of scans.3.0 ScopeThis manual will describe the basic operation of this tool.4.0 Applicable DocumentsRevision HistoryKLA-Tencor has provided an on-line (beta version) manual for this tool. This manual will be available to Users by request only. Please contact Matthew Wasilik to obtain this file.5.0 Definitions & Process Terminology5.1 SpecificationsScanning stylus (standard): 5-micron radius tip, 60 angled stylusStylus force: 15 mg (nominal setting)Profile length (max): 10 mm in the right direction2 mm in the left directionMaximum step height: 2 mm (for stepping down conditions only)Scan Length: 10 mmScan Speed: 2 µm/s to 200 µm/sSampling Rate: 50, 100, 200, 500 or 1000 HzVertical Range: ± 10 µm (20 µm) at 0.012 Å vertical resolution± 200 µm (400 µm) at 0.24 Å vertical resolution± 1000 µm (2000 µm) at 1.2 Å vertical resolution Horizontal Resolution: 0.01 µm (100 Å) at 2 µm/s scan speedScan Method: Moving stylus, stationary stageStylus Control: Manually adjustable forceRange: 1.0 – 99.9 mgResolution: 0.1 mg (~ 0.5mg standard deviation)Optical Magnification: 1) Standard: 70 – 210 x2) High Mag. option: 160 – 480 xStep Height Repeatability: 1) At 20 µm range: 0.0008 µm (8 Å) typical standarddeviation1 or 0.1% of measured vertical range.2) At 400 µm range 0.005 µm (4000 Å) typical standarddeviation or 0.2% of the measured vertical range.3) At 2000 µm range 0.030 µm (2 µm) typical standarddeviation or 0.5% of the measured vertical range.Z control : interactive control via softwareMaximum sample size: 158 mm diameterMaximum sample thickness: 21 mmMaximum sample weight: 1 kgmmThroatdepth: 81X/Y maximum travel: 151mm x 80 mmStage rotation: 360°, unlimited manual rotationLeveling: manual and various software leveling of profiles5.2 Scan ParametersThe main screen displays the scan parameters, the live video image of the sample and stylus, and the scan trace. The different parameters are described here.5.2.1 Scan Length - Can be entered in units of µm (10 mm max in right direction, 2 mm max inleft direction)5.2.2 Number of Scans - A multi-scan mode of up to 10 repeated scans at the position can beselected. The mean and standard deviation of the measurements will be calculated.5.2.3 Scan Speed - Speeds between 2 to 200 µm/s can be selected by the user.5.2.4 Advanced - This menu gives other options for scan speed, including scan delay. Moreinformation on this will be added at a later time.5.2.5Sampling Rate - Rates between 50 to 1000 Hz can be selected by the user.5.2.6 Scan Time - This is automatically determined by the Scan Length, Scan Speed, andNumber of Scans parameters that are selected by the user.5.2.7 Scan Direction - Either the right or left direction arrow can be selected by the user. Notethat the maximum scan length differs by direction: 10 mm max in right direction, 2 mmmax in the left direction.5.2.8 Resolution - This is automatically determined by the Scan Speed, and Sampling Rateparameters that are selected by the user. For example, a slower scan speed and highersampling rate will yield better resolution.5.2.9 Sensor Range - The ASIQ has 3 types of sensors with ranges of 20 µm, 400 µm, and 2mm, respectively. The user can select which sensor best suits their scan purposes.Note: If the user is not sure of the dimensions of the features to be scanned, a sensor with the largest range should be used first for measurements.Choosing a sensor with a smaller range than the actual feature size canresult in damage to the sensor and to the sample. Also, when stepping upfrom bottom to the top of a feature (peak bias), it is preferred that themaximum distance not exceeds the dimension of 875 microns. This willprevent potential damage to the stylus.5.2.10 AdjustmentThe user can choose from 3 different biases: Center, Valley, and Peak bias.Note: When using the 20-µm sensor, only the center bias can be used. For the 400- m and 2-mm sensor ranges, any of the 3 biases can be used.5.2.10.1 Center Bias – Divides the range into equal ± halves, i.e., for the 400-µmrange, ± 200 µm can be measured. The center bias setting is optimized for arandomly distributed surface measurement.5.2.10.2 Valley bBas – The full range is measured below the starting point (for the 400µm range, 0 to – 400 µm can be measured). The valley bias setting isoptimized for a hole or trench measurement.5.2.10.3 Peak Bias – The full range is measured above the starting point (for the 400µm range, 0 to + 400 µm can be measured). The peak bias setting isoptimized for measuring “bumps” on a surface.Note: When using peak bias, it is preferred that the maximum distancenot exceeds the dimension shown in Figure 2. This will preventpotential damage to the stylus.5.2.11Required Stylus ForceThis parameter box should be colored green, which indicates that the value is within 10%of the set point. If the color is yellow or red, report on FAULTS.Note: Deep trench measurements may require adjustment to the stylus force.Users may be trained to do this. Send email to ASIQ@silicon with specificrequest if you wish to be trained for this.5.2.12 Contact SpeedThe speed at which the stylus approaches the sample, on a scale from 1 to 10. Thedefault value for silicon is 5. For softer materials (gold, photoresist, etc.) a lower settingshould be used (1-3). In order to prolong the life of the stylus tip, it is not recommendedthat a contact speed value higher than 5 be used.5.2.13 Required Radius - Set at 5 µm. Only one stylus is available for the ASIQ, so this valueis not to be changed.5.2.14 Elevator Position - Records the position of the stage.5.2.15 AnalysisThree types of data analysis can be selected. Measured Profile shows the original scanprofile. Step Height Analysis allows the user to perform various types of data analysis,including leveling, zooming in on a particular part of the data, etc. Roughness/Wavinessmode – information on this type of analysis will be added at a later date.5.3 Video ImageA live image of the sample and the stylus (when it is in the lowered position) is shown on the rightside of the screen.5.3.1 Capture VideoOne still image can be captured and saved with the current recipe. It will also beincluded in the data analysis report that is automatically generated.5.3.2 Delete VideoThe captured image can be deleted and a new image captured at any time.5.4 Stylus ControlThe up and down arrows next to the live image box controls the stylus and the elevator. Clickingon the up or down arrows once will raise or lower the stylus from its housing, respectively.Clicking and holding down the up arrow will lower the stage, and the stylus will be left raisedabove the sample. Clicking and holding down the down arrow will bring the stylus into contactwith the sample on the stage.5.5 Scan Trace and AnalysisThe main screen displays the scan trace and the main features of data analysis.The parameters of the scan trace that are displayed can be chosen by clicking the Parametersmenu.Some of the main scan trace parameters include:Pos (L), (R)Profile height at intersection with left/right cursor. (When the 2-zoneoption is chosen, the height at the midpoint of the zone is given.) Height (L), (R) Calculated difference between heights at 2 bars/zones.TIR Total Indicator Run out - difference between maximum and minimumprofile heights for section of plot between measurement cursors.Width Width between the 2 bars/zones.There are several other parameters available for data analysis, including Ave, Slope, Radius,Area+, Area-, MaxHt, MinHt, etc.6.0 Safety7.0 Statistical/Process Data8.0 Available Process, Gases, Process Notes8.1 Surface Roughness MeasurementsThe standard stylus at ASIQ has a 5 micron radius tip. This radius can affect roughness data. Ifthe wavelengths on the substrate surface are short relative to the stylus radius, they will notregister on the trace or will be attenuated in height. The minimum wave on the substrate shouldbe large enough to accommodate the stylus in order to receive accurate roughness data.9.0 Equipment Operation9.1 Setting Scan Parameters9.1.2 Scan parameters can be saved as a recipe in a user’s personal folder.9.1.3 Enable the system (asiq) using the Wand.in.9.1.4 Log9.1.5 When the default screen appears, the user can choose New to start a new recipe, orLoad to load a previously saved recipe.9.1.6 Choose and enter various scan parameters, as described in Section 5.2.9.2 Scanning a Sample9.2.1 Bring the stage out towards the front using the controls to the left of the box.Note:Never manually move the stage, except to rotate it.Make sure that the stylus is safely recessed back, and that it is not visible on the screenimage. If not, press the UP arrow once to move the stylus back up. Open the door to thestage and place your wafer on the stage.9.2.2 The stage must be manually rotated to find your desired position. Adjust the zoom knobto the right of the stage if necessary.Note:The zoom should not be adjusted while the stylus is down, as it is easy to knock the stage or stylus when accessing the zoom control.9.2.3 Close the door. Use the stage control knobs to position your sample under the stylushousing.Click on the down arrow once to bring the stylus out from its shield. The message boxwill indicate Dropping Sensor. Then click and hold down the down arrow to bring thestage up and the stylus into contact with the sample, and wait until the stylus adjusts tothe center of the crosshairs on the screen. The message box will indicate Adjustingsensor. Click the up arrow once to bring the stylus out of contact with the sample.Note:Always retract the stylus before moving the stage or adjusting the zoom.Do not attempt to use the zoom function when the stylus is in contact withthe sample. In other words always lift the stylus from the sample (up key)when a measurement scan will not immediately follow.9.2.4 With the sample in position and the desired Scan parameters set, click on START toinitiate the scan. If you need to stop the scan at any point, you can click on STOP.Note:The preferred direction of a scan is shown in Figure 1.9.2.5 The stylus will first make a 400-µm back scan in order to have constant speed during onescan. Then, at the starting point, it will begin data collection.9.2.6 If you wish to save the current recipe, click the Save As button and save it to your ownfolder. Do not create any new folders on the computer.9.3 Data AnalysisAfter the scan, the profile is plotted on the screen with the summary of the data displayed next to it. The program automatically generates a report template, which can be viewed by clicking Data Review. There are various options for data analysis under the Operators menu, including digital noise filtering, erasing defects, and creating charts for presentations.9.3.1 Measuring Profile FeaturesThere are two options for measuring profile features: 2 Bars and 2 Zones. The 2 Barsoption displays two vertical lines that can be clicked on and dragged to any point on theprofile to apply any of the data analysis features to these points. Similarly, the 2 zonescan be manipulated by the user and moved to any point.9.3.2 LevelingIn order to level a plot, two points on the profile whose heights are equal are chosen.The program re-computes the measurement data to make these heights equal onthe display, and the rest of the profile is displayed relative to these points.Click on the leveling button to open the leveling window. There are different types ofleveling operations: Leveling using least Square Line, Min Zone Method, Using 2 Zones(Data Averaging), No Leveling, and Leveling using a polynomial of an order chosen bythe user.The most common method is the 2 Zone Leveling Method, where the two zones areplaced at points where the heights are equal, and the profile is reoriented relative tothese points.The leveling window shows both the original scan trace and the plot that results afterleveling is applied.9.3.3 ZoomThe zoom window allows the user to zoom in on part of the scan profile, or to view theentire profile.9.4 Logging OffTo log off, click on User, which will return to the login screen for the next user. Do not click onExit, which will shut down the whole system.9.5 Saving a file to the CD/RWPress the windows key on the keyboard. A windows menu will open. Then simply drag your fileover the CD drive.10.0 Troubleshooting Guidelines10.1 Occasionally the ASIQ computer software is known to “freeze”. Rebooting the computer typcallysolves this problem. To reboot, if possible press the Windows key on the keyboard and selectRESTART. If Windows key not functional simply press the restart key on the CPU. When theWindows software has rebooted click on the ASIQ icon.10.2 Occasionally the ASIQ stage is known to freeze. Rebooting the computer typcally solves thisproblem. To reboot press the Windows key on the keyboard and select RESTART. If Windowskey not functional simply press the restart key on the CPU. When the Windows software hasrebooted click on the ASIQ icon.11.0 Figures & SchematicsFigure 1Figure 2Figure 3AS200 Study Guide Be sure to know…1. Changing parameters from default menu.2. What part of the machine moves during a scan.3. Moving stylus from home position towards the sample.4. Measuring step height.5. Leveling a profile.6. Zooming in on a profile segment.7. Returning to viewing the entire profile.8. Zooming in on the sample image.9. Returning to previous magnification.10. How to logout.M. Wasilik - April 2003。

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A[0] = 4096 bytes A[1] = 460800 bytes //640*480*1.5 B[0] = 460800 bytes B[1] = 460800 * 3 bytes C[0] = 由video.nFrameWidth (初始為0)
video.nFrameHeight(初始為0)決定
pthread_create if
Constructor
pthread_create
BufferMgmtCallback()
OMX_AllocateBuffer()
Create
OMX_SendCommand(StateSet) StateIdle to StateExecution
fread() Read input file
(Buffer size後來可能會因為Port Reconfigure而改變)
IL Client
Dec A[1]
SendCommand(B, OMX_CommandStateSet, OMX_StateIdle)
SendCommand(A, OMX_CommandStateSet, OMX_StateIdle)
Color_cov B[0]
wait
wait signal
buffer allocation
A[1],B[0]指向同一塊buffer
openmaxStandPort: B[0]
Reuse-buffer
ppBufferHdr: A[1]的pInternalBufferStorage
nPortIndex: nTunneledPort = 0
pAppPrivate: NULL
nSizeBytes: Size of A[1] buffer
CallBacks()
OMX_GetParameter()
OMX_SetupTunnel()
OMX_SendCommand(StateSet) StateLoaded to StateIdle
Video_handle
Colorconv_handle
Message Handler
Fb_sin_handle
AllocateTunnelBuffer)
A[1],B[0]擁有相同大小的buffer Size = 460800 bytes
signal
A[1]::Buffer[]
Queue( )
EventHandler(A, OMX_CommandStateSet, OMX_StateIdle)
Read input to buffer
Buffer
EmptyThisBuffer()
BufferMgmtFunction
Input Buffer
OMX_SendCommand(StateSet) StateExecution to StateIdle
RTLAB Free
6
Setup Tunnel
RTLAB
7
ComponentTunnelRequest( * openmaxStandPort, hTunneledComp,
nTunneledPort , *pTunnelSetup)
If (port is Input Port eg.B[0] )
認定A[1]為自己的Supplier 認定自己為Non-supplier OMX_GetParameter(A[1],…) OMX_SetParameter(A[1],…)
Bellagio Data Processing Flow
清大資工 RTLAB 許宏榮
RTLAB
1
Outline
Bellagio Code Trace (Video)
Buffer Allocate and Management Data Flow Between Ports (Tunneled) Dynamic Port Reconfiguration
RTLAB
2
Bellagio Code Trace Buffer
RTLAB
3
架構
A = Video Decoder B= Color Converter C= Sink
Buffer Supplier: A[1] , B[1] ports
Buffer Non-Supplier: A[0] , B[0] , C[0] ports
pBuffer: Pointer to actual block oRfTmLAeBmory that is acting as the buffer 12
struct OMX_BUFFERHEADERTYPE
OMX_BUFFERHEADERTYPE** ppBufferHdr
RTLAB
13
Buffer Default Size
Else (A[1])
認定B[0]是Tunnel的另一端認定自己是Supplier
RTLAB
8
Tunneled Buffer Allocate (Load_State Idle_State)
RTLAB
9
State transition to Idle in the case of Tunneled Components
RTLAB
4
RTLAB
5
IL Client (application)
BOSA_InitComponentLoader
OMX_Init()
BOSA_CreateComponent
Loder Componts_1 Componts_2 Componts_3
. . . Componts_n
OMX_GetHandle()
EventHandler(B, OMX_CRomTm LAanBdStateSet, OMX_StateIdle)
10
Message_Handler::DoStateSet( ) Load to Idle
RTLAB
11
OMX_ERRORTYPE base_port_UseBuffer( omx_base_PortType *openmaxStandPort, OMX_BUFFERHEADERTYPE** ppBufferHdr, OMX_U32 nPortIndex, OMX_PTR , OMX_U32 nSizeBytes, OMX_U8 * pBuffer)