曼彻斯特编码的verilog实现

module bianma(din,rst,clk16x,clk96,start,tx,sr,state,clk_en,man);

input rst,clk16x,start;

input[7:0] din;

output tx,clk96,sr,state,clk_en,man;

reg clk_en;

reg[7:0] sr;

reg clk96;

reg tx,man;

reg[3:0] state;

reg[2:0] cnt;

always @(posedge clk16x)

begin cnt<=cnt+1;

if(cnt==7) clk96<=~clk96;

end

always @(negedge clk16x or negedge start or posedge rst)

begin if(rst) begin clk_en<=1'd0;end

else if(!start) begin clk_en<=1'b1;end

else if(state==4'd12) begin clk_en<=1'b0;end

end

always @(negedge clk96 or posedge rst)

begin if(rst) begin tx<=1'b1;sr<=8'b0;end

else if(state==4'd1) begin sr<=din;end

else if(state==4'd2) begin tx<=1'b0;end

else if((state>=4'd3)&&(state<=4'd10)) begin tx<=sr[0]; sr[6:0]<=sr[7:1];sr[7]<=1'b1;end

else if(state==4'd11) begin tx<=1'b1;end

else tx<=1'b1;

end

always begin if((state>=4'd3)&&(state<=4'd10))

begin man<=tx^clk96;end

else man<=1'b0;

end

always @(posedge clk96 or posedge rst or negedge clk_en)

begin if(rst) state<=4'b0000;

else if(!clk_en) state<=4'b0000;

else state<=state+1;

end

endmodule