8薄膜晶体管器件特性

大学本科必修课：《薄膜晶体管原理及应用》第8讲薄膜晶体管器件特性任课教师：董承远上海交通大学电子工程系2015‐4‐27薄膜晶体管的操作特性及机理Review: Output Characteristics of NMOSpReview: Transfer Characteristics of NMOSa ce e t ode Depletion ModeEnhancement Mode Depletion ModeQualitative Comparison BetweenNMOS & TFTsI‐V Characteristics of TFTsCh t i ti f TFTTransfer Characteristics of a-Si: H TFTs Output Characteristics of an a-Si TFTgy gReview：Energy Band Diagram of a‐Si:HWeak BondsWeak BondsDeep StatesCovalent BondsOperation p .)I d (A mRegionAbove‐ThresholdIn the above-threshold region, the Fermi-level goes into the※In the above threshold region the Fermi level goes into the conduction band tail due to the high positive gate voltage (V GS>V T);※The conduction band tail and its associated parameters such as n ti and v ti determine the characteristics of the TFT in the above-d d t i th h t i ti f th TFT i th b threshold regime of operation.Sub RegionForward ‐threshold SiN Si HSiN E CGate a ‐SiNx a ‐Si:H a ‐SiNx E V E FSE FM qV a※In the forward subthreshold region the Fermi-level is in the middle of the band gap close to its intrinsic level Thus the middle of the band gap close to its intrinsic level. Thus, the density of trapped electrons at the a-Si:H / insulator interfaces and deep states of the a-Si:H gap is higher than interfaces and deep states of the a Si:H gap is higher than other charge components.Reverse Sub‐thresholdRegion※A high density of interface states is present at the back interface, which leads to a high density of intrinsic electrons at this interface. This electron channel (back channel) id f d ti b t th d i d provides a means for conduction between the drain and source electrodes in the reverse substhtrehold region.Poole‐Frenkel Emission Region※The holes are generated as a result of the Poole-Frenkel field-enhanced thermionic emission at the gate-drain overlap region. The leakage current results by virtue of conduction through the reverse-biased diode at the draind ti th h th bi d di d t th d i overlap region, which is enhanced by the electric field.Off‐Current in a‐Si TFTsQ:What factors may influence the Poole Frenkel Effect Q: What factors may influence the Poole-Frenkel Effect in a-Si TFTs?Review: DOS in ‐SipOperation of p‐Si TFTs-The carrier density increases as the gate voltage is increased.The carrier density increases as the gate voltage is increased-The grain boundary potential decreases as the gate voltage or drain voltage are increased.p() Operation of p‐Si TFTs (cont.)Operation of p‐Si TFTs (cont.)p-At low V g and V d(low field, I off is low and varies almost linearly with the V d. -At higher field, I varies almost exponentially with V and exhibits a g,off p y gdependency only on the channel width. This suggests that carriers are being emitted from the drain space charge region.Operation of p‐Si TFTs (cont.)(a)Thermionic Emission (TE)(b)Field Emission (FE)()(c)Thermionic FieldEmission (TFE, or Poole-Frenkel Emission)F k l E i i)Operation of p‐Si TFTs (cont.)Short ‐Si Chanel Effect in p TFTsChanel Effect in p TFTs(cont) Short ‐Si (cont.)Chanel Effect in p TFTs (cont )N T VariationShort ‐Si (cont.)Chanel Effect in p TFTs(cont) Short ‐Si (cont.)Chanel Effect of p(cont) Short ‐Si TFTs (cont.)Short ‐Si (cont.) Chanel Effect in p TFTs(cont)Short Chanel Effect in p‐Si TFTs (cont.) Drain-Induced Grain Barrier Lowering Effects (DIGBL) Effect薄膜晶体管操作特性的简单物理模型Spice Models of NMOS Review:Level 1:Level1:Level 3:Review: ExampleSolution:Level 3:Level 1:Conclusion: Obviously the drain current is significantly overestimated by Level 1 model.of TFTsModeling Directly modeling TFTs’ above threshold region with MOSFET Level 1of TFTs(cont)Modeling (cont.)•There exist two different points in the operational essence betweenTFTs and MOSFETs:‐TFTs operate at accumulation statel ipwhile MOFETs operate at inversion mode.‐TFTs possess much localized states inth i ti l hil htheir active layers while MOSFET have “ cleaner” energy band structure.Modeling of TFTs (cont.)gModeling of TFTs (cont.)Modeling of TFTs (cont.)of TFTs(cont) Modeling (cont.) Modeling TFTs with Square-law Modelof TFTs(cont)Modeling (cont.)Q: Please identify the linear region and saturation region in the above graphs.the above graphsExercise•An a‐Si TFT was fabricated and measured in our lab. are lab The channel thickness/length100nm/4um ; the initial electron density in a‐Si is 16cm‐3and the field effect mobility is i10d th fi ld ff t bilit i1cm2/V ∙ s. The thickness and the dielectricconstant of gate insulator is 300nm and 7.5p y y p respectively. Permittivity of free spaceε0=8.85 ×10‐14F/cm and the electron chargeis 1.6 ×10 C. If the ds becomes ×10A16‐19C I5‐6 with V gs=10 V and V ds=5 V, please find the channel width value in this device.h l idth l Z i thi d iContact Resistance in TFTs-The specific contact resistances between the source/drain metal electrodes and the n+ a-Si:H layers;-The resistances of n+ a-Si:H film;-The resistances due to the intrinsic a-Si:H layers between the source/ drain n+ a-Si:H layers./d i+Si H lContact Resistance in TFTs (cont.)The experimental relation between R f(in Ω-cm) and RC (in Ω-cm2) for Mo/n+a-Si:H contacts can be described by a Si:H contacts can be described byResistance in TFTs(cont) Contact (cont.)Contact Resistance in TFTs (cont.)Modeling ofTFTswithR c Incluedof TFTs(cont)Modeling (cont.)•MOSFET Level 1 (Square‐law Model) is the simplest physical model of TFTs andeasily dealt with hand calculations.•MOSFET LEVEL 1 can only model TFTs in ‐region with relatively above threshold lower accuracy.非晶硅薄膜晶体管的精确物理模型Modeling ‐Si TFTs (cont.)of a(cont)Field Effect Mobility yModeling ‐Si TFTs (cont.)of a(cont)。