电子科技大学数字设计原理与实践试题(200607期末英文A)

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电子科技大学二零零五至二零零六学年第二学期期末考试

数字逻辑设计及应用课程考试题英文A卷（120分钟）考试形式：闭卷考试日期2006年7月4日

课程成绩构成：平时20 分，期中20 分，实验0 分，期末60 分

1)Fill a vacancy problems (1‟×10)

1. An unused CMOS NAND input should be tied to logic ( ) level or ( ).

2. If an EPROM‟s capacity is 512K ×8 bits, the address inputs should be ( ) bits.

3. A 4

512⨯EPROM can be take as a memory truth table with ( ) inputs and ( ) outputs.

4. In CMOS gates circuits, the series NMOS can realize ( ) operation, the PMOS together with the NMOS should be connected in ( ).

5. A binary signed-magnitude is ( 001101)2,then its corresponding 8-bit two‟s complement is ( ) 2.

6. The function of a DAC is translating the ( ) inputs to the same value of ( ) outputs.

2)Judgement problems (1‟×5)

1. ( ) It must be a combinational logic circuit that only consists of logic gates such as NAND gates, etc.

2. ( ) We need 4 chips of 1K ⨯ 4 bits RAM to form a 4 K ⨯ 8 bits RAM.

3. ( ) The RCO of the 74x163 is asserted only when all of the count bits are 1 and both ENP and ENT are asserted.

4. ( ) The result is “1” when one of “1” XNOR with the result of 1001 of “0” XNOR.

5. ( ) If AC

B=.

AB=，then C

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3)(A) Simplifying the logic function expression BC

='

'（5‟）

+

AB

BC

A

F+

(B) The logic function expression is F=W+XZ+XY，please write out its corresponding mintern list

expression:

F=ΣWXYZ( ) (3’)

4)The combinational logic circuit is as the following figure, the questions are:

(1)Write out the circuit output logic function expression Y; (4‟)

(2)Analyze the circuit, when the hazard may occur according to the inputs, and judge what kind

of hazards they are? (4‟)

(3)Please eliminate the hazards by adding an extra terms, and write out the hazard-free output logic

function expression Y. (4‟)

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5) Design a multi-function combinational logic circuit, which should realize the logic function in table 1.

M 1 and M 0 are the function selection signals, A and B are inputs, F is output. Please realize the circuit with an 8-input, 1-bit multiplexer (74x151) and some necessary logic gates. The selection signal should be CBA=M 1M 0A. （Note ：⊕is XOR ，⊙ is XNOR ）. （10’）

Table 1

6) The state/output table is as the following, please design the circuit with D flip-flops according to the

state assignment, and draw the circuit diagram.

a) Write out the transition/output table and the excitation /output table. (7‟) b) Write out the excitation equations 、output equation. (8‟) c) draw the circuit diagram. (5‟)

state/output table ： state assignment ：

S X 0 1 A A ，1 C ，0 B C ，0 A ，0 C B ，0 D ，0 D A ，1

B ，0

S*，Z

S Q1 Q2 A 0 1 B 1 1 C 0 0 D 1 0