51单片机简介外文翻译

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外文翻译--AT89C51单片机的介绍

专业文献翻译题目: AT89C51单片机的介绍姓名:学院:专业: 电子信息科学与技术班级: 班学号:指导教师: 职称:20 年月日原文：The Introduction of AT89C51DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a full duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexed address/data bus during accesses to external program and data memory. In this mode P0 has internal Pull-up resistor. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during Program verification. External Pull-up resistors are required during Program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal Pull-up resistors. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal Pull-up resistors and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal Pull-up resistors. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current, because of the internal Pull-up resistor. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal Pull-up resistor when emitting 1s. During accesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3 is an 8-bit bi-directional I/O port with internal Pull-up resistor. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal Pull-up resistor and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the Pull-up resistor. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bitset, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum andmaximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit frompower-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.译文：AT89C51的介绍描述AT89C51是一个低电压，高性能CMOS 8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。

51单片机英文及其翻译

英文翻译原文：51 Microcontroller IntroductionMicrocontrollers basic component is a central processing unit (CPU in the computing device and controller), read-only memory (usually expressed as a ROM), read-write memory (also known as Random Access Memory MRAM is usually expressed as a RAM) , input / output port (also divided into parallel port and serial port, expressed as I / O port), and so composed. In fact there is also a clock circuit microcontroller, so that during operation and control of the microcontroller, can rhythmic manner. In addition, there are so-called "break system", the system is a "janitor" role, when the microcontroller control object parameters that need to be intervention to reach a particular state, can after this "janitor" communicated to the CPU, so that CPU priorities of the external events to take appropriate counter-measures.Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, but not ideal because the cost has not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been therapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90s dedicated processor, while the average model prices fall to one U.S. dollar, the most high-end model is only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems.SCM relies on the program, and can be modified. Through different procedures to achieve different functions, in particular special unique features, this is another device much effort needs to be done, some are great efforts are very difficult to achieve. A not very complex functions if the 50's with the United States developed 74 series, or the 60's CD4000 series of these pure hardware buttoned, then the circuit must be a large PCB board! But if the United States if the 70's with a series of successful SCM market, the result will be a drastic change! Just because you are prepared by microcomputer programs can achieve high intelligence, high efficiency and high reliability!IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financiallyProhibitive. Redesign costs can run as high as a $500K, much more if the fix means back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components are extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides postSilicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.The AT89C51 provides the following standard features: 4Kbytes of flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, five vector two-level interrupt architecture, a full duple ser -ail port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the social -labor disabling all other chip functions until the next hardware reset.Pin DescriptionVCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed lowered address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups’.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urge four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI); Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/soul -race four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dui -nag each access to external DataMemory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. A should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, andThe next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved byobserving that their features are enabled.A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps.An analog-to-digital converter (ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself.Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for a digital-to-analog converter (DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned (usually amplified) to a form suitable for operating an actuator.The signals used within microcomputer circuits are almost always too small to be connected directly to the “outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator.To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. T hese hardware devices, called peripherals, are the CPU’s window t o the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions.Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.Its applicationsSCM is widely used in instruments and meters, household appliances, medical equipment, aerospace, specialized equipment, intelligent management and process control fields, roughly divided into the following several areas:SCM has a small size, low power consumption, controlling function, expansion flexibility, the advantages of miniaturization and ease of use, widely used instrument, combining different types of sensors can be realized, such as voltage, power, frequency, humidity, temperature, flow, speed, thickness, angle, length, hardness, elemental, physical pressure measurement. SCM makes use of digital instruments, intelligence, miniaturization, and functionality than the use of more powerful electronic or digital circuits. Such as precision measuring equipment (power meter, oscilloscope, various analytical instrument).译文：51单片机简介单片机的基本组成是由中央处理器（即CPU中的运算器和控制器）、只读存贮器（通常表示为ROM）、读写存贮器（又称随机存贮器通常表示为RAM）、输入/输出口（又分为并行口和串行口，表示为I/O口）等等组成。

AT89C51单片机毕业论文外文翻译

附录A功能概述AT89C51单片机是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4k bytes的可反复擦写的Flash只读程序存储器和128 bytes的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS—51指令系统，片内置通用8位中央处理器（CPU）和Flash存储单元，功能强大AT89C51单片机可提供许多高性价比的应用场合，可灵活应用于各种控制领域。

主要性能参数与MCS—51产品指令系统完全兼容4k字节可重擦写Flash闪速存储器1000次擦写周期全静态操作：0Hz—24MHz三级加密程序存储器128×8字节内部RAM32个可编程I/O口线2个16位定时/计数器6个中断源可编程串行UART通道低功耗空闲和掉电模式引脚功能说明VCC：电源电压GND：地P0口：P0口是一级8位漏极开路型双向I/O口，也即地址/数据总线复用口。

作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口写“1” 可作为高阻搞输入端用。

在访问外部数据存储器或程序存储器时，这级口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。

在Flash编程时，P0口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外妆上拉电阻。

P1口：P1口是一个带内部上拉电阻的8位双向I/O口，P1口的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。

对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流。

Flash编程和程序校验期间，P1接收低8位地址。

P2口：P2口是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。

文献翻译-51系列单片机的结构和功能

Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have ,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computer .An one-chip computer system is made up of several following parts:(1) One microprocessor of 8 (CPU).(2) At slice data memory RAM (128B/256B),it used to depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc.(3)Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc..(4)Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too.(5)Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer.(6)Five cut off cutting off the control system of the source .(7)One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter(UART)), is it realize one-chip computer or one-chip computer and serial communication of computer to use for.(8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller, etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarily of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transferstation of data transmission on 8051 inside .The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter ,the order is deposited, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out .Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unisonoutside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC, visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction, but four function of pass way these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingThe circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouths, its output grade draws the resistance supreme. When using it as the mouth in common use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write "1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used asI/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together :One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast ;When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the resistance on needn't answer and then. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1. P3 mouth one multi-functional port, mouth getting many than P1 it have "and " 3 door and 4 buffer". Two part these, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and " door 3 function one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W =At 1 o'clock, output Q end signal; Act as Q =At 1 o'clock, can output W line signal . At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance . It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location (the location or the byte) to visit to P3 mouth /at not lasting lining, there are inside hardware latch Qs =1.The operation principle of P3 mouth is similar to P1 mouth.Output grade, P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outer . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally ,as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high leveleffective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal。

完整word版,51单片机英文及其翻译

51单片机外文翻译

Proceedings of the 2007 Computer Science and IT Education ConferenceDevelopment of a Microcontroller Based Robotic ArmJegede Olawale, Awodele Oludele, Ajayi Ayodele,and Ndong Miko AlejandroBabcock University, Ilisan- Remo, Nigeriajegede1@; delealways@zeebaby05@; alejandro_mico@AbstractRobotic arm has become popular in the world of robotics. The essential part of the robotic arm isa programmable microcontroller based brick capable of driving basically three stepper motors design to form an anthropomorphic structure. The first design was for experimental use on a human-size industrial robot arm called PUMA 560 used to explore issues in versatile object handling and compliance control in grasp actions (Bejczy & Jau, 1986). This paper explains the method of interfacing the robotic arm stepper motors with the programmed 8051-based microcontrollerwhich are used to control the robot operations. We have employed the assembly languagein programming our microcontroller. A sample robot which can grab (by magnetizing) and release small objects (by demagnetizing) is built for demonstrating the method explained. Keywords: MCU, PUMA, PIO, LATCH, I/OIntroductionBackgroundTaking a look back at the history of robot development, a special kind of human-size industrialrobotic arm called Programmable Universal Machine for Assembly (PUMA) came into existence.This type of robot is often termed anthropomorphic because of the similarities between its structureand the human arm. The individual joints are named after their human-arm counterparts. “Itis worth noting that in our work, the hand is magnetic and not a generalized manipulator. In theproper sense of the word, manipulation is the function of the arm. The function of the arm is toposition and orient the hand, act as a mechanical connection and power and sensingtransmissionlink between the hand and the main body of the person. The full functional meaning of the armrests in the hand” (Bejczy & Jau, 1986). Our work provides i mportant elements that are requiredto build a simple robotic arm of very high quality. As stated earlier we are making use of the 8051-based microcontroller.The 8051‟s instruction set is optimizedfor one-bit operations that are often desiredin real world, real time operations.(Pont, 2002).ObjectiveThe primary objective is to make theRobotic arm, which comprises of threestepper motors, to interface with the In-Material published as part of this publication, either on-line orin print, is copyrighted by the Informing Science Institute.Permission to make digital or paper copy of part or all of theseworks for personal or classroom use is granted without feeprovided that the copies are not made or distributed for profitor commercial advantage AND that copies 1) bear this noticein full and 2) give the full citation on the first page. It is permissibleto abstract these works so long as credit is given. Tocopy in all other cases or to republish or to post on a server orto redistribute to lists requires specific permission and paymentof a fee. Contact Publisher@ to requestredistribution permission.Development of a Microcontroller Based Robotic Arm550tel 8051-based micro-controller. It provides more interfaces to the outside world and has largermemory to store many programs.ScopeThe scope of this work involves confirming the 8051 micro-controller Input/Output (I/O) signalsare compatible with that of the robotic arm stepper motors and testing of the robot‟s motor signalsthrough programming the 8051 microcontroller. Assembly programming is used to develop the programs for the EPROM 2732 on the 8051 micro-controller platform that takes robot‟s motorsignal as I/O and controls the robot operation programmatically.We have assumed that after figuring out the interface issues for the Robot with the 8051microcontroller,the same knowledge can be extended to make very complex robots with enhanced functionality.ApproachWe were able to perform a detailed study of the robotic arm and the 8051 micro-controller. Wetested the built robotic arm, and the stepper motors when the robot is loaded. We also learnt andfamiliarized with the 8051 micro-controller using assembly language, and converting the assemblylanguage codes to hexadecimal codes using a development board.RoboticsThe word …robotics’, meaning the study of robots was coined by Isaac Asimov. Robotics involveselements of both mechanical and electrical engineering, as well as control theory, computing andnow artificial intelligence (Selig, 1992). According to the Robot Institute of America, “A robot isa reprogrammable, multifunctional manipulator designed to move materials, parts, tools or specializeddevices through variable programmed motions for the performance of a variety of tasks”(Robotics Research Group, n.d.)The fact that a robot can be reprogrammed is important: it is definitely a characteristic of robots.In order to perform any useful task the robot must interface with the environment, which may comprise feeding devices, other robots, andmost importantly people.Mechanical Structure of theArmIn constructing our arm, we made use of threestepper motors and gears since our structure isa three dimensional structure. A typical prototypethat we employed is as shown in Figure 1.There is a stepper motor at the base, whichallows for circular movement of the wholestructure; another at the shoulder which allowsfor upward and downward movement of thearm; while the last stepper motor at the wristallows for the picking of objects by the magnetichand.Figure 1. Anthropomorphic Type ofRobot Design (Selig, 1992, p.29)Jegede, Awodele, Ajayi, & Miko551Micro-ControllerA microcontroller is an entire computer manufactured on a single chip. Microcontrollers are usuallydedicated devices embedded within an application e.g. as engine controllers in automobiles and as exposure and focus controllers in cameras. In order to serve these applications, they have ahigh concentration of on-chip facilities such as serial ports, parallel input/output ports, timers,counters, interrupt control, analog-to-digital converters, random access memory, read only memory, etc. The I/O, memory, and on-chip peripherals of a microcontroller are selected dependingon the specifics of the target application. Since microcontrollers are powerful digital processors,the degree of control and programmability they provide significantly enhances the effectivenessof the application.Embedded control applications also distinguish the microcontroller from its relative, the generalpurposemicroprocessor. Embedded systems often require real-time operation and multitasking capabilities. Real-time operation refers to the fact that the embedded controller must be able toreceive and process the signals from its environment as they are received. Multitasking is the capabilityto perform many functions in a simultaneous or quasi-simultaneous manner (Yeralan, S.& Emery, 2000, p. 2).Figure 2. Block diagrams of a Microcontroller (microElectronika, 2004)The various components of the MCU shown in Figure 2 are explained below:Random Access Memory (RAM): RAM is used for temporary storage of data during runtime. ROM: ROM is the memory which stores the program to be executed.SFR Registers: Special Function Registers are special elements of RAM.Program Counter: This is the "engine" which starts the program and points to the memory address of the instruction to be executed. Immediately upon its execution, value ofcounter increments by 1.Development of a Microcontroller Based Robotic Arm552Control Logic: As the name implies, it which supervises and controls every aspect of operationswithin MCU, and it cannot be manipulated. It comprises several parts, the mostimportant ones including: instructions decoder, Arithmetical Logic Unit (ALU) andAccumulator.A/D Converter: A/D stands for analog to digital. They convert analog signals to digital signals.I/O Ports: To be of any practical use, microcontrollers have ports which are connected to the pins on its case. Every pin can be designated as either input or output to suit user's needs.Oscillator: This is the rhythm section of the MCU. The stable pace provided by this instrumentallows harmonious and synchronous functioning of all other parts of MCU.Timers: timers can be used for measuring time between two occurrences and can also behave like a counter. The Watchdog Timer resets the MCU every time it overflows, and the program execution starts anew (much as if the power had just been turned on). Power Supply Circuit: this powers the MCU. (MikroElectronika, 2004).MethodologyThe method employed in designing and constructing the robotic arm are based on the operationalcharacteristics and features of the microcontrollers, stepper motors, the electronic circuit diagramand most importantly the programming of the microcontroller and stepper motors. Block DiagramThe block diagram of our work is as shown in Figure 3.Figure 3. Block diagramCONTROLUNIT[MCU]KEYPADMOTORSMAGNETICSENSORSSensor driver(transistor)Motor driver(transistors)POWERSUPPLYUNITJegede, Awodele, Ajayi, & Miko553Circuit DiagramThe electronic circuit diagram of the development board is as shown in Figure 4. The connectionof the identified components and devices are as shown. The components shown are: the MCU, theLATCH 74LS373, the EPROM 2732, Intel 8255 PIO, diodes, resistors, capacitors, inductors, transistors, and op-amps. This components work together to achieve the set goal of controllingthe anthropomorphic-like arrangement of the stepper motor. The microcontroller is the processingdevice that coordinates all the activities of all the components for proper functioning. Power SupplyThis is used to power the whole system i.e. the Control Unit, Magnetic Sensing Unit, and the Stepper Motors. The transformer is a 220/12V step down transformer. We used a bridge rectifierto convert the 12V alternating current to direct current.The unregulated output from the filtering circuit is fed into a voltage regulator LM7805 and LM7812. These two are chosen for the design because the LM7805 has an output of +5V whichis required to power the Control Unit, and the Magnetic Coil while the LM7812 has an output of+12v which is required to power the Stepper motors.The TIP41 connected to the IC regulators functions as an emitter follower amplifier making surethat at least the required voltage by the Control Unit, the Magnetic Coil and the Stepper Motorsproduced.MCU 8051This is the processor. It coordinates the operation of the robotic arm by collecting information from the EPROM, the LATCH, and the PIO; interprets and then execute the instructions. It is theheart of the whole system.LATCH 74LS373This is a D-type transparent latch. It is an 8 bit register that has 3 state bus driving outputs,fullparallel access for loading, and buffer control inputs. It is transparent because when the enableEN(enable) input is high, the output will look exactly like the D input. This latch particularly separates the data and address information from the MCU before sending to the instructed destination.The high-impedance state and increased high logic-level drive provide these registerswith the capability of being connected directly to and driving the bus lines in a bus-organized systemwithout need for interface or pull-up components. These latches are particularly attractive forimplementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.We are using this latch because there is a need to separate our 8 bit data and 8 bit address informationfrom the common line of the MCU, and send them to the appropriate device(s).8255 PIOThis is a programmable input/output device. It interfaces the connection between the 8051, theLATCH 74LS373, and the EPROM 2732 to external devices such as the stepper motors, (as is our own case) thereby allowing for communication.(EPROM) 2732EPROM stands for Electrically Programmable Read Only Memory. We made use of this externalEPROM specifically because it makes the controller cheaper, allows for longer programs, and because its content can be changed during run time and can also be saved after the power is off.Development of a Microcontroller Based Robotic Arm554Figure 4. Control Unit(Digitouch, 2006)The overall diagrammatical layout of the complete circuit diagram of the whole control unit is shown in Figure 4.Stepper MotorThe stepping motor is a motor that is driven and controlled by an electrical pulse train generatedby the MCU (or other digital device). Each pulse drives the stepping motor by a fraction of onerevolution, called the step angle.Jegede, Awodele, Ajayi, & Miko555The Magnetic Sensing UnitThe magnetic sensing unit consists of a magnetic coil which can be magnetized simply by the action of the port P1.0 of the 8051. The port 1.0 was made use of because when designated as output, each of the pin can be connected up to four TTL inputs. That is why we have connectedthe pin 1.0 to the magnetic coil through three TTL logic.The design is such that on the downward movement of the wrist, the 8051 sends an electrical signalto the Darlington pair connected to the magnetic coil.The magnetic sensing unit is powered on by three BC548 Darlington NPN pair transistor, througha diode each and a 5k resistor. The pair amplifies the current and makes the magnetic coil turn into magnet. Then any magnetic material could be picked (by attraction) and then movement continues.The magnetic material can then be dropped at another point when the wrist is made tocome down, this also is an action from the 8051 as it withdraws the electrical signal from the coil.Control CircuitThis is the control panel of the system as it oversees the operations of the mechanical arm, andthe magnetic sensing unit. The MCU 8051 of the control unit acts as the brain of the control panelas it coordinates all the activities of the other devices. When power (+5V) was supplied to the control unit, the MCU started off by loading the program from the EPROM M2732A, interpretedand executed the instruction codes through the various operational principles which had been describedin details in chapter three (session 3.2).The 8051 then sends signal to the stepper motor which moves 9° per step. The stepper motor (M3) at the wrist first moves five times (45°) turning the gears to cause a downward movement ofthe hand. The stepper motor at the shoulder (M2) moves next stepping five times (45°) and makesthe connected gears to cause the movement of the arm 45° forward. Then the stepper motor at thebase(M1) moves either ten times (90°) or twenty times (180°), depending on the button pressed,causing the whole structure to turn from right to left( or vice versa) through the connected gears.The magnetic coil resting on the hand becomes magnetized immediately the last gear on the handstops moving. Then, it magnetizes (picks) any magnetic material it can find and then M3 and M2moves the arm up while M1 moves (rotates the structure) from left to right (or vice versa) and then the 8051 demagnetizes the magnetic coil thereby making the hand to drop the metallic object.ResultsThis work is able to successfully accomplish the defined functionality. A sample robot which canrotate, magnetize an object, lower and raise its arm, by being controlled by the 8051 microcontrolleris built successfully. The 8051-development board is soldered and it used the required procedurefor the correct operation of the controller. The 8051 development board has been interfaced to the stepper motors such that the anthropomorphic like structure can be controlled fromthe buttons at the base of the structure (robotic arm).There are four buttons being controlled by the control unit at the base of the arm:•ON/OFF: the ON button puts on the system while the OFF button puts off the system •START/STOP: the START button starts the movement of the whole arm from its reset point, while the STOP button takes the arm back to its reset button after completion of its movement.Development of a Microcontroller Based Robotic Arm556•RIGHT-LEFT/LEFT-RIGHT: when this button is switched to the RIGHT-LEFT part it causes movement from right to left, while the LEFT-RIGHT part causes movement fromleft to right.•180/90: when the button is on 180, it causes a rotation of 180 degree of the base stepper motor, but when put on 90 degrees, it causes rotation of 90 degrees.ConclusionIn this paper we have interfaced the robot with different kinds of I/O devices and our method allowsfor storing more programs to enhance more functionality. From our work, we deduced thatin comparison to humans, robots can be much stronger and are therefore able to lift heavier weights and exert larger forces. They can be very precise in their movements, reduce labor costs,improve working conditions, reduce material wastage and improve product quality (Mair, 1988).This i s why they‟re very important in industries because the overall objective of industrial engineeringis productivity (Hicks, 1994, p. 61).Meanwhile, intelligent Control is the discipline that implements Intelligent Machines (IMs) to perform anthropormorphic tasks with minimum supervision and interaction with a human operator.This project can be further enhanced to as a multi-disciplinary project involving electrical and computer engineers to work together to create more complex, intelligent robots controlled by the8051 micro-controller.ReferencesBejczy, A. K., & Jau, B. M. (1986). Smart hand systems for robotics and teleoperation. Proceedings of theSixth CISM-IFToMM Symposium on Theory and Practise of Robots and Manipulators, Hermes Publishing.Engelberger, J. F. (1989). Robotics in service (pp 224-226). Kogan Page.Hall, D. V. (2004). Microprocessors and interfacing, Programming and hardware (pp 278-279). McGrawHill.Hicks, P. E. (1994). Industrial engineering and management. McGraw-Hill.Mair, G. M. (1988). Industrial robotics. Prentice Hall.microElectronika. (2004). Architecture and programming of 8051 MCU (Chapter 1).Pont, M. J. (2002). Embedded C. Addison-Wesley.Robotics Research Group. (n.d.). Learn More History. Retrieved from/rrg/learn_more/history/Selig, J. M. (1992). Introductory robotics. Prentice Hall.Valavanis, K. P., & Saridis, G. N. (1992). Intelligent robotics. Academic Publishers.Yeralan, S., & Emery, H. (2000). Programming and interfacing the 8051 microcontroller in C and Assembly.Rigel Press.。

外文翻译---51系列单片机的结构和功能

外文翻译---51系列单片机的结构和功能外文资料翻译英文原文：Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers .An one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). (2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. (4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction, may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command center, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing devices temporarily of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a expresses in the order. The controller includes the procedure counter, the order is deposited, theorder decipher , the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read) and RAM in 8051 slices (data memory, can is it can write) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether.Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction , but four function of way these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharingOutput grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing auto. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer millimeter of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal:Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output, Schmitt of trigger constantly in each S5P2, machine of cycle in having one more, then just got and restored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with theoscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.中文译文：51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。

51单片机中的英文缩写全称(整理)

51单片机中的英文缩写全称(整理) 51单片机中的英文缩写全称(整理)单片机（Microcontroller）是一种集成了处理器、内存、输入/输出设备以及时钟等功能的微型计算机系统。

在单片机领域中，英文缩写广泛应用，方便人们对各种电子元器件、芯片和技术进行简洁明了的表达。

本文将整理51单片机中常见的英文缩写全称，方便读者了解和使用。

一、基本概念与组成1. MCU - Microcontroller Unit（单片机单元）：指一种完整、独立的微型计算机系统，由中央处理器（CPU）、内存（RAM、ROM）、输入/输出（I/O）接口和时钟等组件组成。

2. CPU - Central Processing Unit（中央处理器）：执行单片机数据处理、逻辑控制和运算等核心功能的部件。

3. RAM - Random Access Memory（随机存取存储器）：用于临时存储程序和数据的存储器，读写速度快但容量较小。

4. ROM - Read-Only Memory（只读存储器）：存储固定程序和数据，无法进行写操作。

5. I/O - Input/Output（输入/输出）：与单片机外部设备进行数据交互的接口。

6. Clock - 时钟：提供单片机工作所需的时序信号，控制指令执行和数据传输的节奏。

二、核心技术与模块1. ISP - In-System Programming（系统编程）：通过特定的下载器将程序和数据下载到单片机内部，实现在线编程。

2. UART - Universal Asynchronous Receiver/Transmitter（通用异步收发器）：用于实现串行通信的接口。

3. ADC - Analog-to-Digital Converter（模数转换器）：将模拟信号转换为相应的数字量。

4. PWM - Pulse Width Modulation（脉宽调制）：通过改变信号的脉宽来控制电气或电子设备的输出功率。

51单片机简介Brief-introduction-of51MCU大学毕业论文外文文献翻译及原文

毕业设计（论文）外文文献翻译文献、资料中文题目：51单片机简介文献、资料英文题目：Brief introduction of 51 MCU 文献、资料来源：文献、资料发表（出版）日期：院（部）：专业：班级：姓名：学号：指导教师：翻译日期： 2017.02.14Brief introduction of 51 MCUDescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Function characteristicThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC：Supply voltage.GND：Ground.Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during programverification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current, because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. In this application, it uses strong internal pullupswhen emitting 1s. Duringaccesses to external data memory that use 8-bit addresses, Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped toVCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1.Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Figure 1. Oscillator Connections Figure 2. External Clock Drive ConfigurationIdle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. Themode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.外文翻译：51单片机简介描述A T89C51是一个低电压，高性能CMOS8位单片机带有4K字节的可反复擦写的程序存储器（PENROM）。

(完整word版)51单片机外文翻译

Structure and function of the MCS-51 seriesStructure and function of the MCS—51 series one-chip computer is a name of a piece of one-chip computer series which Intel Company produces。

This company introduced 8 top—grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS—48 series in 1976. It belong to a lot of kinds this line of one—chip computer the chips have,such as 8051， 8031， 8751,80C51BH， 80C31BH,etc。

， their basic composition, basic performance and instruction system are all the same。

8051 daily representatives- 51 serial one—chip computers .An one-chip computer system is made up of several following parts：（ 1) One microprocessor of 8 （CPU)。

（ 2） At slice data memory RAM （128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show， etc。

51单片机缩写的英文全称及中文名称

单片机缩写的英文全称及中文名称PC = programmer counter //程序计数器counter 计算器, 计数器, 计算者, 柜台, 筹码['kauntə]ACC = accumulate [ə'kju:mjuleit //累加器: 积累: 积聚PSW = programmer status word //程序状态字status'steitəs, 'stæ-]n. 地位；状态；情形；重要身分SP = stack point //堆栈指针stack[stæk n. 堆；堆叠vt. 使堆叠；把…堆积起来vi. 堆积，堆叠DPTR = data point register //数据指针寄存器'redʒistə寄存器IP = interrupt priority //中断优先级[,intə'rʌpt 中断[prai'ɔrəti] 优先；优先权；[数] 优先次序；优先考虑的事IE = interrupt enable // 中断使能i'neibl]使能够，使成为可能；授予权利或方法TMOD = timer mode // 定时器方式(定时器/计数器控制寄存器) ['taimə定时器，计时器mode [məud模式，方式ALE = alter (变更,可能是)['ɔ:ltə]PSEN = programmer saving enable //程序存储器使能(选择外部程序存储器的意思) EA = enable all(允许所有中断)完整应该是enable all interruptPROG = programme (程序)SFR = special funtion register //特殊功能寄存器TCON = timer control //定时器控制PCON = power control //电源控制MSB = most significant bit//最高有效位[sig'nifikənt有效的；有意义的LSB = last significant bit//最低有效位CY = carry //进位（标志）['kæri]AC = assistant carry //辅助进位[ə'sistənt n. 助手，助理，助教adj. 辅助的，助理的；有帮助的OV = overflow //溢出[,əuvə'fləu, 'əuvəfləu ORG = originally[ə'ridʒənəli //起始来源DB = define [di'fain]定义byte [bait] //字节定义EQU = equal //等于['i:kwəl]DW = define word //字定义 E = enable //使能OE = output enable //输出使能RD = read //读WR = write //写中断部分：INT0 = interrupt 0 //中断0 INT1 = interrupt 1//中断1T0 = timer 0 //定时器0 T1 = timer 1 //定时器1TF1 = timer1 flag //定时器1 标志(其实是定时器1中断标志位) [flæɡvi. 标记；衰退；枯萎vt. 标记；插旗n. 标志；旗子IE1 = interrupt exterior //(外部中断请求,可能是) ik'stiəriə]外部的IT1 = interrupt touch //(外部中断触发方式,可能是)ES = enable serial //串行使能['siəriəl, 'si:r- adj. 连续的；连载的；分期偿还的n. 电视连续剧；[图情] 期刊；连载小说serial communication [计]串行通信serial port [计]串行端口；序列埠serial interface [计]串联接口ET = enable timer //定时器使能PS = priority serial //串口优先级EX = enable exterior //外部使能(中断)[ik'stiəriə] adj. 外部的；表面的；外在的n. 外部；表面；外型；外貌PX = priority exterior //外部中断优先级PT = priority timer //定时器优先级寄存器部分:SFR:special funtion register //特殊功能寄存器(片内RAM 80H~FFH)ACC:accumulate //累加器SP:stack point //堆栈指针PSW:programmer status word //程序状态字IE:interrupt enable // 中断使能DPL,DPH:DPTR(data point register //数据指针寄存器)的低8位和高8位IP:interrupt priority //中断优先级PCON:power control //电源控制SCON:serial control //串行口控制TCON:timer control //定时器控制SBUF:serial buffer //串行数据缓冲['bʌfə] n. [计] 缓冲区；缓冲器，[车辆] 减震器vt. 缓冲TMOD:timer mode //定时器方式PSW:CY:carry (psw.7) //进位（标志）AC:auxiliary carry (psw.6) //辅助进位F0: (psw.5) //用户自定义标志位OV:overflow (psw.2) //溢出RS1,RS0:register select (psw.4,psw.3)//工作寄存器组选择位[si'lekt]挑选P:parity (psw.0) //奇偶校验位['pæriti. 平价；同等；相等IE:EA:Enable All Interrupt /CPU开/关中断控制位ET1:Enable Timer //定时器2溢出中断允许位ES:Enable Serial Port //串行口中断允许位EX:Enable External //外部中断1的中断允许位IP:PS:Priority Serial //串口优先级PT:Priority Timer //定时器优先级PX:Priority External //外部中断优先级[ik'stə:nəl] adj. 外部的；表面的；[药] 外用的；外国的；外面的n. 外部；外观；外面SCON:RI:Receive Interrupt //串行口接收中断请求标志位TI:Transmit Interrupt //串行口发送中断请求标志位[trænz'mit, træns-, trɑ:n-] vt. 传输；传播；发射；传达；遗传vi. 传输；发射信号TCON:TF1:Timer1 Overflow Flag //定时器1溢出中断请求标志TR1:Timer1 Run //定时器1启动控制位IE1:Interrupt Edge //外部中断1请求标志位[edʒ]IT1:Interrupt Type //外部中断1触发方式选择位8051引脚:RST:RESET (9)//复位，重启P3:RXD:Received eXchange [iks'tʃeindʒ Data (10,p3.0)//接收串行数据eXchange n. 交换；交流；交易所；兑换vt. 交换；交易；兑换vi. 交换；交易；兑换TXD:Transmit eXchange Data (11,p3.1)//发送串行数据INT0:interrupt 0 (12,p3.2)//中断0 INT1:interrupt 1 (13,p3.3)//中断1T0:timer 0 (14,p3.4)//定时器0 T1:timer 1 (15,p3.5)//定时器1RD：ReaD (16,p3.6)//外部数据存储器(RAM)的读信号WR：WRite (17,p3.7)//外部数据存储器(RAM)的写信号XTAL2,XTAL1:External Crystal ['kristəl晶体Oscillator ['ɔsileitə振荡器(18,19) //外部晶体振荡器PSEN:Program Store [stɔ:]Enable (29) //程序存储器(ROM)使能n. 商店；储备，贮藏；仓库vt. 贮藏，储存ALE:Address Latch Enable (30) //地址锁存Latch锁存器EA：External Address Enable (31) //外部程序存储器(ROM)地址允许其它：OE:output enable //输出使能MSB = most significant bit//最高有效位[sig'nifikənt] adj. 重大的；有效的；有意义的；值得注意的；意味深长的n. 象征；有意义的事物LSB = last significant bit//最低有效位DB = define byte //字节定义ORG = originally //起始来源EQU = equal //等于DW = define word //字定义CLKOUT：Clock out,时钟输出BUSWDITH：总线宽度Vref：参考电压（带ADC的单片机中有的）参考电压（Voltage Reference）['refərəns n. 参考，参照；HSO：High Speed Output，高速输出HSI：High Speed Input：高速输入INST：Instruction，指令READY就绪，总线中的就绪信号或引脚NMI：No Mask Interruput （Input）：不可屏蔽的中断请求（输入）[mɑ:sk, mæskBHE：Bank High Enable：存储器的高位允许，如在80286系统中RAM的组织为16位的，分为高8位和低8位数据，分别的控制信号为BHE和BLE Bank n. 银行；岸；浅滩；储库vt. 将…存入银行；倾斜转弯vi. 堆积；倾斜转弯MCS-51指令（1）数据传送类指令（7种助记符）助记符英文注释功能MOV Move 对内部数据寄存器RAM和特殊功能寄存器SFR的数据进行传送MOVC Move Code 读取程序存储器数据表格的数据传送MOVX Move External RAM 对外部RAM的数据传送XCH Exchange 字节交换XCHD Exchange low-order Digit ['didʒit]低半字节交换POP Pop from Stack) 出栈PUSH Push onto ['ɔntu, -tə] Stack) 入栈（2）算术运算类指令（8种助记符）ADD Addition 加法ADDC Add with Carry 带进位加法SUBB Subtract [səb'trækt] with Borrow 带借位减法vt. 减去；扣DA Decimal ['desiməl]adj. 小数的；十进位的n. 小数Adjust [ə'dʒʌst]调整十进制调整INC Increment ['inkrimənt加1 DEC Decrement 'dekrimənt]减1MUL Multiplication、Multiply 乘法[,mʌltipli'keiʃən n. [数] 乘法；增加['mʌltiplai vt. 乘；使增加；使繁殖；使相乘vi. 乘；繁殖；增加adv. 多样地；复合地adj. 多层的；多样的DIV Division[di'viʒən n. [数] 除法；部门；分割；师（军队）；赛区、Divide 除法di'vaid vt. 划分；除；分开；使产生分歧vi. 分开；意见分歧n. [地理] 分水岭，分水线(3)逻辑运算类指令（10种助记符）ANL And Logic 逻辑与'lɔdʒik] n. 逻辑；逻辑学；逻辑性adj. 逻辑的ORL OR Logic 逻辑或CLR Clear kliə]清零XRL Exclusive-OR Logic 逻辑异或[ik'sklu:siv] adj. 独有的；排外的；专一的n. 独家新闻；独家经营的项目；排外者CPL Complement 取反'kɔmplimənt] n. 补语；余角；补足物vt. 补足，补助RL Rotate left 循环左移[rəu'teit, 'rəut-, 'rəuteit vi.旋转；循环vt. 使旋转；使转动；使轮流adj. [植] 辐状的RLC Rotate Left throught the Carry flag 带进位循环左移RR Rotate Right 循环右移RRC Rotate Right throught the Carry flag 带进位循环右移SWAP Swap 低4位与高4位交换[swɔp, swɔ:p n. 交换；交换之物vt. 与...交换；以...作交换vi. 交换；交易(4)控制转移类指令（17种助记符）ACALL Absolute subroutine Call 子程序绝对调用'æbsəlju:t, ,æbsə'lju:t adj. 绝对的；完全的；专制的n. 绝对；绝对事物'sʌbru:,ti:n, ,sʌbru:'ti:n] n. [计] 子程序LCALL Long subroutine Call 子程序长调用RET Return from subroutine 子程序返回RETI Return from Interruption 中断返回SJMP Short Jump 短转移JMP Jump Indirect 间接跳越[,indi'rekt, -dai-] adj. 间接的；迂回的；非直截了当的AJMP Absolute Jump 绝对转移LJMP Long Jump 长转移CJNE Compare and Jump if Not Equal 比较不相等则转移kəm'pεə] vt. 比较；对照；比喻为vi. 比较；相比n. 比较DJNZ Decrement and Jump if Not Zero 减１后不为０则转移JZ Jump if Zero 结果为０则转移JNZ Jump if Not Zero 结果不为０则转移JC Jump if the Carry flag is set 有进位则转移JNC Jump if Not Carry 无进位则转移JB Jump if the Bit is set) B位为１则转移JNB Jump if the Bit is Not set B位为０则转移JBC Jump if the Bit is set and Clear the bit 位为１则转移，并清除该位NOP No Operation 空操作[,ɔpə'reiʃən] n. 操作；经营；[外科] 手术；[数][计] 运算（5）位操作指令（1种助记符）SETB Set Bit 置位伪指令助记符英文注释功能ORG OriginDB Define ByteDW Define WordEQU EqualDATA DataXDATA External DataBIT BitEND End51外部引脚缩写英文解释中文解释RST （9）Reset 复位信号引脚[,ri:'set, 'ri:set vi. 重置；清零vt. 重置；重新设定；重新组合n. 重新设定；重新组合；重排版RxD (10--P3.0) Receive Data 串口接收端TxD (11--P3.1) Transmit Data 串口发送端INT0(————) （12--P3.2）Interrupt0 外部中断0信号输入引脚INT1(————) （13--P3.3）Interrupt1 外部中断1信号输入引脚T0 (14--P3.4) Timer0 定时/计数器0输入信号引脚T1 (15--P3.5) Timer1 定时/计数器1输入信号引脚LSB = last significant bit//最低有效位significant [sig'nifikənt有效的WR(———) (16--P3.6) write写信号引脚RD(———) (17--P3.7) read 读信号引脚PSEN(—————) （29）programmer saving enable 外部程序存储器读选通信号ALE （30）Address Latch Enable 地址锁存允许信号EA(———) (31) enable 外部ROM选择信号51内部寄存器SFR special funtion register 特殊功能寄存器ACC accumulate 累加器A PSW programmer status word 程序状态字CY (PSW.7) carry 进位标志位AC (PSW.6) assistant carry 辅助进位标志位ə'sistənt] n. 助手，助理，助教adj. 辅助的，助理的；有帮助的OE = output enable //输出使能OV (PSW.2) overflow 溢出标志位[,əuvə'fləu, 'əuvəfləu]PC programmer counter 程序计数器DPTR data point register 数据指针寄存器SP stack point 堆栈指针TCON timer control 定时器控制寄存器TF1（TCON.7）Timer1 flag T1中断标志位TR1（TCON.6）Timer1 Run T1运行控制位TF0 （TCON.5）Timer0 flag T0中断标志位TR0 （TCON.4）Timer0 Run T0运行控制位IE1 （TCON.3） Interrupt1 exterior 外部中断1中断标志位ik'stiəriə adj. 外部的；表面的；外在的n. 外部；表面；外型；外貌MSB = most significant bit//最高有效位IT1 （TCON.2）Interrupt1 touch 外部中断1 触发方式选择位IE0 （TCON.1）Interrupt0 exterior 外部中断0中断标志位IT0 （TCON.0）Interrupt0 touch 0-电平触发1-下降沿触发IE （A8H）interrupt enable 中断允许寄存器EA (IE.7) enable all interrupt 中断总允许位ES (IE.4) enable serial 串行口中断允许位['siəriəl, 'si:r-] adj. 连续的；连载的；分期偿还的n.电视连续剧；[图情] 期刊；连载小说ET0 （IE.1）enable timer 0 T0中断允许位ET1（IE.3）enable timer 1 T1中断允许位EX1 （IE.2）enable exterior 1 外部中断1中断允许位EX0 （IE.0）enable exterior 0 外部中断0中断允许位IP （B8H）interrupt priority 中断优先级寄存器PS (IP.4) priority serial 串口优先级标志位PT1 (IP.3) priority timer 1 定时器1优先级标志位PX1 (IP.2) priority exterior 1 外部中断1优先级标志位PT0 (IP.1) priority timer 0 定时器0优先级标志位PX0 (IP.0) priority exterior 0 外部中断0优先级标志位PCON (87H) power control 电源控制和波特率选择TMOD （89H）timer mode 定时器方式控制寄存器。

MCS-51系列单片机中英文资料对照外文翻译文献综述教学文稿

精品文档MCS-51系列单片机中英文资料对照外文翻译文献综述Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have, such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same.8051 daily representatives-51 serial one-chip computers.A one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3)Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031, 8032.(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporaries of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to counttemporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a express in the order. The controller includes the procedure counter, the order is deposited, the order deciphering, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, using for middle result to deposit operation, the data are stored temporarily and the data are buffered. In RAMof this 128B, there is unit of 32 bytes that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of location, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different datatransmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast I/O ports, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make data can latch when outputting, data can buffer when making introduction, but four function of pass away these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use port correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouth, its output grade draws the resistance supremely. When using it as the mouth in common use,output grade is it leak circuit to turn on, is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write"1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate, can draw the pin to the high level fast; when resistance value is very large, P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw electric current load to offer outwards, draw the resistance on needn't answer and thinking. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end relatively about 20,000 ohms because of load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1.P3 mouth one multi-functional port, mouth getting many than P1 it have "3 doors and 4 buffers". Two parts there, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and" door 3functions one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W=At 1 o'clock, output Q end signal; act as Q=At 1 o'clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance .It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location to visit to P3 mouth/at not lasting lining, there are inside hardware latch Qs=1. The operation principle of P3 mouth is similar to P1 mouth.Output grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outer. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscilloscope tentatively,push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS-51系列单片机的功能和结构MSC-51系列单片机具有一个单芯片电脑的结构和功能，它是英特尔公司的系列产品的名称。

89C51单片机简介-外文原文及译文

89C51 Microcontroller Introduction Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, but not ideal because the cost has not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90s dedicated processor, while the average model prices fall to one U.S. dollar, the most high-end model is only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems.SCM relies on the program, and can be modified. Through different procedures to achieve different functions, in particular special unique features, this is another device much effort needs to be done, some are great efforts are very difficult to achieve. A not very complex functions if the 50's with the United States developed 74 series, or the 60's CD4000 series of these pure hardware buttoned, then the circuit must be a large PCB board! But if the United States if the 70's with a series of successful SCM market, the result will be a drastic change! Just because you areprepared by microcomputer programs can achieve high intelligence, high efficiency and high reliability!IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides postsilicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri -ng each access to external DataMemory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, andthe next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal formsis carried out in a number of steps.An analog-to-digital converter(ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself.Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for a digital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator.The signals used within microcomputer circuits are almost always too small to be connected directly to the “outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator.To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. T hese hardware devices, called peripherals, are the CPU’s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions.Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.Its applicationsSCM is widely used in instruments and meters, household appliances, medical equipment, aerospace, specialized equipment, intelligent management and process control fields, roughly divided into the following several areas:SCM has a small size, low power consumption, controlling function, expansion flexibility, the advantages of miniaturization and ease of use, widely used instrument, combining different types of sensors can be realized, such as voltage, power, frequency, humidity, temperature, flow, speed, thickness, angle, length, hardness, elemental, physical pressure measurement. SCM makes use of digital instruments, intelligence, miniaturization, and functionality than the use of more powerful electronic or digital circuits. Such as precision measuring equipment (power meter, oscilloscope, various analytical instrument).89C51单片机简介单片机广泛应用于各个商业领域，比如：调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。

51单片机论文英语文翻译

英文原文DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Block DiagramVCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers cansink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers cansink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers cansink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receivessome control signals forFlash programming andverification.RSTReset input. A high onthis pin for two machinecycles while the oscillator isrunning resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin orto external memory.Power Down ModeIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:If the device is powered up without a reset, the latch initializes to a random value, and holds that valueuntil reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash：The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled.program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: T he entire Flash Programmable and Erasable Read Only Memory array is erasedelectrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated,will automatically time itself to completion.Figure 3. Programming the Flash Figure 4. Verifying the FlashFlash Programming and Verification CharacteristicsNote: 1. Only used in 12-volt programming mode.Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°CStorage Temperature ..................................... -65°C to +150°CVoltage on Any Pinwith Respect to Ground .....................................-1.0V to +7.0VMaximum Operating Voltage............................................. 6.6VDC Output Current...................................................... 15.0 mADC CharacteristicsMaximum IOL per port pin: 10 mAMaximum IOL per 8-bit port: Port 0: 26 mAPorts 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mA2. Minimum VCC for Power Down is 2V.AC Characteristics(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF)External Program Memory Read CycleExternal Data Memory Read CycleExternal Data Memory Write CycleExternal Clock Drive WaveformsShift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.Float Waveforms(1)Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs.Ordering Information– Reserved bits.. Reset value depends on reset source.描述AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。

AT89C51单片机中英文文献翻译AT89C51的概况

The General Situation of AT89C511 The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Platform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once inthe market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financially prohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components are extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions. This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully. Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts. The type of the device and its application requirements determine which types of testing are performed on the device.1.2 The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Figure 1-2-1 Block Diagram1.3 Pin DescriptionVCC: Supply voltage.GND: Ground.Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull ups are required during program verification.Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN: Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twice eachmachine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. The spinal receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2: Output form the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Power-down Mode:In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRS but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. The AT89C51 code memory array is programmed byte by byte in either programming mode. Toprogram any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.2 Programming AlgorithmsBefore programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 Ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.2.1 Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify:If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Figure 2-1-1 Programming the Flash Figure 2-2-2 Verifying the Flash2.2 Chip Erase:The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.2.3 Reading the Signature Bytes:The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programming2.4 Programming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter (ADC) is used to convert a continuously variable signal to a corresponding digital form which can take any one of a fixed number of possible binary values. If the output of the transducer does not vary continuously, no ADC is necessary. In this case the signal conditioning section must convert the incoming signal to a form which can be connected directly to the next part of the interface, the input/output section of the microcomputer itself. Output interfaces take a similar form, the obvious difference being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of the interface and performs the scaling numbers which may be needed for digital-to-analog converter (DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator. The signals used within microcomputer circuits are almost always too small to be connected directly to the outside world” and some kind of interface must be used to translate them to a more appropriate form. The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator. To solve real-world problems, a microcontroller must have more than just a CPU, a program, and a data memory. In addition, it must contain hardware allowing the CPU to access information from the outside world. Once the CPU gathers information and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPU’s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose I70 port. Each of the I/O pins can be used as either an input or an output. The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions. Some type of serial unit is included on microcontrollers to allow the CPU to communicate bit-serially with external devices. Using a bit serial format instead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously.AT89C51的概况1 AT89C51的应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。

单片机外文翻译

单片机外文翻译河北农业大学毕业设计(论文)外文资料翻译院(系): 信息科学与技术学院专业: 电子信息科学与技术姓名: 李洋学号: 2007234020316外文出处: from internetStructure and function of the MCS-51 series附件: 1.外文资料翻译译文,2.外文原文。

完成日期: 2011 年 3月1 日1. 外文资料翻译译文:51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。

这家公司在1976年引入8位MCS - 48系列单片机后，于1980年又推出了8位高档的MCS - 51系列，8031，8751，80C51BH，80C31BH等，单片机。

它包含很多种这类型的单片机，如8051它们的基本组成，基本性能和指令系统都是一样的。

一般情况习惯用8051来代表51系列单片机。

一个单片机的系统是由以下几部分组成:(1)一个8位CPU微处理器。

(2)静态随机存取存储器，能够储存程序运行过程中产生的数据。

(3)程序存储器ROM / EPROM中(4KB/8KB)，用来保存程序和一些初始数据。

但是在一些单片机中不使用ROM / EPROM中，如8031，8032，80c系列等。

(4)4个8排的I / O并行接口P0~P3，每个口可以用作输入，也可以用作输出。

(5)2个定时器/计数器，每个定时器/计数器可设置计数用来计数外部事件，可以设置成常用的定时方式，并可以根据计算或结果控制单片机的运行。

(6)五个中断源控制系统。

(7)1个双向串行I / O口的UART(通用异步接收器/发送器UART)，用于实现单片机的串行通信。

(8)振荡器和时钟产生电路，需要外部电源的石英晶体微调电路，允许接在12v的振荡频率上。

上述部分通过内部数据总线连接。

其中，CPU是单片机的核心，它是单片机的控制和指挥中心，ALU算数逻辑运算单元可进行算术运算和逻辑运算，由1个 8暂时存储器，和2个 8位的累加器组成。