非常经典 清华大学 李宇根 PLL讲义

Spring Semester, 2008
PLL DESIGN AND CLOCK/FREQUENCY GENERATION (Lecture 14)
Woogeun Rhee Institute of Microelectronics Tsinghua University

Final Examination
• Date & time: June 24th (7:15pm – 9:00pm) • Place: 6B204 (Lecture room) • You can bring one A4 sheet with formula or anything written. Must be hand-written!! • Using calculator is allowed (maybe not necessary).
2
W. Rhee, Institute of Microelectronics, Tsinghua University

V. Advanced Topics 1. Coupling
3
W. Rhee, Institute of Microelectronics, Tsinghua University

Coupling Effect on Clock Jitter
JSSC’96, von Kaenel et al.
Without Supply Noise
SiRF’06, Jenkins et al.
With Supply Noise
4
W. Rhee, Institute of Microelectronics, Tsinghua University

Review: Effect of External Noise Coupling
Ideal Oscillator With Good Isolation With Coupling
• Coupling within fo/(2Q) will be increased by fo/(2Qfm) - Just behaviors like circuit noise!! • Interference coupling near Fout can be reduced only by isolation.
5
W. Rhee, Institute of Microelectronics, Tsinghua University

Coupling Mechanism
• Substrate noise • Supply noise • Ground bouncing • Crosstalk
6
W. Rhee, Institute of Microelectronics, Tsinghua University

Substrate Noise in SoC
“Substrate noise coupling is still one of the least understood phenomena in mixed signal/RF SoC designs”

7
W. Rhee, Institute of Microelectronics, Tsinghua University

Living with Substrate Noise
• Use known physical isolation methods. Develop rules of thumb for layout. • Simulate noise effect during floor planning or layout. Requires sophisticated and accurate software.
8
W. Rhee, Institute of Microelectronics, Tsinghua University

Substrate Noise Coupling Mechanism
(possible noise) nFET
p+ n n n
nFET
n
wiring; inductor
Noise sources: substrate contacts drain/source junctions metal levels Noise receivers: substrate contacts drain/source junctions nFET channel (body effect) metal levels
9
W. Rhee, Institute of Microelectronics, Tsinghua University

Substrate Noise Effect
10
W. Rhee, Institute of Microelectronics, Tsinghua University

Substrate Noise in ASIC Environment •Synthesized digital circuits usually have 3-terminal transistors

with global supply and ground.

•More complicated with huge number of transistors and different voltage islands.

•Power/ground grids good for lowering impedance not for isolation. ÆDifficult to form customized substrate contacts.

•Support for substrate modeling extraction??

ÆBetter to have more silicon experience.