先进芯片封装知识介绍PPT
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▼ Provides fine pitch top package interface with thru mold via ▼ Improved board level reliability ▼ Larger die size / package size ratio ▼ Compatible with flip chip, wire bond, or stacked die configurations ▼ Cost effective compared to alternative next generation solutions
Advanced Packaging Tech
1
Outline
▼ Package Development Trend ▼ 3D Package ▼ WLCSP & Flip Chip Package
2
Package Development Trend
3
Package Development Trend
A through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits. A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. In most 3D packages, the stacked chips are wired together along their edges. This edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon via replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or thickness.
▼ SO Family
▼ QFP Family
▼ BGA Family
4
Package Development Trend
▼ CSP Family
▼ Memory Card
▼ SiP Module
5
3D Package
3D Package
6
3D Package Introduction
High
Multi Chip Stack
2 Chip Stack Flip Chip & Wirebond
3 S-CSP
3S-PBGA Stacked-SiP
4SS-SCSP
5SCSP
ቤተ መጻሕፍቲ ባይዱ
Ultra thin Stack
FS-CSP1
FS-CSP2
FS-BGA
2 Chip Stack Wirebond
Low
S-etCSP S-TSOP / S-QFP
Through Mold Via
Top view
Bottom view
12
▼ Process Flow of TMV PoP
Ball Placement on top surface Die Bond
Mold (Under Full optional)
PoP
Laser drilling
Ball Placement on bottom
10
▼ PoP Core Technology
Low Loop Wire
PoP
Pin Gate Mold
Wafer Thinning
PS-vfBGA PS-etCSP
Package Stacking
11
PoP
▼ Amkor’s TMV™ PoP
▼ Allows for warpage reduction by utilizing fully-molded structure ▲ More compatible with substrate thickness reduction
Wire Bonding Stacked Die TSV
9
PoP
▼ What’s PoP?
▲ PoP is Package on Package ▲ Top and bottom packages are tested separately by device manufacturer or subcon.
Tape-SCSP (or LGA)
S-PBGA
S-SBGA
S-CSP (or LGA)
SS-SCSP(film)
SS-SCSP(paste)
S-M2CSP 7
Stacked Die
FOW materil
Wire Top die
Bottom die 8
TSV
▼ TSV (Through Silicon Via)
Singulation Final Visual Inspection
Base M’tl
Thermal effect
13
PiP
Epoxy
spacer
Memory die Analog die Digital die
Package on Package (PoP) Stacking
etCSP + S-CSP etCSP Stack
Paper Thin PS-vfBGA + SCSP
PoP with interposer PS-fcCSP + SCSP
PiP
DDDD2234 DDDD3242
PoP QFN
Functional Integration
Advanced Packaging Tech
1
Outline
▼ Package Development Trend ▼ 3D Package ▼ WLCSP & Flip Chip Package
2
Package Development Trend
3
Package Development Trend
A through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits. A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. In most 3D packages, the stacked chips are wired together along their edges. This edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon via replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or thickness.
▼ SO Family
▼ QFP Family
▼ BGA Family
4
Package Development Trend
▼ CSP Family
▼ Memory Card
▼ SiP Module
5
3D Package
3D Package
6
3D Package Introduction
High
Multi Chip Stack
2 Chip Stack Flip Chip & Wirebond
3 S-CSP
3S-PBGA Stacked-SiP
4SS-SCSP
5SCSP
ቤተ መጻሕፍቲ ባይዱ
Ultra thin Stack
FS-CSP1
FS-CSP2
FS-BGA
2 Chip Stack Wirebond
Low
S-etCSP S-TSOP / S-QFP
Through Mold Via
Top view
Bottom view
12
▼ Process Flow of TMV PoP
Ball Placement on top surface Die Bond
Mold (Under Full optional)
PoP
Laser drilling
Ball Placement on bottom
10
▼ PoP Core Technology
Low Loop Wire
PoP
Pin Gate Mold
Wafer Thinning
PS-vfBGA PS-etCSP
Package Stacking
11
PoP
▼ Amkor’s TMV™ PoP
▼ Allows for warpage reduction by utilizing fully-molded structure ▲ More compatible with substrate thickness reduction
Wire Bonding Stacked Die TSV
9
PoP
▼ What’s PoP?
▲ PoP is Package on Package ▲ Top and bottom packages are tested separately by device manufacturer or subcon.
Tape-SCSP (or LGA)
S-PBGA
S-SBGA
S-CSP (or LGA)
SS-SCSP(film)
SS-SCSP(paste)
S-M2CSP 7
Stacked Die
FOW materil
Wire Top die
Bottom die 8
TSV
▼ TSV (Through Silicon Via)
Singulation Final Visual Inspection
Base M’tl
Thermal effect
13
PiP
Epoxy
spacer
Memory die Analog die Digital die
Package on Package (PoP) Stacking
etCSP + S-CSP etCSP Stack
Paper Thin PS-vfBGA + SCSP
PoP with interposer PS-fcCSP + SCSP
PiP
DDDD2234 DDDD3242
PoP QFN
Functional Integration