74HC_HCT573 三态锁存器
74VHCT573AMTCX,74VHCT573AMT,74VHCT573ASJ, 规格书,Datasheet 资料
74VHCT573A Octal D-Type Latch with 3-STATE Outputs74VHCT573A Octal D-Type Latch with 3-STATE OutputsLogic SymbolIEEE/IECTruth TableH = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High ImpedanceFunctional DescriptionThe VHCT573A contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE)input is HIGH, data on the D n inputs enters the latches.In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes.When LE is LOW the latches store the information that was present on the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode, but, this does not interfere with entering new data into the latches.Logic DiagramPlease note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.InputsOutputsOE LE D O n L H H H L H L L L L X O 0HXXZ74VHCT573A Octal D-Type Latch with 3-STATE OutputsAbsolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or beoperable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.Recommended Operating Conditions (5)The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.Notes:2.HIGH or LOW state. I OUT absolute maximum rating must be observed.3.When outputs are in OFF-State or when V CC = 0V.4.V OUT < GND, V OUT > V CC (Outputs Active).5.Unused inputs must be held HIGH or LOW. They may not float.Symbol ParameterRatingV CC Supply Voltage –0.5V to +7.0V V IN DC Input Voltage –0.5V to +7.0V V OUTDC Output Voltage Note 2 Note 3–0.5V to V CC + 0.5V–0.5V to +7.0VI IK Input Diode Current –20mA I OK Output Diode Current (4) ±20mA I OUT DC Output Current ±25mA I CC DC V CC /GND Current ±75mAT STG Storage Temperature–65°C to +150°CT LLead Temperature (Soldering, 10 seconds)260°CSymbol ParameterRatingV CC Supply Voltage 4.5V to +5.5V V IN Input Voltage 0V to +5.5V V OUTOutput Voltage Note 2 Note 30V to V CC 0V to 5.5V T OPR Operating Temperature–40°C to +85°C t r , t fInput Rise and Fall Time, V CC =5.0V ± 0.5V0ns/V ~ 20ns/V74VHCT573A Octal D-Type Latch with 3-STATE OutputsDC Electrical CharacteristicsNoise CharacteristicsNote:6.Parameter guaranteed by design.SymbolParameterV CC (V)Conditions T A = 25°CT A = –40°C to +85°C UnitsMin.Typ.Max.Min.Max. V IH HIGH Level Input Voltage4.5 2.0 2.0V5.5 2.02.0V IL LOW Level Input Voltage4.50.80.8V5.50.80.8V OH HIGH Level Output Voltage4.5V IN = V IH or V ILI OH = –50µA 4.40 4.50 4.40V I OH = –8mA 3.943.80V OL LOW Level Output Voltage4.5V IN = V IH or V ILI OL = 50µA 0.00.10.1V I OL = 8mA 0.360.44I OZ 3-STATE Output Off-State Current 5.5V IN = V IH or V IL , V OUT = V CC or GND ±0.25±2.5µA I IN Input Leakage Current0–5.5V IN = 5.5V or GND ±0.1±1.0µA I CC Quiescent Supply Current5.5V IN = V CC or GND 4.040.0µA I CCT Maximum I CC /Input 5.5V IN =3.4V , Other Inputs = V CC or GND 1.35 1.50mA I OFFOutput Leakage Current (Power Down State)0.0V OUT = 5.5V0.55.0µA SymbolParameterV CC (V)ConditionsT A = 25°CUnitsTyp.LimitsV OLP (6)Quiet Output Maximum Dynamic V OL5.0C L = 50pF 1.2 1.6V V OLV (6)Quiet Output Minimum Dynamic V OL5.0C L = 50pF –1.2–1.6V V IHD (6)Minimum HIGH Level Dynamic Input Voltage 5.0C L = 50pF 2.0V V ILD (6)Maximum LOW Level Dynamic Input Voltage5.0C L = 50pF0.8V74VHCT573A Octal D-Type Latch with 3-STATE OutputsAC Electrical CharacteristicsNotes:7.Parameter guaranteed by design. t OSLH = |t PLH max – t PLH min |; t OSHL = |t PHL max – t PHL min |8.C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation:I CC (Opr.) = C PD • V CC • f IN + I CC / 8 (per F/F). The total C PD when n pcs. of the Latch operates can be calculated by the equation: C PD (total) = 14 + 13n.AC Operating RequirementsSymbolParameterV CC (V)ConditionsT A = +25°CT A = –40°C to +85°CUnitsMin.Typ.Max.Min.Max.t PLH , t PHL Propagation Delay Time (LE to O n ) 5.0 ± 0.5C L = 15pF 7.712.3 1.013.5nsC L = 50pF 8.513.3 1.014.5t PLH , t PHL Propagation Delay Time (D to O n ) 5.0 ± 0.5C L = 15pF 5.18.5 1.09.5ns C L = 50pF5.99.5 1.010.5t PZL , t PZH 3-STATE Output Enable Time 5.0 ± 0.5R L = 1k ΩC L = 15pF6.310.9 1.012.5ns C L = 50pF7.111.9 1.013.5t PLZ , t PHZ3-STATE Output Disable Time5.0 ± 0.5R L = 1k ΩC L = 50pF 8.811.2 1.012.0ns t OSLH , t OSHL Output to OutputSkew5.0 ± 0.5(7)1.0 1.0ns C IN Input Capacitance V CC = Open 41010pF C OUT Output Capacitance V CC = 5.0V6pF C PDPower Dissipation Capacitance(8)25pF SymbolParameterV CC (V)T A = +25°CT A = –40°C to +85°C UnitsMin.Typ.Max.Min.Max.t W (H)Minimum Pulse Width (LE) 5.0 ± 0.5 6.58.5ns t S Minimum Set-Up Time 5.0 ± 0.5 1.5 1.5ns t HMinimum Hold Time5.0 ± 0.53.53.5nsFigure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B74VHCT573A Octal D-Type Latch with 3-STATE Outputs The™TinyBoost。
M74HCT573TTR中文资料
1/11July 2001sHIGH SPEED:t PD = 21ns (TYP .) at V CC = 4.5V sLOW POWER DISSIPATION:I CC = 4µA(MAX.) at T A =25°CsCOMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 6mA (MIN)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573DESCRIPTIONThe M74HCT573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with silicon gate C 2MOS technology.This 8-BIT D-Type latches is controlled by a latch enable input (LE) and output enable input (OE).While the LE input is held at a high level, the Q outputs will follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data.While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is at high level the outputs will be in a high impedance state.The 3-State output configuration and the wide choice of outline make bus organized system simple.The M74HCT573 is designed to directly interface HSC 2MOS systems with TTL and NMOS components.All inputs are equipped with protection circuits against static discharge and transient excess voltage.M74HCT573OCTAL D-TYPE LATCHWITH 3 STATE OUTPUT NON INVERTINGPIN CONNECTION AND IEC LOGIC SYMBOLSORDER CODESPACKAGE TUBE T & RDIP M74HCT573B1R SOP M74HCT573M1RM74HCT573RM13TR TSSOPM74HCT573TTRM74HCT5732/11INPUT AND OUTPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEX: Don’t CareZ: High Impedance(*): Q Outputs are latched at the time when the LE input is taken low logic level.LOGIC DIAGRAMPIN No SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW)2, 3, 4, 5, 6, 7, 8, 9D0 to D7Data Inputs12, 13, 14, 15, 16, 17, 18, 19Q0 to Q73 State Latch Outputs11LE Latch Enable Input 10GND Ground (0V)20V CCPositive Supply VoltageINPUTSOUTPUTSOE LE D QH X X ZL L X NO CHANGE (*)L H L L LHHHM74HCT5733/11ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°CRECOMMENDED OPERATING CONDITIONSSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7V V I DC Input Voltage -0.5 to V CC + 0.5V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current ± 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 35mA I CC or I GND DC V CC or Ground Current± 70mA P D Power Dissipation 500(*)mW T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage 4.5 to 5.5V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature-55 to 125°C t r , t fInput Rise and Fall Time (V CC = 4.5 to 5.5V)0 to 500nsM74HCT5734/11DC SPECIFICATIONSAC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6ns)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage4.5 to5.5 2.02.02.0V V IL Low Level Input Voltage4.5 to5.50.80.80.8V V OH High Level Output Voltage4.5I O =-20 µA 4.4 4.5 4.4 4.4VI O =-6.0 mA 4.184.31 4.134.10V OL Low Level Output Voltage4.5I O =20 µA 0.00.10.10.1V I O =6.0 mA 0.170.260.330.40I I Input Leakage Current5.5V I = V CC or GND ± 0.1± 1± 1µA I OZ High Impedance Output Leakage Current5.5V I = V IH or V IL V O = V CC or GND ± 0.5± 5± 10µA I CC Quiescent Supply Current5.5V I = V CC or GND 44080µA ∆ I CCAdditional Worst Case Supply Current5.5Per Input pin V I = 0.5V or V I = 2.4V Other Inputs at V CC or GND2.02.93.0mASymbolParameterTest ConditionValue UnitV CC (V)C L (pF)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t TLH t THL Output TransitionTime4.5507121518ns t PLH t PHL Propagation DelayTime (LE - Q,Q) 4.55021334150ns 4.515025394959t PLH t PHL Propagation DelayTime (D - Q,Q) 4.55019303845ns 4.515023364554t PZL t PZH Output EnableTime 4.550R L = 1 K Ω19303845ns 4.515023364554t PLZ t PHZ Output DisableTime4.550R L = 1 K Ω18253138ns t W(L) t W(H)Minimum PulseWidth (LE) 4.5507151922ns t s Minimum Set-Up Time4.5504101315ns t hMinimum Hold Time4.550555nsM74HCT5735/11CAPACITIVE CHARACTERISTICS1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /8 (per Flip Flop)TEST CIRCUITC L = 50pF/150pF or equivalent (includes jig and probe capacitance)R 1 = 1K Ω or equivalentR T = Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance5101010pF C OUT OutputCapacitance10pF C PDPower Dissipation Capacitance (note 1)51pF TESTSWITCH t PLH , t PHL Open t PZL , t PLZ V CC t PZH , t PHZGNDM74HCT5736/11WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES(f=1MHz; 50% duty cycle)M74HCT5737/11WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)WAVEFORM 3: PROPAGATION DELAY TIMES(f=1MHz; 50% duty cycle)元器件交易网M74HCT573 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2000 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - MoroccoSingapore - Spain - Sweden - Switzerland - United Kingdom© 11/11。
74hc573完整中文资料
74hc573中文资料参数-74hc573引脚图-功能原理-74hC573的作用-应用电路-74hC563-54hC57高性能硅门CMOS器件SL74HC573跟LS/AL573的管脚一样。
器件的输入是和标准CMOS输出兼容的；加上拉电阻，他们能和LS/ALSTTL输出兼容。
当锁存使能端为高时，这些器件的锁存对于数据是透明的（也就是说输出同步）。
当锁存使能变低时，符合建立时间和保持时间的数据会被锁存。
×输出能直接接到CMOS，NMOS和TTL接口上×操作电压范围：2.0V~6.0V×低输入电流：1.0uA×CMOS器件的高噪声抵抗特性·三态总线驱动输出·置数全并行存取·缓冲控制输入·使能输入有改善抗扰度的滞后作用原理说明：M54HC563/74HC563/M54HC573/74HC573的八个锁存器都是透明的D 型锁存器，当使能（G）为高时，Q 输出将随数据（D）输入而变。
当使能为低时，输出将锁存在已建立的数据电平上。
输出控制不影响锁存器的内部工作，即老数据可以保持，甚至当输出被关闭时，新的数据也可以置入。
这种电路可以驱动大电容或低阻抗负载，可以直接与系统总线接口并驱动总线，而不需要外接口。
特别适用于缓冲寄存器，I/O 通道，双向总线驱动器和工作寄存器。
HC563引脚功能表：HC573引脚功能表：图1 HC573引脚图图2 HC573 国际电工委员会逻辑符号图3 HC563引脚图图4 HC563 国际电工委员会逻辑符号图5 HC563 逻辑图图6 HC573 逻辑图图7 输入输出等效电路真值表：ABSOLUTE MAXIMUM RATINGS绝对最大额定值：Top Operating Temperature: M54HC Series M74HC Series 操作温度：M54HC系列M74HC系列-55 to +125 -40 to +85℃tr,tf Input Rise and Fall Time输入上升和下降时间VCC =2V0 to 1000ns VCC=4.5V0 to 500VCC =6V0 to 400VOHHigh Level Output Voltage输出高电平电压2.0 VI = VIH or VILIO=-20 μA1.92.0-1.9 -1.9 -V4.54.44.54.44.4---6.05.96.05.95.9-4.5IO=-6.0mA4.184.314.134.10-6.0IO=-7.8 mA5.685.85.635.60-VOLLow Level Output Voltage输出低电平电压2.0 VI = VIH or VILIO=20μA-0.0 0.1 -0.1-0.1V4.5-0.00.1 0.10.16.0-0.00.10.10.14.5IO=6.0mA-0.170.260.330.406.0IO=7.8mA-0.180.260.330.40IIInput Leakage Current输入漏电流6.0VI =VCC or GND--±0.1-±1±1μA IOZState Output Off State Current关断状态3态输出电流6.0VI =VIH or VIL VO =VCC or GND--±0.5-±5.0-±10μAICCQuiescent Supply Current静态电源电流6.0VI =VCC or GND--4-40-80μA应用电路图：点击图片查看大图图8。
(锁存器)sn74hc573
PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-8512801VRA ACTIVE CDIP J201None Call TI Level-NC-NC-NC 5962-8512801VSA ACTIVE CFP W201None Call TI Level-NC-NC-NC 85128012A ACTIVE LCCC FK201None Call TI Level-NC-NC-NC 8512801RA ACTIVE CDIP J201None Call TI Level-NC-NC-NC 8512801SA ACTIVE CFP W201None Call TI Level-NC-NC-NC JM38510/65406BRA ACTIVE CDIP J201None Call TI Level-NC-NC-NC SN54HC573AJ ACTIVE CDIP J201None Call TI Level-NC-NC-NCSN74HC573ADBR ACTIVE SSOP DB202000Pb-Free(RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIMSN74HC573ADW ACTIVE SOIC DW2025Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74HC573ADWR ACTIVE SOIC DW202000Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74HC573AN ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74HC573AN3OBSOLETE PDIP N20None Call TI Call TISN74HC573APWLE OBSOLETE TSSOP PW20None Call TI Call TISN74HC573APWR ACTIVE TSSOP PW202000Pb-Free(RoHS)CU NIPDAU Level-1-250C-UNLIMSN74HC573APWT ACTIVE TSSOP PW20250Pb-Free(RoHS)CU NIPDAU Level-1-250C-UNLIM SNJ54HC573AFK ACTIVE LCCC FK201None Call TI Level-NC-NC-NC SNJ54HC573AJ ACTIVE CDIP J201None Call TI Level-NC-NC-NC SNJ54HC573AW ACTIVE CFP W201None Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-May not be currently available-please check /productcontent for the latest availability information and additional product content details.None:Not yet available Lead(Pb-Free).Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green(RoHS&no Sb/Br):TI defines"Green"to mean"Pb-Free"and in addition,uses package materials that do not contain halogens, including bromine(Br)or antimony(Sb)above0.1%of total product weight.(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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74HC573数据手册
© NXP B.V. 2012. All rights reserved.
2 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
D0
D1
D2
D3
Q0 19 Q1 18 Q2 17 3-STATE Q3 16 OUTPUTS Q4 15 Q5 14 Q6 13 Q7 12
mna809
74HC_HCT573
Product data sheet
All information provided in this document is subject to legal disclaimers.
3 of 21
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input
Fig 6. Pin configuration DHVQFN20
Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Multiple package options ESD protection:
74AHC573 74AHCT573 CMOS 高速透明储存器说明书
74AHC573; 74AHCT573Octal D-type transparant latch; 3-stateRev. 7 — 8 November 2011Product data sheet1. General descriptionThe 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatiblewith Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standardNo.7A.The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuringseparate D-type inputs for each latch and 3-state true outputs for bus orientedapplications. A latch enable input (LE) and an output enable input (OE) are common to alllatches.When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition thelatches are transparent, i.e. a latch output will change state each time its correspondingDn input changes. When pin LE is LOW, the latches store the information that is presentat the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.When pin OE is LOW, the contents of the 8latches are available at the outputs. Whenpin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches.The 74AHC573; 74AHCT573 is functionally identical to the 74AHC373; 74AHCT373, buthas a different pin arrangement.2. Features and benefits⏹Balanced propagation delays⏹All inputs have a Schmitt trigger action⏹Common 3-state output enable input⏹Functionally identical to the 74AHC373; 74AHCT373⏹Inputs accept voltages higher than V CC⏹Input levels:◆For 74AHC573: CMOS input level◆For 74AHCT573: TTL input level⏹ESD protection:◆HBM EIA/JESD22-A114E exceeds 2000V◆MM EIA/JESD22-A115-A exceeds 200V◆CDM EIA/JESD22-C101C exceeds 1000V⏹Multiple package options⏹Specified from -40︒C to +85︒C and from -40︒C to +125︒C3. Ordering information4. Functional diagramTable 1.Ordering informationType numberPackageTemperature rangeNameDescriptionVersion74AHC57374AHC573D -40︒C to +125︒C SO20plastic small outline package; 20leads;body width 7.5mmSOT163-174AHC573PW -40︒C to +125︒C TSSOP20plastic thin shrink small outline package; 20leads; body width 4.4mmSOT360-174AHC573BQ-40︒C to +125︒CDHVQFN20plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5⨯4.5⨯0.85mmSOT764-174AHCT57374AHCT573D -40︒C to +125︒C SO20plastic small outline package; 20leads; body width 7.5mmSOT163-174AHCT573PW -40︒C to +125︒C TSSOP20plastic thin shrink small outline package; 20leads; body width 4.4mmSOT360-174AHCT573BQ-40︒C to +125︒CDHVQFN20plastic dual in-line compatible thermal enhanced very thin quad flat package no leads; 20 terminals; body 2.5⨯4.5⨯0.85mmSOT764-15. Pinning information5.1Pinning5.2Pin descriptionTable 2.Pin descriptionSymbol Pin DescriptionOE1output enable input (active LOW) D0 to D72, 3, 4, 5, 6, 7, 8, 9data inputGND10ground (0V)LE11latch enable (active HIGH)Q0 to Q719, 18, 17, 16, 15, 14, 13, 12data outputV CC20supply voltage6. Functional description[1]H =HIGH voltage level;h =HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;L =LOW voltage level;l =LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;Z =high-impedance OFF-state.7. Limiting values[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.[2]For SO20 packages: above 70︒C the value of P tot derates linearly at 8mW/K.For TSSOP20 packages: above 60︒C the value of P tot derates linearly at 5.5mW/K.For DHVQFN20 packages: above 60︒C the value of P tot derates linearly with 4.5mW/K.Table 3.Function table [1]Operating modeInput Internal latch Output OE LE Dn Qn Enable and read register (transparent mode)L H L L L H H H Latch and read registerL L l L L h H H Latch register and disable outputsHLl L Z hHZTable 4.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Voltages are referenced to GND (ground = 0V).Symbol Parameter Conditions Min Max Unit V CC supply voltage -0.5+7.0V V I input voltage-0.5+7.0V I IK input clamping current V I < -0.5V[1]-20-mA I OK output clamping current V O <-0.5V or V O >V CC +0.5V [1]-20+20mA I O output current V O = -0.5V to (V CC +0.5V)-25+25mA I CC supply current -+75mA I GND ground current -75-mA T stg storage temperature -65+150︒C P tottotal power dissipationT amb = -40 ︒C to +125︒C[2]-500mW8. Recommended operating conditions9. Static characteristicsTable 5.Operating conditions Symbol ParameterConditionsMinTypMaxUnit74AHC573V CC supply voltage 2.0 5.0 5.5V V I input voltage 0- 5.5V V O output voltage 0-V CC V T amb ambient temperature-40+25+125︒C ∆t/∆V input transition rise and fall rateV CC = 3.0 V to 3.6 V --100ns/V V CC = 4.5 V to 5.5 V--20ns/V74AHCT573V CC supply voltage 4.5 5.0 5.5V V I input voltage 0- 5.5V V O output voltage 0-V CC V T amb ambient temperature-40+25+125︒C ∆t/∆Vinput transition rise and fall rateV CC = 4.5 V to 5.5 V--20ns/VTable 6.Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0V).Symbol Parameter Conditions25 ︒C -40︒C to +85 ︒C -40︒C to +125 ︒C UnitMin Typ Max Min Max Min Typ Max 74AHC573V IHHIGH-level input voltageV CC = 2.0 V 1.5-- 1.5- 1.5--V V CC = 3.0 V 2.1-- 2.1- 2.1--V V CC = 5.5 V3.85-- 3.85- 3.85--V V ILLOW-level input voltageV CC = 2.0 V --0.5-0.5--0.5V V CC = 3.0 V --0.9-0.9--0.9V V CC = 5.5 V-- 1.65- 1.65-- 1.65V V OHHIGH-level output voltage V I = V IH or V IL I O = -50μA; V CC =2.0 V1.92.0- 1.9- 1.9--V I O = -50μA; V CC =3.0 V 2.9 3.0- 2.9- 2.9--V I O = -50μA; V CC =4.5 V 4.4 4.5- 4.4- 4.4--V I O = -4.0mA; V CC =3.0 V 2.58-- 2.48- 2.40--V I O = -8.0mA; V CC =4.5 V3.94-- 3.80- 3.70--V V OLLOW-level output voltage V I = V IH or V IL I O = 50μA; V CC =2.0 V-00.1-0.1--0.1V I O = 50μA; V CC =3.0 V -00.1-0.1--0.1V I O = 50μA; V CC =4.5 V -00.1-0.1--0.1V I O = 4.0mA; V CC =3.0 V --0.36-0.44--0.55V I O = 8.0mA; V CC =4.5 V--0.36-0.44--0.55VI OZ OFF-stateoutput current V I=V IH or V IL;V O=V CC or GND;V CC=5.5V--±0.25-±2.5--±10.0μAI I input leakagecurrent V I=V CC or GND;V CC=0V to5.5V--0.1- 1.0-- 2.0μAI CC supply current V I=V CC or GND;I O=0A;V CC=5.5V-- 4.0-40--80μAC I inputcapacitanceV I=V CC or GND-310-10--10pFC O outputcapacitance-4-----10pF 74AHCT573V IH HIGH-levelinput voltageV CC = 4.5 V to 5.5 V 2.0-- 2.0- 2.0--VV IL LOW-levelinput voltageV CC = 4.5 V to 5.5 V--0.8-0.8--0.8VV OH HIGH-leveloutput voltage V I= V IH or V IL; V CC=4.5 VI O= -50μA 4.4 4.5- 4.4- 4.4--V I O= -8.0mA 3.94-- 3.80- 3.70--VV OL LOW-leveloutput voltage V I= V IH or V IL; V CC=4.5 VI O= 50μA-00.1-0.1--0.1V I O= 8.0mA--0.36-0.44--0.55VI OZ OFF-stateoutput current V I=V IH or V IL;V O=V CC or GND per inputpin; other inputs at V CC orGND; I O=0 A--±0.25-±2.5--±10.0μAI I input leakagecurrent V I=5.5 V or GND;V CC=0V to5.5V--0.1- 1.0-- 2.0μAI CC supply current V I=V CC or GND; I O = 0 A;V CC=5.5V-- 4.0-40--80μA∆I CC additionalsupply current per input pin;V I=V CC-2.1V; I O=0 A;other pins at V CC or GND;V CC=4.5V to5.5V-- 1.35- 1.5-- 1.5mAC I inputcapacitanceV I=V CC or GND-310-10--10pFC O outputcapacitance -4-----10pFTable 6.Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0V).Symbol Parameter Conditions25 ︒C-40︒C to+85 ︒C-40︒C to+125 ︒C UnitMin Typ Max Min Max Min Typ Max10. Dynamic characteristicsTable 7.Dynamic characteristicsVoltages are referenced to GND (ground = 0 V); for test circuit see Figure11.Symbol Parameter Conditions25 ︒C-40︒C to+85 ︒C-40︒C to+125 ︒C UnitMin Typ[1]Max Min Max Min Max74AHC573t pd propagationdelay Dn to Qn; see Figure7[2]V CC = 3.0 V to 3.6 VC L=15pF- 5.511.0 1.013.0 1.014.0nsC L=50pF-7.814.5 1.016.5 1.018.5ns V CC = 4.5 V to 5.5 VC L=15pF- 3.9 6.8 1.08.0 1.08.5nsC L=50pF- 5.58.8 1.010.0 1.011.0ns LE to Qn; see Figure8[2]V CC = 3.0 V to 3.6 VC L=15pF- 5.811.9 1.014.0 1.015.0nsC L=50pF-8.315.4 1.017.5 1.019.5ns V CC = 4.5 V to 5.5 VC L=15pF- 4.27.7 1.09.0 1.010.0nsC L=50pF- 5.99.7 1.011.0 1.012.5nst en enable time OE to Qn; see Figure9[3]V CC = 3.0 V to 3.6 VC L=15pF- 5.811.5 1.013.5 1.014.5nsC L=50pF-8.315.0 1.017.0 1.019.0nsV CC = 4.5 V to 5.5 VC L=15pF- 4.47.7 1.09.0 1.010.0nsC L=50pF- 6.39.7 1.011.0 1.012.5ns t dis disable time OE to Qn; see Figure9[4]V CC = 3.0 V to 3.6 VC L=15pF- 6.811.0 1.013.0 1.014.0nsC L=50pF-9.714.5 1.016.5 1.018.5nsV CC = 4.5 V to 5.5 VC L=15pF- 4.67.7 1.09.0 1.010.0nsC L=50pF-7.49.7 1.011.0 1.012.5ns t W pulse width LE HIGH; see Figure8V CC=3.0 V to 3.6 V 5.0-- 5.0- 5.0-nsV CC=4.5 V to 5.5 V 5.0-- 5.0- 5.0-ns t su set-up time Dn to LE; see Figure10V CC=3.0 V to 3.6 V 3.5-- 3.5- 3.5-nsV CC=4.5 V to 5.5 V 3.5-- 3.5- 3.5-ns[1]Typical values are measured at nominal supply voltage (V CC = 3.3V and V CC = 5.0V).[2]t pd is the same as t PHL and t PLH .[3]t en is the same as t PZH and t PZL .[4]t dis is the same as t PHZ and t PLZ .[5]C PD is used to determine the dynamic power dissipation (P D in μW).P D =C PD ⨯V CC 2⨯f i ⨯N +∑(C L ⨯V CC 2⨯f o )where:f i = input frequency in MHz;f o =output frequency in MHz;C L =output load capacitance in pF;V CC =supply voltage in V;N =number of inputs switching;∑(C L ⨯V CC 2⨯f o )=sum of the outputs.t hhold timeDn to LE; see Figure 10V CC =3.0 V to 3.6 V 1.5-- 1.5- 1.5-ns V CC =4.5 V to 5.5 V1.5-- 1.5- 1.5-ns C PDpower dissipation capacitancef i = 1 MHz;V I =GND to V CC[5]-12-----pF74AHCT573; V CC = 4.5 V to 5.5 V t pdpropagation delay Dn to Qn; see Figure 7[2]C L =15pF- 3.5 5.51 6.517.0ns C L =50pF- 4.97.518.519.5ns LE to Qn; see Figure 8[2]C L =15pF - 3.9 6.017.017.5ns C L =50pF- 5.58.519.5111.0ns t enenable timeOE to Qn; see Figure 9[3]C L =15pF - 4.1 6.517.518.5ns C L =50pF- 5.98.5110.0111.0ns t disdisable time OE to Qn; see Figure 9[4]C L =15pF - 4.5 6.517.518.5ns C L =50pF- 6.49.0110.0111.5ns t W pulse width LE HIGH; see Figure 8 5.0-- 5.0- 5.0-ns t su set-up time Dn to LE; see Figure 10 3.5-- 3.5- 3.5-ns t h hold time Dn to LE; see Figure 10 1.5-- 1.5- 1.5-ns C PDpower dissipation capacitancef i = 1 MHz;V I =GND to V CC[5]-18-----pFTable 7.Dynamic characteristics …continuedVoltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.Symbol Parameter Conditions25 ︒C -40︒C to +85 ︒C -40︒C to +125 ︒C Unit MinTyp [1]Max Min Max Min Max11. WaveformsTable 8.Measurement pointsType Input OutputV M V M V X V Y74AHC5730.5⨯V CC0.5⨯V CC V OL + 0.3 V V OH- 0.3 V 74AHCT573 1.5 V0.5⨯V CC V OL + 0.3 V V OH- 0.3 VTable 9.Test dataType Input Load S1 positionV I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74AHC573V CC≤3.0ns15pF, 50pF1kΩopen GND V CC74AHCT573 3.0V≤3.0ns15pF, 50pF1kΩopen GND V CC12. Package outlineSO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1Fig 12.Package outline SOT163-1 (SO20)TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1Fig 13.Package outline SOT360-1 (TSSOP20)Fig 14.Package outline SOT764-1 (DHVQFN20)SOT764-1DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;20 terminals; body 2.5 x 4.5 x 0.85 mm13. AbbreviationsTable 10.AbbreviationsAcronym DescriptionCDM Charged Device ModelCMOS Complementary Metal-Oxide SemiconductorESD ElectroStatic DischargeHBM Human Body ModelMM Machine ModelTTL Transistor-Transistor Logic14. Revision historyTable 11.Revision historyDocument ID Release date Data sheet status Change notice Supersedes74AHC_AHCT573 v.720111108Product data sheet-74AHC_AHCT573 v.6 Modifications:•Legal pages updated.74AHC_AHCT573 v.620101125Product data sheet-74AHC_AHCT573 v.5 74AHC_AHCT573 v.520100325Product data sheet-74AHC_AHCT573 v.4 74AHC_AHCT573 v.420100303Product data sheet-74AHC_AHCT573 v.3 74AHC_AHCT573 v.320080424Product data sheet-74AHC_AHCT573 v.2 74AHC_AHCT573 v.220031208Product specification-74AHC_AHCT573 v.1 74AHC_AHCT573 v.119990927Product specification--15. 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Contents1 General description. . . . . . . . . . . . . . . . . . . . . . 12 Features and benefits . . . . . . . . . . . . . . . . . . . . 13 Ordering information. . . . . . . . . . . . . . . . . . . . . 24 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 25 Pinning information. . . . . . . . . . . . . . . . . . . . . . 45.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Functional description . . . . . . . . . . . . . . . . . . . 57 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 58 Recommended operating conditions. . . . . . . . 69 Static characteristics. . . . . . . . . . . . . . . . . . . . . 610 Dynamic characteristics . . . . . . . . . . . . . . . . . . 811 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 1313 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 1614 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 1615 Legal information. . . . . . . . . . . . . . . . . . . . . . . 1715.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 1715.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 1715.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 1816 Contact information. . . . . . . . . . . . . . . . . . . . . 1817 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19© Nexperia B.V. 2017. All rights reserved For more information, please visit: Forsalesofficeaddresses,pleasesendanemailto:*************************** Date of release:。
74573锁存器 STC12c5a60s2 资料
74573引脚图三态总线驱动输出·置数全并行存取·缓冲控制输入·使能输入有改善抗扰度的滞后作用原理：74LS573 的八个锁存器都是透明的 D 型锁存器，当使能（G）为高时，Q 输出将随数据（D）输入而变。
当使能为低时，输出将锁存在已建立的数据电平上。
输出控制不影响锁存器的内部工作，即老数据可以保持，甚至当输出被关闭时，新的数据也可以置入。
这种电路可以驱动大电容或低阻抗负载，可以直接与系统总线接口并驱动总线，而不需要外接口。
特别适用于缓冲寄存器，I/O 通道，双向总线驱动器和工作寄存器引脚功能D0–D7：Data Inputs数据输入LE：Latch Enable Input (Active HIGH) 锁存使能输入（高电平有效）OE：3-STATE Output Enable Input (Active LOW) 3态输出使能输入（低电平有效）O0–O7：3-STATE Latch Outputs 3态锁存输出Operating Conditions 操作条件VCC ：Supply Voltage 电源电压最小4.75V最大5.25VVIH ：High Level Input Voltage输入高电平电压最小2VVIL：LOW Level Input Voltage 输入低电平电压最大0.8VIOH：HIGH Level Input Current输入高电平电流最大-2.6mAIOL：LOW Level Output Current低电平输出电流最大24mATA ：Free Air Operating Temperature工作温度最大70摄氏度直流电气特性VI Input Clamp Voltage输入钳位电压VCC=最小, II=−18 mA - - −1.5 VVOH High Level OutputVoltage输出高电平电压VCC = 最小, IOH=最大,VIL = 最大 2.7 3.4 - VVOL Low Level OutputVoltage输出低电平电压VCC = 最小, IOL=最大- 0.35 0.5 - VIH = 最小- - - VIOL=4 mA, VCC=最小- - - -II Input Current @ 最大Input Voltage输入电压VCC=最大, VI=7V - - 1 mAIIH HIGH Level Input Current输入高电平电流VCC=最大, VI=2.7V - - 20 μAIIL LOW Level Input Current低电平输入电流VCC=最大, VI=0.4V - - −0.4 mAIOS Short CircuitOutput Current输出短路电流VCC=最大(Note 3) −30 - −130 mA -ICC Supply Current电源电流VCC=最大- - 50 mAIOZH 3-STATE Outputoff Current High 3态输出高阻态时高电平电流IOZL 3-STATE Outputoff Current Low 3态输出高阻态时低电平电流tPLH tPHL Propagation Delay传播延迟tPLH tPHL Propagation Delay传播延迟LE to Q - 36 25 ns tPZH tPZL 3-STATE Enable Time3态启用时间OE to Q - 20 25 nstPHZ tPLZ 3-STATE Enable Time3态启用时间OE to Q - 20 25 nsts(H)ts(L) Setup Time (High/Low) 设置时间（高/低）Data to LE 3 7 - nsth(H)th(L) Hold Time (High/Low)保持时间（高/低)Le Data to LE 10 10 - ns tw(H) - Pulse Width (High) 脉冲宽度（高）LeData to LE 15 - - ns看一下STC12C5A60S2系列1T单片机的功能就明白较89C51的优势了： 1.增强型8051 CPU，1T，单时钟/ 机器周期，指令代码完全兼容传统8051 2.工作电压：STC12C5A60S2 系列工作电压：5.5V - 3.3V STC12LE5A60S2 系列工作电压：3.6V - 2.2V 3. 工作频率范围：0 - 35MHz，相当于普通8051 的0～420MHz 4. 用户应用程序空间8K /16K / 20K / 32K / 40K / 48K / 52K / 60K / 62K 字节...... 5. 片上集成1280 字节RAM 6. 通用I/O 口（36/40/44 个），复位后为：准双向口/ 弱上拉（普通8051 传统I/O 口）可设置成四种模式：准双向口/ 弱上拉，推挽/ 强上拉，仅为输入/ 高阻，开漏每个I/O 口驱动能力均可达到20mA，但整个芯片最大不要超过120mA 7. I S P（在系统可编程）/IAP （在应用可编程），无需专用编程器，无需专用仿真器可通过串口（P3.0/P3.1）直接下载用户程序，数秒即可完成一片8. 有EEPROM 功能(STC12C5A62S2/AD/PWM 无内部EEPROM) 9. 看门狗10.内部集成MAX810 专用复位电路（外部晶体12M 以下时，复位脚可直接1K 电阻到地）11. 外部掉电检测电路: 在P4.6 口有一个低压门槛比较器5V 单片机为1.32V，误差为+/-5%,3.3V 单片机为1.30V，误差为+/-3% 12. 时钟源：外部高精度晶体/ 时钟，内部R/C 振荡器(温漂为+/-5% 到+/-10% 以内) 用户在下载用户程序时，可选择是使用内部R/C 振荡器还是外部晶体/ 时钟常温下内部R/C 振荡器频率为：5.0V 单片机为：11MHz ～15.5MHz 3.3V 单片机为：8MHz ～12MHz 精度要求不高时，可选择使用内部时钟，但因为有制造误差和温漂，以实际测试为准13. 共4 个16 位定时器：两个与传统8051 兼容的定时器/ 计数器,16 位定时器T0 和T1，没有定时器2，但有独立波特率发生器，做串行通讯的波特率发生器，再加上2 路PCA 模块可再实现2 个16 位定时器14. 2 个时钟输出口，可由T0 的溢出在P3.4/T0 输出时钟，可由T1 的溢出在P3.5/T1 输出时钟15. 外部中断I/O 口7 路,传统的下降沿中断或低电平触发中断,并新增支持上升沿中断的PCA 模块，Power Down 模式可由外部中断唤醒，INT0/P3.2, INT1/P3.3, T0/P3.4, T1/P3.5, RxD/P3.0, CCP0/P1.3(也可通过寄存器设置到P4.2 ), CCP1/P1.4 (也可通过寄存器设置到P4.3) 16. PWM(2 路）/PCA（可编程计数器阵列,2 路）--- 也可用来当2 路D/A 使用--- 也可用来再实现2 个定时器--- 也可用来再实现2 个外部中断(上升沿中断/ 下降沿中断均可分别或同时支持) 17. A/D 转换, 10 位精度ADC，共8 路，转换速度可达250K/S(每秒钟25 万次) 18. 通用全双工异步串行口(UART)，由于STC12 系列是高速的8051，可再用定时器或PCA 软件实现多串口19. STC12C5A60S2 系列有双串口，后缀有S2 标志的才有双串口，RxD2/P1.2(可通过寄存器设置到P4.2)，TxD2/P1.3(可通过寄存器设置到P4.3) 20. 工作温度范围：-40 - +85℃(工业级) / 0 - 75℃(商业级) 21. 封装：PDIP-40,LQFP-44,LQFP-48 I/O 口不够时，可用 2 到 3 根普通I/O 口线外接74HC164/165/595（均可级联）来扩展I/O 口,还可用A/D 做按键扫描来节省I/O 口，或用双CPU,三线通信，还多了串口。
74hc573和74hc595有什么不同？该怎样区分74hc573和74hc595
74hc573 和74hc595 有什么不同？该怎样区分
74hc573 和74hc595
这是两种完全不同的器件，74hc573 是个锁存器，而74hc595 则是一个串转并的芯片。
虽然它俩都能节约外部引脚及增大驱动能力，但不是不同点还是大于相同点的，本文是要比较74hc573 和74hc595 的不同点，看看它俩差别在哪些地方。
74hc573
74HC573 是拥有八路输出的透明锁存器，输出为三态门，是一种高性能硅栅CMOS 器件。
器件的输入是和标准CMOS 输出兼容的，加上拉电阻他们能和LS/ALSTTL 输出兼容。
八进制3 态非反转透明锁存器+74HC573+高性能硅门CMOS 器件+SL74HC573 跟LS%2FAL573 的管脚一样。
器件的输入是和标准CMOS 输出兼容+的；加上拉电阻，他们能和LS%2FALSTTL 输出兼容。
当锁存使能端为高时，这些器件的锁存对于数据是透明的（也就是说输出同步）。
当锁存使能变低时，符合建立时间和保持时间的数据会被锁存。
74VHCT573ATTR资料
74VHCT573AOCTAL D-TYPE LATCHWITH 3STATE OUTPUT NON INVERTINGFebruary 2000s HIGH SPEED:t PD =5.4ns (TYP.)at V CC =5V sLOW POWER DISSIPATION:I CC =4µA (MAX.)at T A =25o CsCOMPATIBLEWITH TTL OUTPUTS:V IH =2V (MIN),V IL =0.8V(MAX)sPOWER DOWN PROTECTION ON INPUTS &OUTPUTSsSYMMETRICAL OUTPUT IMPEDANCE:|I OH |=I OL =8mA (MIN)sBALANCED PROPAGATION DELAYS:t PLH ≅t PHLsOPERATING VOLTAGERANGE:V CC (OPR)=4.5V to 5.5VsPIN AND FUNCTION COMPATIBLE WITH 74SERIES 573s IMPROVED LATCH-UP IMMUNITY sLOW NOISE:V OLP =0.9V(Max.)DESCRIPTIONThe 74VHCT573A is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology.This 8bit D-Type latch is controlled by a latch enable input (LE)and an output enable input (OE).While the LE input is held at a high level,the Q outputs will follow the data inputs precisely.When the LE is taken low,the Q outputs will be latched precisely at the logic level of D input data.While the (OE)input is low,the 8outputs will be in a normal logic state (high or low logic level)and while high level the outputs will be in a high impedance state.Power down protection is provided on all inputs and outputs and 0to 7V can be accepted on inputs with no regard to the supply voltage.This device can be used to interface 5V to 3V.All inputs and outputs are equipped with protection circuits against static discharge,giving them 2KV ESD immunity and transient excess voltage.PIN CONNECTION AND IEC LOGIC SYMBOLS®SOPTSSOPORDER CODESPACKAGETUBE T &R SOP 74VHCT573AM74VHCT573AMTR TSSOP74VHCT573ATTR1/1074VHCT573AINPUT EQUIVALENT CIRCUIT PIN DESCRIPTIONPIN No SYMBOL NAME AND FUNCTION1OE3State Output EnableInput(Active LOW)D0to D7Data Inputs2,3,4,5,6,7,8,9Q0to Q73State Latch Outputs12,13,14,15,16,17,18,1911LE Latch EnableInput10GND Ground(0V)20V CC Positive Supply Voltage TRUTH TABLEINPUTS OUTPUTS OE LE D QH X X ZL L X NO CHANGE*L H L LL H H HX:Don’t careZ:High impe dance*Q outputs are latched atthe time when the LEinput is taken low logic level.LOGIC DIAGRAM2/1074VHCT573AABSOLUTE MAXIMUM RATINGSSymbol Parameter Value Unit V CC Supply Voltage-0.5to+7.0V V I DC Input Voltage-0.5to+7.0V V O DC Output Voltage(see note1)-0.5to+7.0V V O DC Output Voltage(see note2)-0.5to V CC+0.5VI IK DC Input Diode Current-20mAI OK DC Output Diode Current±20mAI O DC Output Current±25mAI CC or I GND DC V CC or Ground Current±50mAT stg Storage Temperature-65to+150o CT L Lead Temperature(10sec)300o C Absolute Maximum Ratingsarethose values beyond which dam age to the device may occur.Functional operation un der these condition is not implied.1)Output in OFFState2)High or Low StateRECOMMENDED OPERATING CONDITIONSSymbol Parameter Value Unit V CC Supply Voltage 4.5to5.5V V I Input Voltage0to5.5V V O Output Voltage(see note1)0to5.5V V O Output Voltage(see note2)0to V CC V T op Operating Temperature-40to+85o C dt/dv Input Rise and Fall Time(see note3)(V CC=5.0±0.5V)0to20ns/V1)Output in OFFState2)High or Low State3)V IN from0.8V to2V3/10DC SPECIFICATIONSSymbol Parameter Test Conditions Value UnitV CC (V)T A=25o C-40to85o C Min.Typ.Max.Min.Max.V IH High Level InputVoltage4.5to5.522VV IL Low Level InputVoltage4.5to5.50.80.8VV OH High Level OutputVoltage 4.5I O=-50µA 4.4 4.5 4.4V 4.5I O=-8mA 3.94 3.8V OL Low Level OutputVoltage 4.5I O=50µA0.00.10.1V 4.5I O=8mA0.360.44I OZ High ImpedanceOutput LeakageCurrent 4.5to5.5V I=V IH or V ILV O=0V to5.5V±0.25±2.5µAI I Input Leakage Current0to5.5V I=5.5V or GND±0.1±1.0µA I CC Quiescent SupplyCurrent5.5V I=V CC or GND440µA∆I CC Additional Worst CaseSupply Current 5.5One Input at3.4V,other input at V CC orGND1.35 1.5mAI OPD Output LeakageCurrent0V OUT=5.5V0.5 5.0µA AC ELECTRICAL CHARACTERISTICS(Input t r=t f=3ns)Symbol Parameter Test Condition Value UnitV CC (V)C L(pF)T A=25o C-40to85o CMin.Typ.Max.Min.Max.t PLH t PHL Propagation DelayTime LE to Q5.0(*)15 5.37.5 1.09.0ns5.0(*)50 5.98.5 1.010.0t PLH t PHL Propagation DelayTime D to Q5.0(*)15 5.47.0 1.09.0ns5.0(*)506.48.0 1.010.0t PZL t PZH Output EnableTime 5.0(*)15R L=1KΩ5.47.5 1.010.0ns5.0(*)506.08.5 1.011.0t PLZt PHZOutput Disable Time 5.0(*)50R L=1KΩ 6.39.0 1.012.0nst w Pulse Width(LE)HIGH5.0(*) 5.0 5.0nst s Setup Time D to LEHIGH or LOW5.0(*) 2.0 2.0nst h Hold Time D toLEHIGH or LOW5.0(*) 1.5 1.5nst OSLH t OSHL Output to Output SkewTime(note1)5.0(*)50 1.0 1.0ns(*)Voltag e range is5V±0.5VNote1:Parameter guaranteed bydesign.t soLH=|t pLHm-t pLHn|,t soHL=|t pHLm-t pHLn| 74VHCT573A4/10CAPACITIVE CHARACTERISTICSSymbol Parameter Test Conditions Value UnitT A=25o C-40to85o CMin.Typ.Max.Min.Max.C IN Input Capacitance41010pFC OUT Output Capacitance8pFC PD Power DissipationCapacitance(note1)26pF1)C PD isdefined as the value of the IC’sinternal equiva lent capacitance which is calculated fromthe operating current consumption without load.(Referto Test Circuit).Average operating current can be obtained bythe following equation.I CC(opr)=C PD•V CC•f IN+I CC/8(per Latch)DYNAMIC SWITCHING CHARACTERISTICSSymbol Parameter Test Conditions Value UnitV CC (V)T A=25o C-40to85o C Min.Typ.Max.Min.Max.V OLP Dynamic Low VoltageQuiet Output(note1,2)5.0C L=50pF 0.60.9VV OLV-0.9-0.6V IHD Dynamic High VoltageInput(note1,3)5.0 2.0V ILD Dynamic Low VoltageInput(note1,3)5.00.81)Worst case package.2)Max num ber of outputs defined as(n).Data inputs aredriven0V to3.0V,(n-1)outputs switching and one out put at GND.3)Max num ber of data inputs(n)switching.(n-1)switching0V to3.0V.Inputs under test switching:3.0V to threshold(V ILD),0V to threshold(V IHD),f=1MHz. TEST CIRCUITTEST SWITCHt PLH,t PHL Opent PZL,t PLZ V CCt PZH,t PHZ GNDC L=15/50pF or equ ivalent(includes jigand probe capacitance)R L=R1=1KΩorequivalentR T=Z OU T of pulse generator(typ ically50Ω)74VHCT573A5/1074VHCT573AWAVEFORM1:LE TO Qn PROPAGATION DELAYS,LE MINIMUM PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES(f=1MHz;50%duty cycle)6/1074VHCT573A WAVEFORM2:OUTPUT ENABLE AND DISABLE TIMES(f=1MHz;50%duty cycle)WAVEFORM3:PROPAGATION DELAY TIME(f=1MHz;50%duty cycle)7/10DIM.mm inch MIN.TYP.MAX.MIN.TYP.MAX.A 2.650.104a10.100.200.0040.007a2 2.450.096b 0.350.490.0130.019b10.230.320.0090.012C 0.500.020c145(typ.)D 12.6013.000.4960.512E 10.0010.650.3930.419e 1.270.050e311.430.450F 7.407.600.2910.299L 0.50 1.270.190.050M 0.750.029S8(max.)P013LSO-20MECHANICAL DATA74VHCT573A8/10DIM.mminch MIN.TYP.MAX.MIN.TYP.MAX.A 1.10.433A10.050.100.150.0020.0040.006A20.850.90.950.3350.3540.374b 0.190.300.00750.0118c 0.090.20.00350.0079D 6.4 6.5 6.60.2520.2560.260E 6.25 6.4 6.50.2460.2520.256E1 4.34.4 4.480.1690.1730.176e 0.65BSC0.0256BSCK 0o 4o 8o 0o 4o 8o L0.500.600.700.0200.0240.028cEbA2AE1D1PIN 1IDENTIFICATIONA1LK eTSSOP20MECHANICAL DATA74VHCT573A9/1074VHCT573AInformation furnished is believed to be accurate and reliable.However,STMicroelectroni c s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use.No license is granted by implication or otherwise under any patent or patent rights of STMicroelectroni c s.Specification mentioned in this publication are subject to change without notice.This publication supersedes and replaces all informati o n previously supplied.STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics©2000STMicroelectronics–Printed in Italy–All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia-Brazil-China-Finland-France-Germany-Hong Kong-India-Italy-Japan-Malaysia-Malta-MoroccoSingapore-Spain-Sweden-Switzerland-United Kingdom-U.S.A..10/10。
74HC57芯片
74HC57芯片
74HC573
八进制 3 态非反转透明锁存器
74HC573
高性能硅门 CMOS 器件
SL74HC573 跟 LS/AL573 的管脚一样。
器件的
锁存器
输入是和标准CMOS 输出兼容的；加上拉电阻，他们能和LS/ALSTTL 输出兼容。
当锁存使能端LE为高时，这些器件的锁存对于数据是透明的（也就是说输出同步）。
当锁存使能变低时，符合建立时间和保持时间的数据会被锁存。
×\u36755X出能直接接到 CMOS，NMOS 和 TTL 接口上
×\u25805X作电压范围：2.0V~6.0V
×\u20302X输入电流：1.0uA
×CMOS 器件的高噪声抵抗特性
OE￣ 1 20 Vcc
1D— 2 19 —1Q
2D— 3 18 —2Q
3D— 4 17 —3Q
4D— 5 16 —4Q
5D— 6 15 —5Q
6D—7 14 —6Q
7D—8 13 —7Q
8D—9 12 —8Q
GND 10 11 LE
OE LE D Q
L H H H
L H L L
L L X Q0
H X X Z
1脚三态允许控制端低电平有效
1D~8D为数据输入端
1Q~8Q为数据输出端
74HC573引脚图
LE为锁存控制端
（当OE为高电平时（即OE非为低电平），当LE为高电平时，D与Q同时为高或低电平；那个LE为低电平时，无论给D何种电平状态，Q都保持上一次的数据状态）。
74hc573芯片资料
74HC573和74LS373原理一样，8数据锁存器。
主要用于数码管、按键等等的控制1. 真值表参见74LS373的PDF的第2页：Dn LE OE OnH H L HL H L LX L L QoX X H Z这个就是真值表,表示这个芯片在输入和其它的情况下的输出情况。
每个芯片的数据手册（datasheet）中都有真值表。
布尔逻辑比较简单,在此不赘述;2. 高阻态就是输出既不是高电平,也不是低电平,而是高阻抗的状态;在这种状态下,可以多个芯片并联输出;但是,这些芯片中只能有一个处于非高阻态状态,否则会将芯片烧毁;高阻态的概念在RS232和RS422通讯中还可以用到。
3. 数据锁存当输入的数据消失时,在芯片的输出端,数据仍然保持;这个概念在并行数据扩展中经常使用到。
4. 数据缓冲加强驱动能力。
74LS244/74LS245/74LS373/74LS573都具备数据缓冲的能力。
OE：output_enable,输出使能;LE：latch_enable,数据锁存使能,latch是锁存的意思;Dn：第n路输入数据;On：第n路输出数据;再看这个真值表,意思如下：第四行：当OE＝1是,无论Dn、LE为何,输出端为高阻态;第三行：当OE＝0、LE＝0时,输出端保持不变;第二行第一行：当OE＝0、LE＝1时,输出端数据等于输入端数据;结合下面的波形图,在实际应用的时候是这样做的：a．OE＝0;b．先将数据从单片机的口线上输出到Dn;c．再将LE从0->1->0d．这时,你所需要输出的数据就锁存在On上了,输入的数据在变化也影响不到输出的数据了;实际上,单片机现在在忙着干别的事情,串行通信、扫描键盘……单片机的资源有限啊。
在单片机按照RAM方式进行并行数据的扩展时,使用movx @dptr, A这条指令时,这些时序是由单片机来实现的。
后面的表格中还有需要时间的参数,你不需要去管它,因为这些参数都是几十ns 级别的,对于单片机在12M下的每个指令周期最小是1us的情况下,完全可以实现;如果是你自己来实现这个逻辑,类似的指令如下：mov P0,A ;将数据输出到并行数据端口clr LEsetb LEclr LE ;上面三条指令完成LE的波形从0->1->0的变化74ls573跟74LS373逻辑上完全一样,只不过是管脚定义不一样,数据输入和输出端。
HC573锁存器知识
3. 当OE为低电平，LE为低电平，无论D 为何种电平，Q总保持上一次的状态 （即Q端保持住LE端变为低电平之前 Q端电平状态）。
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锁存器HC573介绍
一、端口介绍
OE-三态允许控制端/输出使 能端（低电平有效） D0--D7为数据输入端 Q0—Q7为数据输出端 LE-锁存允许端或锁存控制 端
二、真值表
H-高电平 L-低电平 X-任意电平 Z-高阻态 NO CHANGE上次电平状态
三、锁存实现
1. 当OE为高电平，无论LE于D端为何种 电平状态，其输出都为高组态，芯 片不可控。OE端须接低电平（可直 接接地）。
74HC573锁存器
du74HC573是8位三态锁存器。
当锁存器的输入端出现有效信号，输入状态被锁存到输出端，直到下一个锁存信号到来时刷新。
这里的三态，是指它的输出可以是“0”或“1”状态，又可以是高阻状态。
高阻态相当于隔断状态，没有逻辑控制功能。
原理说明
M54HC563/74HC563/M54HC573/74HC573的八个
锁存器都是透明的D 型锁存器，当使能（G）为高时，Q 输出将随数据（D）输入而变。
当使能为低时，输出将锁存在已建立的数据电平上。
输出控制不影响锁存器的内部工作，即老数据可以保持，甚至当输出被关闭时，
新的数据也可以置入。
这种电路可以驱动大电容或低阻抗负载，可以直接与系统总线接口并驱动总线，而不需要外接口。
特别适用于缓冲寄存器，I/O 通道，双向总线驱动器和工作寄存器。
数据锁存器74HC573在模式锁存触发电路中的应用
数据锁存器74HC573在模式锁存触发电路中的应用【任务引领】上一个任务中我们产生了一个1秒钟的延时信号，在此期间的过渡无效状态都不能引起后续继电器的动作，那就需要添加一个锁存器进行信号的锁存处理，我们利用数据锁存器74HC573完成此项任务。
1图锁存器认识（动画112）【知识目标】1．掌握寄存器的工作原理及分类。
2．掌握锁存器的工作原理。
【能力目标】1．能利用锁存器实现数据锁存。
【任务准备】1．触发器的原理及应用；8.2.1寄存器的特点和分类能存放二值代码的部件叫做寄存器。
寄存器按功能分为数码寄存器和移位寄存器。
数码寄存器只供暂时存放数码，可以根据需要将存放的数码随时取出参加运算或者进行数据处理。
移位寄存器不但可存放数码，而且在移位脉冲作用下，寄存器中的数码可根据需要向左或向右移位。
数码寄存器和移位寄存器被广泛用于各种数字系统和数字计算机中。
寄存器存入数码的方式有并行输入和串行输入两种。
并行输入方式是将各位数码从对应位同时输入到寄存器中；串行输入方式是将数码从一个输入端逐位输入到寄存器中。
从寄存器取出数码的方式也有并行输出和串行输出两种。
在并行输出方式中，被取出的数码在对应的输出端同时出现；在串行输出方式中，被取出的数码在一个输出端逐位输出。
并行方式与串行方式比较，并行存取方式的速度比串行存取方式快得多，但所用的数据线要比串行方式多。
构成寄存器的核心器件是触发器。
对寄存器中的触发器只要求具有置0、置1的功能即可，所以无论何种结构的触发器，只要具有该功能就可以构成寄存器了。
能存放二值代码的部件叫做寄存器。
寄存器按功能分为数码寄存器和移位寄存器。
数码寄存器只供暂时存放数码，可以根据需要将存放的数码随时取出参加运算或者进行数据处理。
移位寄存器不但可存放数码，而且在移位脉冲作用下，寄存器中的数码可根据需要向左或向右移位。
数码寄存器和移位寄存器被广泛用于各种数字系统和数字计算机中。
寄存器存入数码的方式有并行输入和串行输入两种。
74HC573_74HCT573
74HC573/74HCT573（锁存器）
一、简介
74HC573/74HCT573是高速硅门CMOS工艺集成电路，兼容TTL（LSTTL），符合JED EC-7A标准，它将输入数据分别锁存在不同的锁存器上，三态门输出。
锁存器的输入使能端是LE，输出使能端是OE。
当LE端是高电平时，数据进入锁存器；当LE端是低电平时，锁存器保留数据。
当OE端是低电平时，8个锁存器的数据输出有效；当OE端是高电平时，输出端为高阻抗，OE端输入不会影响锁存器中的数据。
二、特点
z输入与输出接口分别置于封装两面，有利于与微处理器相接；
z输入输出接口可与微处理器或微机相接；
z三态门正相输出；
z总线驱动；
z采用DIP20或PLCC20封装形式。
三、内部框图
四、引脚功能。
74hc573锁存器作用
74hc573锁存器作用
在LED和数码管显示方面，要维持一个数据的显示，往往要持续的快速的刷新。
尤其是在四段八位数码管等这些要选通的显示设备上。
在人类能够接受的刷新频率之内，大概每三十毫秒就要刷新一次。
这就大大占用了处理器的处理时间，消耗了处理器的处理能力，还浪费了处理器的功耗。
锁存器的使用可以大大的缓解处理器在这方面的压力。
当处理器把数据传输到锁存器并将其锁存后，锁存器的输出引脚便会一直保持数据状态直到下一次锁存新的数据为止。
这样在数码管的显示内容不变之前，处理器的处理时间和IO 引脚便可以释放。
可以看出，处理器处理的时间仅限于显示内容发生变化的时候，这在整个显示时间上只是非常少的一个部分。
而处理器在处理完后可以有更多的时间来执行其他的任务。
这就是锁存器在LED和数码管显示方面的作用:节省了宝贵的MCU时间。
锁存器和缓冲器的作用和区别
锁存器就是把当前的状态锁存起来，使CPU送出的数据在接口电路的输出端保持一段时间锁存后状态不再发生变化，直到解除锁定。
还有些芯片具有锁存器，比如芯片74LS244就具有锁存的功能，它可以通过把一个引脚置高后，输出就会保持现有的状态，直到把该引脚清0后才能继续变化。
缓冲寄存器又称缓冲器，它分输入缓冲器和输出缓冲器两种。
前者的作用是将外设送来的数据暂时存放，以便处理器将它取走；后者的作用是用来暂时存放处理器送往外设的数据。
有了数控缓冲器，就可以使高速工作的CPU与慢速工作的外设起协调和缓冲作用，实现数据传送的同步。
由于缓冲器接在数据总线上，故必须具有三态输出功能。
SN74HCT573中文资料
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74ls573工作原理
74ls573工作原理Title: Understanding the Working Principle of 74LS573The 74LS573 is a 3-state octal D-type latch with three-state outputs. It is designed to operate with low power consumption and high speed, making it a popular choice in various digital circuits.74LS573是一个具有三态输出的3态8位D型锁存器。
它设计用于低功耗和高速操作，因此在各种数字电路中备受欢迎。
The latch function of the 74LS573 allows it to store and retain data even when the input signals change. This is achieved through the use of internal latches that capture the data on the rising edge of the latch enable (LE) input.74LS573的锁存功能使其能够在输入信号改变时存储和保留数据。
这是通过内部锁存器实现的，这些锁存器在锁存使能（LE）输入的上升沿捕获数据。
When the LE input is high, the data present on the D inputs is latched and appears on the Q outputs. Conversely, when LE is low, the Q outputs are in a high-impedance state, effectively disconnecting them from the internal circuitry.当LE输入为高电平时，D输入上的数据被锁存并出现在Q输出上。
CD74HCT573中文资料
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO
• HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO
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Octal D-type transparent latch; 3-state
Rev. 7 — 4 March 2016 Product data sheet
1. General description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
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Product data sheet
Rev. 7 — 4 March 2016
2 of 20
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
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74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
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Logic diagram
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[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state.
2. Features and benefits
Input levels: For 74HC573: CMOS level For 74HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Multiple package options Complies with JEDEC standard no. 7 A ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to +85 C and from 40 C to +125 C
5. Pinning information
5.1 Pinning
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NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1. Ordering information Temperature range 74HC573D 74HCT573D 74HC573DB 74HCT573DB 74HC573PW 74HCT573PW 74HC573BQ 74HCT573BQ 40 C to +125 C DHVQFN20 40 C to +125 C TSSOP20 40 C to +125 C SSOP20 40 C to +125 C Name SO20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm Version SOT163-1 SOT339-1 SOT360-1 SOT764-1 Type number Package
Fig 1.
Functional diagram
74HC_HCT573
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Rev. 7 — 4 March 2016
4 of 20
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Functional description
Table 3. Function table[1] Control OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs L L H LE H L L Input Dn L H l h l h
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 7 — 4 March 2016
3 of 20
NXP Semiconductors
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
4. Functional diagram