单片机毕业设计外文翻译--AT89S52
AT89S52单片机应用中英文翻译
本科毕业设计（论文）AT89S52单片机应用中英文翻译专业名称：电气工程及其自动化年级班级：学生姓名：指导老师：二O一二年六月九日AT89S52 MCU ApplicationsFunction Characteristic DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin DescriptionVCC ：Supply voltage.GND ：Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 outputbuffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table 1. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that areexternally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table 2.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during eachaccess to exter-nal data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data. Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #data. Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Watchdog TimerThe WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information o n the timers’ operation, please click on the document link below:/dyn/resources/prod_documents/DOC4316.PDFTimer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Power-down ModeIn the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be heldactive long enough to allow the oscillator to restart and stabilize.Idle ModIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.AT89S52单片机应用功能特征描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。
单片机温度控制系统毕业论文中英文资料外文翻译文献
单片机温度控制系统中英文资料外文翻译文献英文原文DescriptionThe at89s52 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s h igh density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmelat89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe at89s52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vectortwo-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the at89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description:VCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internalpull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of theat89s52 as listed below:Port 3 also receives some control signals for Flash programming andverification.RSTReset input. A high on this pin for two machine cycles while theoscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of theaddress during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 theoscillator frequency, and may be used for external timing or clockingpurposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFRlocation 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the at89s52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSENactivations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. Port pinalternate functions P3.0rxd (serial input port) P3.1txd (serial output port) P3.2^int0 (external interrupt0) P3.3^int1 (external interrupt1) P3.4t0 (timer0 external input) P3.5t1 (timer1 external input) P3.6^WR (external data memory write strobe) P3.7 ^rd (external data memory read strobe)EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down Modesmode Program memory ALE ^psen Port0 Port1Port2Port3idle internal 1 1 data data data Data Idle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down ModeIn the power down mode the oscillator is stopped, and the instructionthat invokes power down is the last instruction executed. The on-chip RAMand Special Function Registers retain their values until the power down modeis terminated. The only exit from power down is a hardware reset. Resetredefines the SFRs but does not change the on-chip RAM. The reset shouldnot be activated before VCC is restored to its normal operating level andmust be held active long enough to allow the oscillator to restart andstabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) orcan be programmed (P) to obtain the additional features listed in the tablebelow:Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin issampled and latched during reset. If the device is powered up without a reset,the latch initializes to a random value, and holds that value until reset isactivated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Programming the Flash：The at89s52 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or alow-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the at89s52 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The at89s52 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.Vpp=12v Vpp=5vTop-side mark at89s52xxxxyywwat89s52xxxx-5yywwsignature (030H)=1EH(031H)=51H(032H)=FFH (030H)=1EH (031H)=51H (032H)=05HThe at89s52 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the at89s52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: T he entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.中文翻译描述at89s52是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大at89s52单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
AT89C52中英译文
AT89S52主要性能·与MCS-51单片机产品兼容·8K字节在系统可编程Flash存储器·1000次擦写周期·全静态操作：0Hz～33Hz·三级加密程序存储器·32个可编程I/O口线·三个16位定时器/计数器·八个中断源·全双工UART串行通道·低功耗空闲和掉电模式·掉电后中断可唤醒·看门狗定时器·双数据指针·掉电标识符功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。
使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51 产品指令和引脚完全兼容。
片上Flash允许程序存储器在系统可编程，亦适于常规编程器。
在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。
AT89S52具有以下标准功能：8k字节Flash，256字节RAM，32 位I/O 口线，看门狗定时器，2 个数据指针，三个16 位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。
另外，AT89S52 可降至0Hz 静态逻辑操作，支持2种软件可选择节电模式。
空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。
掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。
引脚结构8 位微控制器8K 字节在系统可编程Flash引脚描述VCC : 电源GND: 地P0 口：P0口是一个8位漏极开路的双向I/O口。
作为输出口，每位能驱动8个TTL逻辑电平。
对P0端口写“1”时，引脚用作高阻抗输入。
当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。
在这种模式下，P0具有内部上拉电阻。
at89c52单片机简介中英文对照外文翻译文献
at89c52单片机简介中英文对照外文翻译文献中英文资料对照外文翻译A T89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。
Storage RAM immediately﹑memoy read ROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。
Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。
单片机外文翻译--8位8字节闪存单片机AT89C52
电子与信息工程学院本科毕业论文(设计)外文文献翻译译文题目： 8-bit Microcontroller With 8K Bytes Flash AT89C52 学生姓名：专业：电气工程及其自动化指导教师：2012年11月外文资料8-bit Microcontroller With 8K Bytes Flash AT89C52FeaturesCompatible with MCS-51™ Products8K Bytes of In-System Reprogrammable Flash MemoryEndurance: 1,000 Write/Erase CyclesFully Static Operation: 0 Hz to 24 MHzThree-level Program Memory Lock256 x 8-bit Internal RAM32 Programmable I/O LinesThree 16-bit Timer/CountersEight Interrupt SourcesProgrammable Serial ChannelLow-power Idle and Power-down ModesDescriptionThe AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 outputbuffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memories that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memories that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V CC for internal program executions. This pin also receives the 12-volt programming enable voltage (V PP) during Flash programming when 12-volt programming is selected.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shown in the Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 RegistersControl and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2in 16-bit capture mode or 16-bit auto-reload mode.Interrupt RegistersThe individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Data MemoryThe AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H .MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON.Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2 can generate an interrupt. The capture mode is illustrated inAuto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD. Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.外文资料译文：8位8字节闪存单片机AT89C52主要性能●与MCS-51单片机产品兼容●8K字节在系统可编程Flash存储器●1000次擦写周期●全静态操作：0Hz～24Hz●三级加密程序存储器●256×8位内部存储器●32个可编程I/O口线●三个16位定时器/计数器●八个中断源●可编程串行通道●低功耗空闲和掉电模式功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K内置可编程闪存。
AT89S52-毕业设计外文资料翻译
外文原文AT89S52Features• Compatible with MCS-51® Products• 8K Bytes of In-System Programmable (ISP) Flash Memory• 1000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 33 MHz• Three-level Program Memory Lock• 256 x 8-bit Internal RAM• 32 Programmable I/O Lines• Three 16-bit Timer/Counters• Eight Interrupt Sources• Full Duplex UART Serial Channel• Low-power Idle and Power-down Modes• Interrupt Recovery from Power-down Mode• Watchdog Timer• Dual Data Pointer• Power-off FlagDescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combining a versatile 8-bit CPU with in system programmable Flash on a monolithicchip, the Atmel AT89S52 is a powerful icrocontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following tandard features:沈阳农业大学学士学位论文外文翻译8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin ConfigurationsBlock DiagramAT89S52Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance Inputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during ccesses to external program and data memory. In this mode, P0 has int -ernal pullups.沈阳农业大学学士学位论文外文翻译Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur -ing program verification.External pullups are required during program veri- fication.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the ti -mer/counter 2 exte- rnal count input (P1.0/T2) and the timer/counter 2 trigger input(P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses toexternal data memory that use 16-bit ddresses (MOVXAT89S52@ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins,they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature沈阳农业大学学士学位论文外文翻译is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ- ency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has no effect if the microco- ntroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to external program memory.When the AT89S52 is executing code from external program memory, PSENis activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be ternally latched on reset.EA should be strapped to VCC for internal rogram executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the nternal clock operatingAT89S52circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or nactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H , RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Timer 2 Operating ModesIn the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high沈阳农业大学学士学位论文外文翻译in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To nsure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, whichdisables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemented.User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Reference data:1. the ATMEL company AT89S52 technical manuals2.Shenzhen Development Co., Ltd. AT89C52 Datasheets source SCM3.Fudan University Press, single-chip microprocessor theory, application and testZHANG You-de, etc.AT89S52外文翻译AT89S52主要性能●与MCS-51单片机产品兼容●8K字节在系统可编程Flash存储器●1000次擦写周期●全静态操作：0Hz～33Hz●三级加密程序存储器●32个可编程I/O口线●三个16位定时器/计数器●八个中断源●全双工UART串行通道●低功耗空闲和掉电模式●掉电后中断可唤醒●看门狗定时器●双数据指针●掉电标识符功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程Flash 存储器。
基于at89s52单片机的超声波测距设计的外文翻译
外文资料原文Ultrasonric distance meteDocument Type and Number:United States Patent 5442592Abstract:An ultrasonic distance meter cancels out the effects of temperature and humidity variations by including a measuring unit and a reference unit. In each of the units, a repetitive series of pulses is generated, each having a repetition rate directly related to the respective distance between an electroacoustic transmitter and an electroacoustic receiver. The pulse trains are provided to respective counters, and the ratio of the counter outputs is utilized to determine the distance being measured.Publication Date:08/15/1995.Primary Examiner:Lobo, Ian J.A.BACKGROUND OF THE INVENTIONThis invention relates to apparatus for the measurement of distance and, more particularly, to such apparatus which transmits ultrasonic waves between two points.Precision machine tools must be calibrated. In the past, this has been accomplished utilizing mechanical devices such as calipers, micrometers, and the like. However, the use of such devices does not readily lend itself to automation techniques. It is known that the distance between two points can be determined by measuring the propagation time of a wave travelling between those two points. One such type of wave is an ultrasonic, or acoustic, wave. When an ultrasonic wave travels between two points, the distance between the two points can be measured by multiplying the transit time of the wave by the wave velocity in the medium separating the two points. It is therefore an object of the present invention to provide apparatus utilizing ultrasonic waves to accurately measure the distance between two points.When the medium between the two points whose spacing is being measured is air, the sound velocity is dependent upon the temperature and humidity of the air. It is therefore a further object of the,present invention to provide apparatus of the type described which is independent of temperature and humidity variations.B.SUMMARY OF THE INVENTIONThe foregoing and additional objects are attained in accordance with the principles of this invention by providing distance measuring apparatus which includes a reference unit and a measuring unit. The reference and measuring units are the same and each includes an electroacoustic transmitter and an electroacoustic receiver. The spacing between the transmitter and the receiver ofthe reference unit is a fixed reference distance, whereas the spacing between the transmitter and receiver of the measuring unit is the distance to be measured. In each of the units, the transmitter and receiver are coupled by a feedback loop which causes the transmitter to generate an acoustic pulse which is received by the receiver and converted into an electrical pulse which is then fed back to the transmitter, so that a repetitive series of pulses results. The repetition rate of the pulses is inversely related to the distance between the transmitter and the receiver. In each of the units, the pulses are provided to a counter. Since the reference distance is known, the ratio of the counter outputs is utilized to determine the desired distance to be measured. Since both counts are identically influenced by temperature and humidity variations, by taking the ratio of the counts, the resultant measurement becomes insensitive to such variations.C.DETAILED DESCRIPTIONA.principle of ultrasonic distance measurement1, the principle of piezoelectric ultrasonic generatorPiezoelectric ultrasonic generator is the use of piezoelectric crystal resonators to work. Ultrasonic generator, the internal structure as shown in Figure 1, it has two piezoelectric chip and a resonance plate. When it's two plus pulse signal, the frequency equal to the intrinsic piezoelectric oscillation frequency chip, the chip will happen piezoelectric resonance, and promote the development of plate vibration resonance, ultrasound is generated. Conversely, if the two are not inter-electrode voltage, when the board received ultrasonic resonance, it will be for vibration suppression of piezoelectric chip, the mechanical energy is converted to electrical signals, then it becomes the ultrasonic receiver.The traditional way to determine the moment of the echo's arrival is based on thresholding the received signal with a fixed reference. The threshold is chosen well above the noise level, whereas the moment of arrival of an echo is defined as the first moment the echo signal surpasses that threshold. The intensity of an echo reflecting from an object strongly depends on the object's nature, size and distance from the sensor. Further, the time interval from the echo's starting point to the moment when it surpasses the threshold changes with the intensity of the echo. As a consequence, a considerable error may occur Even two echoes with different intensities arriving exactly at the same time will surpass the threshold at different moments. The stronger one will surpass the threshold earlier than the weaker, so it will be considered as belonging to a nearer object.2, the principle of ultrasonic distance measurementUltrasonic transmitter in a direction to launch ultrasound, in the moment to launch the beginning of time at the same time, the spread of ultrasound in the air, obstacles on his way to return immediately, the ultrasonic reflected wave received by the receiver immediately stop the clock. Ultrasound in the air as the propagation velocity of 340m / s, according to the timer records the timet, we can calculate the distance between the launch distance barrier (s), that is: s = 340t / 2B.Ultrasonic Ranging System for the Second Circuit DesignSystem is characterized by single-chip microcomputer to control the use of ultrasonic transmitter and ultrasonic receiver since the launch from time to time, single-chip selection of 8751, economic-to-use, and the chip has 4K of ROM, to facilitate programming. Circuit schematic diagram shown in Figure 2. Draw only the front range of the circuit wiring diagram, left and right in front of Ranging Ranging circuits and the same circuit, it is omitted.1,40 kHz ultrasonic pulse generated with the launchRanging system using the ultrasonic sensor of piezoelectric ceramic sensors UCM40, its operating voltage of the pulse signal is 40kHz, which by the single-chip implementation of the following procedures to generate.puzel: mov 14h, # 12h; ultrasonic firing continued 200mshere: cpl p1.0; output 40kHz square wavenop;nop;nop;djnz 14h, here;retRanging in front of single-chip termination circuit P1.0 input port, single chip implementation of the above procedure, the P1.0 port in a 40kHz pulse output signal, after amplification transistor T, the drive to launch the first ultrasonic UCM40T, issued 40kHz ultrasonic pulse, and the continued launch of 200ms. Ranging the right and the left side of the circuit, respectively, then input port P1.1 and P1.2, the working principle and circuit in front of the same location.2, reception and processing of ultrasonicUsed to receive the first launch of the first pair UCM40R, the ultrasonic pulse modulation signal into an alternating voltage, the op-amp amplification IC1A and after polarization IC1B to IC2. IC2 is locked loop with audio decoder chip LM567, internal voltage-controlled oscillator center frequency of f0 = 1/1.1R8C3, capacitor C4 determine their target bandwidth. R8-conditioning in the launch of the carrier frequency on the LM567 input signal is greater than 25mV, the output from the high jump 8 feet into a low-level, as interrupt request signals to the single-chip processing.Ranging in front of single-chip termination circuit output port INT0 interrupt the highest priority, right or left location of the output circuit with output gate IC3A access INT1 port single-chip, while single-chip P1.3 and P1. 4 received input IC3A, interrupted by the process to identify the source of inquiry to deal with, interrupt priority level for the first left right after. Part of the source code is as follows:receive1: push pswpush accclr ex1; related external interrupt 1jnb p1.1, right; P1.1 pin to 0, ranging from right to interrupt service routine circuitjnb p1.2, left; P1.2 pin to 0, to the left ranging circuit interrupt service routine return: SETB EX1; open external interrupt 1pop accpop pswretiright: ...; right location entrance circuit interrupt service routineAjmp Returnleft: ...; left Ranging entrance circuit interrupt service routineAjmp Return3, the calculation of ultrasonic propagation timeWhen you start firing at the same time start the single-chip circuitry within the timer T0, the use of timer counting function records the time and the launch of ultrasonic reflected wave received time. When you receive the ultrasonic reflected wave, the receiver circuit outputs a negative jump in the end of INT0 or INT1 interrupt request generates a signal, single-chip microcomputer in response to external interrupt request, the implementation of the external interrupt service subroutine, read the time difference, calculating the distance . Some of its source code is as follows:RECEIVE0: PUSH PSWPUSH ACCCLR EX0; related external interrupt 0MOV R7, TH0; read the time valueMOV R6, TL0CLR CMOV A, R6SUBB A, # 0BBH; calculate the time differenceMOV 31H, A; storage resultsMOV A, R7SUBB A, # 3CHMOV 30H, ASETB EX0; open external interrupt 0POP ACCPOP PSWRETIFor a flat target, a distance measurement consists of two phases: a coarse measurement and. a fine measurement:Step 1: Transmission of one pulse train to produce a simple ultrasonic wave.Step 2: Changing the gain of both echo amplifiers according to equation , until the echo is detected.Step 3: Detection of the amplitudes and zero-crossing times of both echoes.Step 4: Setting the gains of both echo amplifiers to normalize the output at, say 3 volts. Setting the period of the next pulses according to the : period of echoes. Setting the time window according to the data of step 2.Step 5: Sending two pulse trains to produce an interfered wave. Testing the zero-crossing times and amplitudes of the echoes. If phase inversion occurs in the echo, determine to otherwise calculate to by interpolation using the amplitudes near the trough. Derive t sub m1 and t sub m2 .Step 6: Calculation of the distance y using equation .D.Fourth, the ultrasonic ranging system software designSoftware is divided into two parts, the main program and interrupt service routine, shown in Figure 3 (a) (b) (c) below. Completion of the work of the main program is initialized, each sequence of ultrasonic transmitting and receiving control.Interrupt service routines from time to time to complete three of the rotation direction of ultrasonic launch, the main external interrupt service subroutine to read the value of completion time, distance calculation, the results of the output and so on..System initialization after the start timer T1 starts counting from 0 to enter the main program to wait for the T1 overflow into the T1 interrupt service routine when the time is reached; T1 interrupt service routine will start a new ultrasonic transmitting, the square wave will be generated in the P1.0 pin at the same time open the timer T0 timing, in order to avoid the diffraction of the direct wave, the delay 1ms and then, after the INT0 interrupt Enable; the INT0 interrupt to allow open, if thisoccurs when the low is representative of the received echo signal, the interrupt request to INT0 interrupt service routine, the INT0 interrupt service routine will stop the timer T0 timing, read the time value of T0 timer to the appropriate storage area.set to receive a sign of success; main program detects reception hallmarks of success, the temperature subroutine is called, collecting the ambient temperature when the ultrasonic ranging, and converted the accurate speed of sound stored in RAM storage unit; SCM calls the distance calculationsubroutine to calculate, calculate the distance between the sensor to the target object; since the main program calls the display subroutine to display; after completion of the first launch, receive, display, the system will delay 100ms re-T1 setinitial value againstart T1 to overflow into the next ranging. If the obstacle is too far beyond the range that T0 overflow has not yet received echo "ERROR" is displayed back to the main flow into a new round of tests.E. CONCLUSIONSRequired measuring range of 30cm ~ 200cm objects inside the plane to do a number of measurements found that the maximum error is 0.5cm, and good reproducibility. Single-chip design can be seen on the ultrasonic ranging system has a hardware structure is simple, reliable, small features such as measurement error. Therefore, it can be used not only for mobile robot can be used in other detection systems.Thoughts: As for why the receiver do not have the transistor amplifier circuit, because the magnification well, CX20106 integrated amplifier, but also with automatic gain control level, magnification to 76dB, the center frequency is 38k to 40k, is exactly resonant ultrasonic sensors frequency外文资料译文超声波测距仪文件类型和数目：美国专利5442592摘要：提出了一种可以抵消温度的影响和湿度的变化的新型超声波测距仪，包括测量单元和参考资料。
AT89S52单片机中英文对照外文翻译文献
(文档含英文原文和中文翻译)中英文资料对照外文翻译英文原文：The Description of MCUMCU DescriptionSCM is also known as micro-controller (Microcontroller Unit), commonly used letters of the acronym MCU MCU that it was first used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor. The first design is by a large number of peripherals and CPU on a chip in the computer system, smaller, more easily integrated into a complex and demanding on the volume control device which. INTEL's Z80 is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors have parted ways.Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, because the cost is not satisfactory but have not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90's dedicated processor, while the average model prices fall to one U.S. dollars, the most high-end [1] model only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems.SCM is more suitable than the specific processor used in embedded systems, so it was up to the application. In fact the number of SCM is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will be integrated single chip. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse with a 1-2 in both the Department of SCM. Personal computer will have a large number of SCM in the work. General car with more than 40 SCM, complex industrial control systems may even have hundreds of SCM in the same time work! SCM is not only far exceeds the number of PC and other computing the sum, or even more than the number of human beingsSingle chip, also known as single-chip microcontroller, it is not complete a certain logic chips, but to a computer system integrated into a chip. Equivalent to a micro-computer, and computer than just the lack of a microcontroller I / O devices. General talk: a chip becomes a computer. Its small size, light weight, cheap, for the study, application and development of facilities provided. At the same time, learning to use the MCU is to understand the principle and structure of the computer the best choice.SCM and the computer functions internally with similar modules, such as CPU, memory, parallel bus, the same effect as well, and hard disk memory devices, and different is its performance of these components were relatively weak many of our home computer, but the price is low , usually not more than 10 yuan you can do with it ...... some control for a class is not very complicated electrical work is enough of. We are using automatic drum washing machine, smoke hood, VCD and so on appliances which could see its shadow! ...... It is primarily as a control section of the core componentsIt is an online real-time control computer, control-line is that the scene is needed is a stronger anti-jamming ability, low cost, and this is, and off-line computer (such as home PC), the main difference.Single chipMCU is through running, and can be modified. Through different procedures to achieve different functions, in particular special unique features, this is another device much effort needs to be done, some great efforts are very difficult to do. A not very complex functions if the 50's with the United States developed 74 series, or the 60's CD4000 series of these pure hardware buttoned, then the circuit must be a large PCB board! But if the United States if the 70's with a series of successful SCM market, the result will be a drastic change! Just because you are prepared by microcomputer programs can achieve high intelligence, high efficiency and high reliability!As the microcontroller on the cost-sensitive, so now the dominant software or the lowest level assembly language, which is the lowest level in addition to more than binary machine code language, and as so low why is the use? Many high-level language has reached the level of visual programming Why is not it? The reason is simply that there is no home computer as a single chip CPU, not as hard as a mass storage device. A visualization of small high-level language program which even if only one button, will reach tens of K of size! For the home PC's hard drive in terms of nothing, but in terms of the MCU is not acceptable. SCM in the utilization of hardware resources to be very high for the job so although the original is still in the compilation of a lot of use. The same token, if the giant computer operating system and applications run up to get home PC, home PC, also can not afford to.Can be said that the twentieth century across the three "power" era, that is, the age of electricity, the electronic age and has entered into the computer age. However, this computer, usually refers to the personal computer, referred to as PC. It consists of thehost, keyboard, monitor and other components. Another type of computer, most people do not know how. This computer is to give all kinds of intelligent machines single chip (also known as micro-controller). As the name suggests, this computer system took only a minimal integrated circuit, can be a simple operation and control. Because it is small, usually hidden in the charged mechanical "stomach" in. It is in the device, like the human brain plays a role, it goes wrong, the whole plant was paralyzed. Now, this microcontroller has a very broad field of use, such as smart meters, real-time industrial control, communications equipment, navigation systems, and household appliances. Once all kinds of products were using SCM, can serve to upgrade the effectiveness of products, often in the product name preceded by the adjective - "intelligent," such as intelligent washing machines. Now some technical personnel of factories or other amateur electronics developers to engage in out of certain products, not the circuit is too complicated, that function is too simple and can easily be copied. The reason may be stuck in the product did not use a microcontroller or other programmable logic device.SCM historySCM was born in the late 20th century, 70, experienced SCM, MCU, SoC three stages.First model1.SCM the single chip microcomputer (Single Chip Microcomputer) stage, mainly seeking the best of the best single form of embedded systems architecture. "Innovation model" success, laying the SCM and general computer completely different path of development. In the open road of independent development of embedded systems, Intel Corporation contributed.2.MCU the micro-controller (Micro Controller Unit) stage, the main direction of technology development: expanding to meet the embedded applications, the target system requirements for the various peripheral circuits and interface circuits, highlight the object of intelligent control. It involves the areas associated with the object system, therefore, the development of MCU's responsibility inevitably falls on electrical, electronics manufacturers. From this point of view, Intel faded MCU development has its objective factors. In the development of MCU, the most famous manufacturers as the number of Philips Corporation.Philips company in embedded applications, its great advantage, the MCS-51 single-chip micro-computer from the rapid development of the micro-controller. Therefore, when we look back at the path of development of embedded systems, do notforget Intel and Philips in History.Embedded SystemsEmbedded system microcontroller is an independent development path, the MCU important factor in the development stage, is seeking applications to maximize the solution on the chip; Therefore, the development of dedicated single chip SoC trend of the natural form. As the microelectronics, IC design, EDA tools development, application system based on MCU SoC design have greater development. Therefore, the understanding of the microcontroller chip microcomputer can be, extended to the single-chip micro-controller applications.MCU applicationsSCM now permeate all areas of our lives, which is almost difficult to find traces of the field without SCM. Missile navigation equipment, aircraft, all types of instrument control, computer network communications and data transmission, industrial automation, real-time process control and data processing, extensive use of various smart IC card, civilian luxury car security system, video recorder, camera, fully automatic washing machine control, and program-controlled toys, electronic pet, etc., which are inseparable from the microcontroller. Not to mention the area of robot control, intelligent instruments, medical equipment was. Therefore, the MCU learning, development and application of the large number of computer applications and intelligent control of the scientists, engineers.The single-chip microcomputer AT89S52 MCU as an example, the pair for further description:AT89S52 MCUFeatures• Compatible with MCS-51 Products• 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 10,000 Write/Erase Cycles• 4.0V to 5.5V Operating Range• Fully Static Operation: 0 Hz to 33 MHz• Three-level Program Memory Lock• 256 x 8-bit Internal RAM• 32 Programmable I/O Lines• Three 16-bit Timer/Counters• Eight Interrupt Sources• Full Duplex UART Serial Channel• Low-power Idle and Power-down Modes• Interrupt Recov ery from Power-down Mode• Watchdog Timer • Dual Data Pointer• Power-off Flag • Fast Programming Time• Flexible ISP Programming (Byte and Page Mode)• Green (Pb/Halide-free) Packaging Option1.DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.2.Pin DescriptionVCC ：Supply voltage.GND ：Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, eachpin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX@ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing orclocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to exter-nal data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.3.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.3.1 Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.3.2 Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.4.Watchdog Timer (One-time Enabled with Reset-out)The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.4.1 Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.4.2 WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.5. UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, please click on the document link below:/dyn/resources/prod_documents/DOC4316.PDF6. Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below:/dyn/resources/prod_documents/DOC4316.PDF7. Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.7.1 Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.7.2 Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD . Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.8. Baud Rate GeneratorTimer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the fol -lowing equation.The Timer can be configured for either timer or counter operation. In most applications, it is con-figured for timer operation (CP/T2 = 0). The timer operation is Timer 2 Overflow Rate Modes 1 and 3 Baud Rates = 16different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter-rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.9. Programmable Clock OutA 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously. Note, however, Modes 1 and 3Oscillator Frequency Baud Rate 32[65536-RCAP2H,RCAP2L]=⨯Oscilator Frequency Clock-Out Frequency=4[65536-(RCAP2H,RCAP2L)]⨯。
基于AT89S52单片机控制的太阳能充电器(硬件)设计附外文文献及译文
中国矿业大学本科生毕业设计附外文文献及翻译基于MC-SILICON的双面太阳能电池在工业环境中的实现姓名：学号：学院：信息与电气工程学院专业：电气工程与自动化设计题目：单片机控制的太阳能充电器（硬件）专题：指导教师：职称：副教授摘要在污染和能源口趋紧张的背景下，太阳能作为一种新型的绿色可再生能源，具有储量大、利用经济、清洁环保等优点。
因此，太阳能的利用越来越受到人们的重视。
本文试图设计一种切实可行的太阳能充电控制器，通过对蓄电池充电，满足小功率的用户需求。
本文重点研究了用AT89S52实现太阳能充电控制技术。
详细介绍了100瓦太阳能电池板向12伏蓄电池充电的太阳能控制器硬件系统，包括系统的硬件电路设计、各部分电路的功能、工作原理和电子元器件型号的选取。
硬件系统由直流稳压电源电路，A/D实现对蓄电池端电压的动态监测及转换、AT89S52控制以及输出继电器开关电路四个部分组成，完成了整个太阳能充电控制器电路原理图的设计和制作。
用PROTEUS仿真软件进行了电路仿真，并且制作了相应的电路板。
但是由于时间关系，没能完成实物的实验测试。
本文还对太阳能电池的结构原理、太阳能电池板的伏安特性、常用的铅酸蓄电池原理及工作情况作了详细介绍，并在此基础上介绍常用的蓄电池充电方法。
关键词：太阳能；蓄电池；充电控制；AT89S52；ADC0809ABSTRACTAgainst the background of energy shortage and its pollution, solar energy as a new kind of energy has a lot of advantages such as large reserves, economic, cleanliness and so on. So, people begin to pay more attention to the use of solar energy. The paper designs a feasible solar energy charging controller and storage batteries are charged to meet the needs of low-power users.This article focuses on the use of single-chip realization of solar charge control technology. 100-watt solar panels to 12-volt solar battery charge controller hardware system is detailed, including system hardware circuit design, the various parts of the circuit functions, working principles and models of selected electronic components. Hardware system is composed of four parts, which are DC regulated power supply circuit, A / D to achieve on the battery terminal voltage of the dynamic monitoring and conversion, AT89S52 relay control and output switching circuit. And finish the entire solar charge controller circuit schematic design and production. PROTEUS simulation with circuit simulation software was accomplished, and a corresponding circuit board was produced. However, due to time constraints, failed to complete the kind of experimental test.In this paper, also the structure of the principle of solar cells, solar panels of the Volta metric characteristics of lead-acid batteries commonly used in the work of principle was detailed, and the basis of methods commonly used on rechargeable batteries was introduced.Key words: solar; battery; charge control; AT89S52; ADC0809目录摘要 (i)ABSTRACT (ii)1 绪论 (1)1.1 课题研究背景 (1)1.1.1 当前面临的能源和环境问题 (1)1.1.2 太阳能的开发和利用 (2)1.1.3 光伏发电的特点 (3)1.2 蓄电池充电系统 (3)1.2.1充电器的发展及其简单的类型 (3)1.2.2 太阳能充电器 (4)1.3 本课题研究的主要内容 (5)2 太阳能电池的研究和分析 (6)2.1 太阳能电池的原理 (6)2.2 太阳能电池的分类 (6)2.3 太阳能电池的等效电路 (7)2.4 太阳能电池板的输出特性及影响因素 (8)2.4.1光伏电池的主要参数 (8)2.4.2太阳的光照强度对光伏电池转换效率的影响 (10)2.4.3 温度对光伏电池输出特性的影响 (10)2.4.4 本系统所采用的光伏电池 (11)2.5 本章小结 (12)3 蓄电池 (13)3.1 蓄电池的概念及其一般特性 (13)3.1.1 电池的定义 (13)3.1.2 主要参数指标 (13)3.1.3 充放电特性 (15)3.2 铅酸蓄电池 (16)3.2.1 铅酸蓄电池的电极反应 (17)3.2.2 铅酸蓄电池的充放电特性 (18)3.3 太阳能----蓄电池充电技术研究 (20)3.3.1 恒流充电 (20)3.3.2 恒压充电 (21)3.3.3 恒压限流充电 (22)3.3.4 两阶段、三阶段充电 (22)3.3.5 快速充电 (22)3.3.6 智能充电 (23)3.4 本章小结 (23)4 太阳能充电控制器的研究及设计 (24)4.1太阳能充电器原理 (24)4.1.1 主控芯片的设计 (24)4.1.2 模数转换模块ADC0809简介 (28)4.1.3 电源模块的设计 (30)4.1.4 分频器的设计 (30)4.1.5 外围电路的设计 (30)4.1.6ADC0809与AT89S52接口 (32)4.1.7 74LS00 (33)4.2 单片机的防干扰技术 (35)4.2.1干扰分析 (35)4.2.2硬件抗干扰方法 (36)4.3 系统的软件设计概述 (37)4.4 本章小结 (39)5 结论 (40)5.1 全文工作总结 (40)5.2 进一步工作设想 (40)致谢 (42)参考文献 (43)翻译部分 (45)中文译文 (45)英文原文 (53)1 绪论1.1 课题研究背景1.1.1 当前面临的能源和环境问题[1,2,3,4]能源犹如人体的血液。
毕业设计(论文)单片机英文中文翻译论文
毕业设计（论文）单片机英文中文翻译论文AT89S52FeaturesCompatible with MCS-51 Products8K Bytes of In-System Programmable ISP Flash Memory –Endurance 10000 WriteErase Cycles40V to 55V Operating RangeFully Static Operation 0 Hz to 33 MHzThree-level Program Memory Lock256 x 8-bit Internal RAM32 Programmable IO LinesThree 16-bit TimerCountersEight Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog Timer Dual Data PointerPower-off Flag Fast Programming TimeFlexible ISP Programming Byte and Page ModeGreen PbHalide-free Packaging OptionDescriptionThe AT89S52 is a low-power high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applicationsThe AT89S52 provides the following standard features 8K bytes of Flash 256 bytes of RAM 32 IO lines Watchdog timer two data pointers three 16-bit timercounters a six-vector two-level interrupt architecture a full duplex serial port on-chip oscillator and clock circuitry In addition the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes The Idle Mode stops the CPU while allowing the RAM timercounters serial port and interrupt system to continue functioning The Power-down mode saves the RAM con-tents but freezes the oscillator disabling all other chip functions until the next interrupt or hardware resetPin Description21 VCC Supply voltage22 GND Ground23 Port 0Port 0 is an 8-bit open drain bidirectional IO port As an output port each pin can sink eight TTL inputs When 1s are written to port 0 pins the pins can be used as high-impedance inputs Port 0 can also be configured to be the multiplexed low-order addressdata bus during accesses to external program and data memory In this mode P0 has internal pull-ups Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification External pull-ups are required during program verification24 Port 1Port 1 is an 8-bit bidirectional IO port with internal pull-ups The Port 1 output buffers can sinksource four TTL inputs When 1s are written to Port 1 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current IIL because of the internal pull-ups In addition P10 and P11 can be configured to be the timercounter 2 external count input P10T2 and the timercounter 2 trigger input P11T2EX respectively as shown in the follow-ing tablePort 1 also receives the low-order address bytes during Flash programming and verificationPort Pin Alternate Functions P10 T2 external count input to TimerCounter 2 clock-out P11 T2EX TimerCounter 2 capturereloadtrigger and direction control P15 MOSI used for In-System Programming P16 MISO used for In-System Programming P17 SCK used for In-System Programming 25 Port 2Port 2 is an 8-bit bidirectional IO port with internal pull-ups The Port 2 output buffers can sinksource four TTL inputs When 1s are written to Port 2 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current IIL because of the internal pull-ups Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses MOVX DPTR In this application Port 2 uses strong internal pull-ups when emitting 1s During accesses to external data memory that use 8-bit addresses MOVX RI Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification26 Port 3Port 3 is an 8-bit bidirectional IO port with internal pull-ups The Port 3 output buffers can sinksource four TTL inputs When 1s are written to Port 3 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current IIL because of the pull-ups Port 3 receives some control signals for Flash programming and verification Port 3 also serves the functions of various special features of the AT89S52as shown in the fol-lowing tablePort Pin Alternate Functions P30 RXD serial input portP31 TXD serial output port P32 external interrupt 0P33 external interrupt 1 P34 T0 timer 0 external inputP35 T1 timer 1 external input P36 external data memory write strobe P37 external data memory read strobe 27 RSTReset input A high on this pin for two machine cycles while the oscillator is running resets the device This pin drives high for 98 oscillator periods after the Watchdog times out The DISRTO bit in SFR AUXR address 8EH can be used to disable this feature In the default state of bit DISRTO the RESET HIGH out feature is enabled28 ALEAddress Latch Enable ALE is an output pulse for latching the low byte of the address during accesses to external memory This pin is also the program pulse input during Flash programming In normal operation ALE is emitted at a constant rate of 16 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped dur-ing each access to external data memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With the bit set ALE is active only during a MOVX or MOVC instruction Otherwise the pin is weakly pulled high Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode29 Program Store Enable is the read strobe to external programmemory When the AT89S52 is executing code from external program memory is activated twice each machine cycle except that two activations are skipped during each access to exter-nal data memory210 VPPExternal Access Enable must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed will be internally latched on reset should be strapped to VCC for internal program executions This pin also receives the 12-volt programming enable voltage VPP during Flash programming 211 XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit212 XTAL2Output from the inverting oscillator amplifierMemory OrganizationMCS-51 devices have a separate address space for Program and Data Memory Up to 64K bytes each of external Program and Data Memory can be addressed31 Program MemoryIf the pin is connected to GND all program fetches are directed to external memory On the AT89S52 if is connected to VCC program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory32 Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM The upper 128 bytes occupy a parallel address space to the Special Function Registers This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space When an instruction accesses an internal location above address 7FH the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space Instructions which use direct addressing access the SFR space For example the following direct addressing instruction accesses the SFR at location 0A0H which is P2MOV 0A0H dataInstructions that use indirect addressing access the upper 128 bytes of RAM For example the following indirect addressing instruction where R0 contains 0A0H accesses the data byte at address 0A0H rather than P2 whose address is 0A0HMOV R0 dataNote that stack operations are examples of indirect addressing so the upper 128 bytes of data RAM are available as stack spaceWatchdog Timer One-time Enabled with Reset-outThe WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets The WDT consists of a 14-bit counter and the Watchdog Timer Reset WDTRST SFR The WDT is defaulted to disable from exiting reset To enable the WDT a user must write 01EH and 0E1H insequence to the WDTRST register SFR location 0A6H When the WDT is enabled it will increment every machine cycle while the oscillator is running The WDT timeout period is dependent on the external clock frequency There is no way to disable the WDT except through reset either hardware reset or WDT overflow reset When WDT over-flows it will drive an output RESET HIGH pulse at the RST pin41 Using the WDTTo enable the WDT a user must write 01EH and 0E1H in sequence to the WDTRST register SFR location 0A6H When the WDT is enabled the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow The 14-bit counter overflows when it reaches 16383 3FFFH and this will reset the device When the WDT is enabled it will increment every machine cycle while the oscillator is running This means the user must reset the WDT at least every 16383 machine cycles To reset the WDT the user must write 01EH and 0E1H to WDTRST WDTRST is a write-only register The WDT counter cannot be read or written When WDT overflows it will generate an output RESET pulse at the RST pin The RESET pulse dura-tion is 98xTOSC where TOSC 1FOSC To make the best use of the WDT it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset42 WDT During Power-down and IdleIn Power-down mode the oscillator stops which means the WDT also stopsWhile in Power-down mode the user does not need to service the WDT There are two methods of exiting Power-down mode by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode When Power-down is exited with hardware reset servicing the WDT should occur as it normally does whenever the AT89S52 is reset Exiting Power-down with an interrupt is significantly different The interrupt is held low long enough for the oscillator to stabilize When the interrupt is brought high the interrupt is serviced To prevent the WDT from resetting the device while the interrupt pin is held low the WDT is not started until the interrupt is pulled high It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode To ensure that the WDT does not overflow within a few states of exiting Power-down it is best to reset the WDT just before entering Power-down mode Before going into the IDLE mode the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled The WDT keeps counting during IDLE WDIDLE bit 0 as the default state To prevent the WDT from resetting the AT89S52 while in IDLE mode the user should always set up a timer that will periodically exit IDLE service the WDT and reenter IDLE mode With WDIDLE bit enabled the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE5 UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C526 Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C527 Timer 2Timer 2 is a 16-bit TimerCounter that can operate as either a timer or an event counter The type of operation is selected by bit C in the SFR T2CON Timer 2 has three operating modes capture auto-reload up or down counting and baud rate generator The modes are selected by bits in T2CON as shown in Table 6-1 Timer 2 consists of two 8-bit registers TH2 and TL2 In the Timer function the TL2 register is incremented every machine cycle Since a machine cycle consists of 12 oscillator periods the count rate is 112 of the oscil-lator frequencyTable 6-1 Timer 2 Operating ModesRCLK TCLK CP TR2 MODE 0 0 1 16-bit Auto-reload 01 1 16-bit Capture 1 X 1 Baud Rate Generator XX 0 Off In the Counter function the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in theregister during S3P1 of the cycle following the one in which the transition was detected Since two machine cycles 24 oscillator periods are required to recognize a 1-to-0 transition the imum count rate is 124 of the oscillator frequency To ensure that a given level is sampled at least once before it changes the level should be held for at least one full machine cycle71 Capture ModeIn the capture mode two options are selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON This bit can then be used to generate an interrupt If EXEN2 1 Timer 2 performs the same operation but a 1-to-0 transi-tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set The EXF2 bit like TF2 can generate an interrupt72 Auto-reload Up or Down CounterTimer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode This feature is invoked by the DCEN Down Counter Enable bit located in the SFR T2MOD Upon reset the DCEN bit is set to 0 so that timer 2 will default to count up When DCEN is set Timer 2 can count up or down depending on the value of the T2EX pin Timer 2 automatically counting up when DCEN 0 In this mode two options areselected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software If EXEN2 1 a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX This transition also sets the EXF2 bit Both the TF2 and EXF2 bits can generate an interrupt if enabled Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 10-2 In this mode the T2EX pin controls the direction of the count A logic 1 at T2EX makes Timer 2 count up The timer will overflow at 0FFFFH and set the TF2 bit This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers TH2 and TL2 respectively A logic 0 at T2EX makes Timer 2 count down The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution In this operating mode EXF2 does not flag an interrupt8 Baud Rate GeneratorTimer 2 is selected as the baud rate generator by setting TCLK andor RCLK in T2CON Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer1 is used for the other function Setting RCLK andor TCLK puts Timer2 into its baud rate generator mode The baud rate generator mode is similar to the auto-reload mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L which are preset by software The baud rates in Modes 1 and3 are determined by Timer 2s overflow rate according to the fol-lowing equation The Timer can be configured for either timer or counter operation In most applications it is con-figured for timer operation CP 0 The timer operation is different for Timer 2 when it is used as a baud rate generator Normally as a timer it increments every machine cycle at 112 the oscillator frequency As a baud rate generator however it increments every state time at 12 the oscillator frequency9 Programmable Clock OutA 50 duty cycle clock can be programmed to come out on P10 This pin besides being a regular IO pin has two alternate functions It can be programmed to input the external clock for TimerCounter 2 or to output a 50 duty cycle clock ranging from 61 Hz to 4 MHz for a 16-MHz operating frequency To configure the TimerCounter 2 as a clock generator bit C T2CON1 must be cleared and bit T2OE T2MOD1 must be set Bit TR2 T2CON2 starts and stops the timer The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in the following equationIn the clock-out mode Timer 2 roll-overs will not generate an interrupt This behavior is similar to when Timer 2 is used as a baud-rate generator It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously Note however that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L10 InterruptsThe AT89S52 has a total of six interrupt vectors two external interrupts and three timer interrupts Timers 0 1 and 2 and the serial port interrupt Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE IE also contains a global disable bit EA which disables all interrupts at once Note that bit position IE6 is unimplemented User software should not write a 1 to this bit position since it may be used in future AT89 products Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON Nei-ther of these flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and that bit will have to be cleared in software The Timer 0 and Timer 1 flags TF0 and TF1 are set at S5P2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in thesame cycle in which the timer overflows11 Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output respectively of an inverting amplifier that can be configured for use as an on-chip oscillator Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven There are no requirements on the duty cycle of the external clock signal since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop but minimum and imum voltage high and low time specifications must be observed12 Idle ModeIn idle mode the CPU puts itself to sleep while all the on-chip peripherals remain active The mode is invoked by software The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset Note that when idle mode is terminated by a hardware reset the device normally resumes pro-gram execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset the instruction following the one that invokes idle mode should notwrite to a port pin or to external memory13 Power-down ModeIn the Power-down mode the oscillator is stopped and the instruction that invokes Power-down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt Reset redefines the SFRs but does not change the on-chip RAM The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize AT89S52单片机主要性能与MCS-51单片机产品兼容8K字节在系统可编程Flash存储器1000次擦写周期全静态操作0Hz～33Hz三级加密程序存储器32个可编程IO口线三个16位定时器计数器八个中断源全双工UART串行通道低功耗空闲和掉电模式掉电后中断可唤醒看门狗定时器双数据指针掉电标识符功能特征描述AT89S52是一种低功耗高性能CMOS8位微控制器具有8K 在系统可编程Flash 存储器使用Atmel 公司高密度非易失性存储器技术制造与工业80C51 产品指令和引脚完全兼容片上Flash允许程序存储器在系统可编程亦适于常规编程器在单芯片上拥有灵巧的8 位CPU 和在系统可编程Flash使得AT89S52为众多嵌入式控制应用系统提供高灵活超有效的解决方案AT89S52具有以下标准功能 8k字节Flash256字节RAM32 位IO 口线看门狗定时器2 个数据指针三个16 位定时器计数器一个6向量2级中断结构全双工串行口片内晶振及时钟电路另外AT89S52 可降至0Hz 静态逻辑操作支持2种软件可选择节电模式空闲模式下CPU 停止工作允许RAM定时器计数器串口中断继续工作掉电保护方式下RAM内容被保存振荡器被冻结单片机一切工作停止直到下一个中断或硬件复位为止引脚功能VCC 电源GND 接地P0口 P0口是一个8位漏极开路的双向IO口作为输出口每位能驱动8个TTL逻辑电平对P0端口写1时引脚用作高阻抗输入当访问外部程序和数据存储器时P0口也被作为低8位地址数据复用在这种模式下P0具有内部上拉电阻在flash编程时P0口也用来接收指令字节在程序校验时输出指令字节程序校验时需要外部上拉电阻24 P1口P1 口是一个具有内部上拉电阻的8 位双向IO 口p1 输出缓冲器能驱动4 个TTL 逻辑电平对P1 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IIL此外P10和P12分别作定时器计数器2的外部计数输入P10T2和时器计数器2的触发输入P11T2EX具体如下表所示在flash编程和校验时P1口接收低8位地址字节引脚号第二功能P10 T2定时器计数器T2的外部计数输入时钟输出P11 T2EX定时器计数器T2的捕捉重载触发信号和方向控制P15 MOSI在系统编程用P16 MISO在系统编程用P17 SCK在系统编程用25 P2口P2 口是一个具有内部上拉电阻的8 位双向IO 口P2 输出缓冲器能驱动4 个TTL 逻辑电平对P2 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IIL在访问外部程序存储器或用16位地址读取外部数据存储器例如执行MOVX DPTR时P2 口送出高八位地址在这种应用中P2 口使用很强的内部上拉发送1在使用8位地址如MOVX RI访问外部数据存储器时P2口输出P2锁存器的内容在flash编程和校验时P2口也接收高8位地址字节和一些控制信号26 P3口P3 口是一个有内部上拉电阻的8 位双向IO 口p2 输出缓冲器能驱动4 个TTL 逻辑电平对P3 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IILP3口亦作为AT89S52特殊功能第二功能使用如下表所示在flash编程和校验时P3口也接收一些控制信号引脚号第二功能P30 RXD串行输入P31 TXD串行输出P32 外部中断0 P33 外部中断1 P34 T0定时器0外部输入P35 T1定时器1外部输入P36 外部数据存储器写选通P37 外部数据存储器写选通27 RST复位输入晶振工作时RST脚持续2 个机器周期高电平将使单片机复位看门狗计时完成后RST 脚输出96 个晶振周期的高电平特殊寄存器AUXR 地址8EH 上的DISRTO位可以使此功能无效DISRTO默认状态下复位高电平有效28 ALE地址锁存控制信号ALE是访问外部程序存储器时锁存低8 位地址的输出脉冲在flash编程时此引脚也用作编程输入脉冲在一般情况下ALE 以晶振六分之一的固定频率输出脉冲可用来作为外部定时器或时钟使用然而特别强调在每次访问外部数据存储器时ALE脉冲将会跳过如果需要通过将地址为8EH 的SFR的第0位置 1ALE操作将无效这一位置 1ALE 仅在执行MOVX 或MOVC指令时有效否则ALE 将被微弱拉高这个ALE 使能标志位地址为8EH的SFR的第0位的设置对微控制器处于外部执行模式下无效29 外部程序存储器选通信号是外部程序存储器选通信号当AT89S52从外部程序存储器执行外部代码时在每个机器周期被激活两次而在访问外部数据存储器时将不被激活210 VPP访问外部程序存储器控制信号为使能从0000H 到FFFFH的外部程序存储器读取指令必须接GND为了执行内部程序指令应该接VCC在flash编程期间也接收12伏VPP电压211 XTAL1振荡器反相放大器和内部时钟发生电路的输入端212 XTAL2振荡器反相放大器的输出端3 存储器结构MCS-51器件有单独的程序存储器和数据存储器外部程序存储器和数据存储器都可以64K寻址31 程序存储器如果引脚接地程序读取只从外部存储器开始对于89S52如果接VCC程序读写先从内部存储器地址为0000H～1FFFH开始接着从外部寻址寻址地址为2000HFFFFH32 数据存储器 AT89S52 有256 字节片内数据存储器高128 字节与特殊功能寄存器重叠也就是说高128字节与特殊功能寄存器有相同的地址而物理上是分开的当一条指令访问高于7FH 的地址时寻址方式决定CPU 访问高128 字节RAM 还是特殊功能寄存器空间直接寻址方式访问特殊功能寄存器SFR例如下面的直接寻址指令访问0A0HP2口存储单元MOV 0A0H data使用间接寻址方式访问高128 字节RAM例如下面的间接寻址方式中R0 内容为0A0H访问的是地址0A0H的寄存器而不是P2口它的地址也是0A0H MOV R0 data堆栈操作也是简介寻址方式因此高128字节数据RAM也可用于堆栈空间4 看门狗定时器WDT是一种需要软件控制的复位方式WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器WDTRST构成WDT 在默认情况下无法工作为了激活WDT户用必须往WDTRST 寄存器地址0A6H中依次写入01EH 和0E1H当WDT激活后晶振工作WDT在每个机器周期都会增加WDT计时周期依赖于外部时钟频率除了复位硬件复位或WDT溢出复位没有办法停止WDT工作当WDT溢出它将驱动RSR引脚一个高个电平输出41 WDT的使用为了激活WDT用户必须向WDTRST寄存器地址为0A6H的SFR依次写入0E1H 和0E1H当WDT激活后用户必须向WDTRST写入01EH和0E1H喂狗来避免WDT溢出当计数达到8191 1FFFH 时13 位计数器将会溢出这将会复位器件晶振正常工作WDT激活后每一个机器周期WDT 都会增加为了复位WDT用户必须向WDTRST 写入01EH 和0E1HWDTRST 是只读寄存器WDT 计数器不能读或写当WDT 计数器溢出时将给RST 引脚产生一个复位脉冲输出这个复位脉冲持续96个晶振周期TOSC其中TOSC 1FOSC为了很好地使用WDT应该在一定时间内周期性写入那部分代码以避免WDT复位42 掉电和空闲方式下的WDT在掉电模式下晶振停止工作这意味这WDT也停止了工作在这种方式下用户不必喂狗有两种方式可以离开掉电模式硬件复位或通过一个激活的外部中断通过硬件复位退出掉电模式后用户就应该给WDT 喂狗就如同通常AT89S52 复位一样通过中断退出掉电模式的情形有很大的不同中断应持续拉低很长一段时间使得晶振稳定当中断拉高后执行中断服务程序为了防止WDT在中断保持低电平的时候复位器件WDT 直到中断拉低后才开始工作这就意味着WDT 应该在中断服务程序中复位为了确保在离开掉电模式最初的几个状态WDT不被溢出最好在进入掉电模式前就复WDT在进入待机模式前特殊寄存器AUXR的WDIDLE位用来决定WDT是否继续计数默认状态下在待机模式下WDIDLE＝0WDT继续计数为了防止WDT 在待机模式下复位AT89S52用户应该建立一个定时器定时离开待机模式再重新进入待机模式5 UART在AT89S52 中UART 的操作与AT89C51 和AT89C52 一样6 定时器0 和定时器1在AT89S52 中定时器0 和定时器1 的操作与AT89C51 和AT89C52 一样7 定时器2定时器2是一个16位定时计数器它既可以做定时器又可以做事件计数器其工作方式由特殊寄存器T2CON中的CT2位选择如表2所示定时器2有三种工作模式捕捉方式自动重载向下或向上计数和波特率发生器如表 3 所示工作模式由T2CON中的相关位选择定时器2 有2 个8位寄存器TH2和TL2在定时工作方式中每个机器周期TL2 寄存器都会加1由于一个机器周期由12 个晶振周期构成因此计数频率就是晶振频率的112表3 定时器2工作模式RCLK TCLK CP TR2 MODE 0 0 1 16位自动重载0 1 1 16位捕捉 1 X 1 波特率发生器X X 0 不用在计数工作方式下寄存器在相关外部输入角T2 发生1 至0 的下降沿时增加1在这种方式下每个机器周期的S5P2期间采样外部输入一个机器周期采样到高电平而下一个周期采样到低电平计数器将加1在检测到跳变的这个周期的S3P1 期间新的计数值出现在寄存器中因为识别1－0的跳变需要2个机器周期24个晶振周期所以最大的计数频率不高于晶振频率的124为了确保给定的电平在改变前采样到一次电平应该至少在一个完整的机器周期内保持不变71 捕捉方式在捕捉模式下通过T2CON中的EXEN2来选择两种方式如果EXEN2 0定时器2时一个16位定时计数器溢出时对T2CON 的TF2标志置位TF2引起中断如果EXEN2 1定时器2做相同的操作除上述功能外外部输入T2EX引脚P111至0的下跳变也会使得TH2和TL2中的值分别捕捉到RCAP2H和RCAP2L中除此之外T2EX 的跳变会引起T2CON 中的EXF2 置位像TF2 一样T2EX 也会引起中断72 自动重载当定时器 2 工作于16 位自动重载模式可对其编程实现向上计数或向下计数这一功能可以通过特殊寄存器T2MOD见表4中的DCEN向下计数允许位来实现通过复位DCEN 被置为0因此定时器2 默认为向上计数DCEN 设置后定时器2就可以取决于T2EX向上向下计数DCEN 0 时定时器2 自动计数通过T2CON 中的EXEN2 位可以选择两种方式如果EXEN2 0定时器2计数计到0FFFFH后置位TF2溢出标志计数溢出也使得定时器寄存器重新从RCAP2H 和RCAP2L 中加载16 位值定时器工作于捕捉模式RCAP2H和RCAP2L的值可以由软件预设如果EXEN2 1计数溢出或在外部T2EXP11引脚上的1到0的下跳变都会触发16位重载这个跳变也置位EXF2中断标志位置位DCEN允许定时器2向上或向下计数在这种模式下T2EX引脚控制着计数的方向T2EX上的一个逻辑1使得定时器2向上计数定时器计到0FFFFH溢出并置位TF2定时器的溢出也使得RCAP2H和RCAP2L中的16位值分别加载到定时器存储器TH2和TL2中T2EX 上的一个逻辑0 使得定时器2 向下计数当TH2 和TL2 分别等于RCAP2H 和RCAP2L中的值的时候计数器下溢计数器下溢置位TF2并将0FFFFH加载到定时器存储器中定时器2上溢或下溢外部中断标志位EXF2 被锁死在这种工作模式下EXF2不能触发中断8 波特率发生器通过设置T2CON中的TCLK或RCLK可选择定时器2 作为波特率发生器如果定时器2作为发送或接收波特率发生器定时器1可用作它用发送和接收的波特率可以不同如图8 所示设置RCLK 和或TCLK 可以使定时器2 工作于波特率产生模式波特率产生工作模式与自动重载模式相似因此TH2 的翻转使得定时器2 寄存器重载被软件预置16位值的RCAP2H和RCAP2L中的值模式1和模式3的波特率由定时器2溢出速率决定定时器可设置成定时器也可为计数器在多数应用情况下一般配置成定时方式CP 0定时器 2 用于定时器操作与波特率发生器有所不同它在每一机器周期112晶振周期都会增加然而作为波特率发生器它在每一机器状态12晶振周期都会增加9 可编程时钟输出可以通过编程在P10 引脚输出一个占空比为50的时钟信号这个引脚除了常规的IO 角外还有两种可选择功能它可以通过编程作为定时器计数器 2 的外部时钟输入或占空比为50的时钟输出当工作频率为16MHZ时时钟输出频率范围为61HZ到4HZ为了把定时器2配置成时钟发生器位CT2CON1必须清0位T2OET2MOD1必须置1位TR2T2CON2启动停止定时器时钟输出频率取决于晶振频率和定时器2捕捉寄存器RCAP2HRCAP2L的重载值如公式所示在时钟输出模式下定时器2不会产生中断这和定时器2用作波特率发生器一样定时器2也可以同时用作波特率发生器和时钟产生不过波特率和输出时钟频率相互并不独立它们都依赖于RCAP2H和RCAP2L10 中断AT89S52 有6个中断源两个外部中断和三个定时中断定时器012和一个串行中断每个中断源都可以通过置位或清除特殊寄存器IE 中的相关中断允许控。
外文翻译--AT89S52单片机
外文原文AT89S52DescriptionThe AT89s52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory(PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89s52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.Pin Configurations: The AT89s52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bittimer/counters, a six-vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.Pin Description·VCC: Supply voltage.·GND: Ground.·Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internalpullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.·Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins)because of the internal that are externally being pulled low will source current (IILpullups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port Pin Alternate FunctionP1.0 T2(external count input to Timer／Counter2)，clock-outP1.1 T2EX(Time／Counter2 capture／reload triggerand direction control)·Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins)because of the internal that are externally being pulled low will source current (IILpullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals duringFlash programming and verification.·Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I) because of the pullups.ILPort 3 also serves the functions of various special features of the AT89C51, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.Port Pin Alternate FunctionP3.0 RXD (serial input port)P3.1 TXD（serial output port）P3.2 external interrupt 0P3.3 external interrupt 1P3.4 T0(timer 0 external input)P3.5 T1(timer 1 external input）P3.6 external data memory write strobeP3.7 external data memory read strobe ·RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.·ALE/PROG: Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.·PSEN: Program Store Enable is the read strobe to external program memory.When the AT89s52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.·EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to V CC for internal program executions.This pin also receives the 12-volt programming enable voltage (V PP) during Flash programming when 12-volt programming is selected.·XTAL1I: nput to the inverting oscillator amplifier and input to the internal clock operating circuit.·XTAL2: Output from the inverting oscillator amplifier.Oscillator Characteristics: XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle Mode: In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access tointernal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down Modes:Power Down Mode: In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock Bits: On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the Flash: The at89s52 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage(VCC) program enable signal.The low voltage programming mode provides a convenient way to program the at89s52 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The at89s52 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The at89s52 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the at89s52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase:The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming Interface: Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.中文翻译AT89S52AT89s52是美国ATMEL公司生产的低功耗，高性能COMS 8位单片机，片内含8K bytes的可反复擦写的Flash只读程序存储器和256 bytes的随机存取数据存储器(RAM)，器件采用ATMEL公司的高密度、非易是失性存储技术生产，与标准MCS－51指令系统及8052产品引脚兼容，片内置通用8位中央处理器(CPU)和Flash存储单元，功能强大AT89s52单片机适用许多较为复杂控制应用场合。
外文翻译--AT89C52单片机的介绍
中文4800字附录3：外文翻译AT89C52 monolithic integrated circuit introduction AT89C52 is the low voltage which American ATMEL Corporation produces, the high performance CMOS 8 monolithic integrated circuits, internal may repeatedly scratch read-only program memory (PEROM) and 256bytes random access data-carrier storage (RAM) including 8k bytes which writes, the component uses ATMEL Corporation the high density, the non-volatility memory technology production, is compatible with the standard MCS-51 command system and 8052 product pins, internal sets at general 8 central processor (CPU) and the Flash memory cell, the function formidable AT89C52 monolithic integrated circuit suits in many comparatively plurality of controls application situation.Main performance parameter:Are completely compatible with the MCS-51 product instruction and the pinThe 8k byte may again scratch writes Flash to dodge the fast memory1000 times scratches the write cycleEntire static operation: 0Hz—24MHzThree level of encryption program memory256×8 In byte RAM32 programmable I/O mouth line3 16 fixed time/counters8 interrupt sourcesProgrammable serial UART channelThe low power loss idle and falls the electricity patternFunction characteristic outline:Below AT89C52 provides the standard function: 8k byte Flash dodges the fast memory, 256 byte internal RAM,32 I/O mouth line, 3 16 fixed time/counters, 6 vector two level of interrupt structures, A full-duplex serial passes unguardedly, internal oscillator and clock electric circuit.At the same time, AT89C52 may fall to the 0HZ static state logical operation, and supports the electricity saving working pattern which two kind of softwares may elect.The idle way stops CPU the work, but permits RAM, fixed time/the counter, serial passes unguardedly and the interruption system continues to work.Falls the electricity way to preserve in RAM the content, but the oscillator knock off and forbids other all part work to reposition until the next hardware.The pin function showsVcc: Supply voltageGND: GroundingP0 mouth: The P0 mouth is one group of 8 leaks leads the way extremely the bidirectional I/O mouth, also is the address/data bus multiplying mouth.As outlet with when, each potential energy absorption current way actuates 8 TTL logic gate, when writes “1” to port P0, may take the high impedance input end uses.When visits exterior data-carrier storage or the program memory, when this group of mouth line segment transforms the address (low 8) and the data bus multiplying, pulls the resistance in the visit activation interior.When Flash programming, P0 mouth receive instruction byte, but when program check, when output order byte, verification, outside the request joins pulls the resistanceP1 mouth: P1 is in a belt interior pulls the resistance 8 bidirectional I/O mouth, the P1 output buffer may actuate (absorption or output current) 4 TTL logic gate.Writes “1” to the port, pulls the resistance through internal on to pull the port tothe high level, this time may make the input port.When makes the input port use, because in internal existence pulls the resistance, some pin is pulled lowly by exterior signal when can output electric current (IIL).With at89C51 similarity is, P1.0 and P1.1 also may take separately fixed time/the counter 2 exterior countings inputs (P1.0/T2) and inputs (P1.1/T2EX), see also table 1.Flash programming and program check period, P1 receives the low 8 bit address.P2 mouth: P2 is one has in the interior to pull the resistance 8 bidirectional I/O mouth, the P2 output buffer may actuate (absorption or output current) 4 TTL logic gate.Writes “1” to port P2, pulls the resistance through internal on to pull the port to the high level, this time may make the input port, when makes the input port use, because in internal existence pulls the resistance, some pin is pulled lowly by exterior signal when can output electric current (IIL).When visits exterior program memory or 16 bit address exterior data-carrier storage (e.g. carries out the MOVX@DPTR instruction), the P2 mouth sends out the high 8 bit address data.When visits 8 bit addresses exterior data-carrier storage (for example carries out the MOVX@RI instruction), the P2 mouth outputs the P2 latch the contentWhen Flash programming or verification, P2 also receives the top digit address and some control signal.P3 mouth: The P3 mouth is a group has in the interior to pull the resistance 8 bidirectional I/O mouth.The P3 mouth output buffer may actuate (absorption or output current) 4 TTL logic gate.Reads in “1” when to the P3 mouth, they the position resistance are pulled by the interior in Gao Bingke the achievement to input the port.This time, will be pulled by the outside the low P3 mouth to use to pull resistance output current (IIL).The P3 mouth besides took the general I/O mouth line, a more important use isIn addition, the P3 mouth also receives some to use in Flash dodging the fast memory programming and the program check control signal.RST: Replacement input.When the oscillator works, the RST pin will appear above two machine cycles the high level to cause the monolithic replacement.ALE/PROG: When visits exterior program memory or the data-carrier storage, ALE (address lock saves permission) to output the pulse to use in the lock saving the address the low 8 bytes.In ordinary circumstances, ALE still by clock oscilation frequency 1/6 output fixed pulse signal, therefore it may the foreign output clock or uses in fixed time the goal.Must pay attention: When visits exterior data-carrier storage will jump over a ALE pulse.To Flash memory programming period, this pin also uses in inputting programming pulse (PROG).If has the necessity, may through to in special function register (SFR) area 8EH the unit D0 position position, be possible to forbid the ALE operation.After this position position, only then MOVX and the MOVC instruction can activate ALE.In addition, this pin can pull weakly high, when the monolithic integrated circuit carries out exterior procedure, should establish the ALE prohibition position to be invalid PSEN: The procedure storage permits the (PSEN) output is exterior program memory reads the gating signal, when AT89C52 takes the instruction by exterior program memory (or data), each machine cycle two PSEN is effective, namely outputs two pulses.When visits exterior data-carrier storage, will jump over two RSEN signals.EA/VPP: Exterior visit permission.Wants to cause CPU only to visit exterior program memory (address is 0000H-FFFFH), the EA end must maintain the low level (earth).Must pay attention: If adds mil LB1 to program, when replacement the interiorcan lock saves the EA end condition.If the EA end (meets the Vcc end) for the high level, CPU carries out in the internal procedure memory instruction.When the Flash memory programs, this pin adds on 12V programming permission power source VPP, certainly this must be this component is uses 12V to program voltage VPP.XTAL1: Oscillator inverting amplifier and internal clock generator input end.XTAL2: Oscillator inverting amplifier out-port. Special function register:In at89C52 internal memory, the 80H-FFH altogether 128 units for special function register (SFE), SFR address basement reflection as shown in Table 2.All addresses all are defined by no means, only then a part is defined from the 80H-FFH altogether 128 bytes, but also has quite a part not to define.To the definition unit read-write will not have been Yuan Xiao, the read-out value will be indefinite, but will read in the data will also lose.Should not “1” not read in the data the definition unit, then will possibly entrust with the new function in these units in the future product, in this case, after replacement these unit value always “0”.AT89C52 besides with AT89C51 all fixed time/counters 0 and fixed time/counter 1, but also increased a fixed time/counter 2.Fixed time/the counter 2 control statusbyte is located T2CON、T2MOD (to see Table 4), the register to (RCA02H, RCAP2L) is the timer 2/automatic loads the register again under 16 capture ways or 16 automatic heavy loading way capture.Interrupt register:AT89C52 has 6 interrupt sources, 2 interrupt priorities, the IE register controls each interrupt position, in the IP register 6 interrupt source each may decide as 2 superiordata-carrier storages:AT89C52 has 256 byte internal RAM,80H-FFH high 128 bytes and the special function register (SFR) address is overlap, also is high 128 byte RAM and the special function register address is same, but in physics they are separated.When an instruction visits the 7FH above dummy home address unit, in the instruction uses the addressing way is different, also is the addressing way decision is visits high 128 byte RAM to visit the special function register.If the instruction is the direct addressing way for the visit special function register.For example, following direct addressing instruction visit special function register 0A0H (i.e. P2 mouth) address unit.MOV 0A0H,#dataThe indirect addressing instruction visits high 128 byte RAM, for example, in following indirect addressing instruction, the R0 content is 0A0H, then the visit data byte address is 0A0H, but is not the P2 mouth (0A0H).MOV the @R0,#datastorehouse operation also is the indirect addressing way, therefore, high 128 bit data RAM also may take the storehouse area use.Timer 0 and timer 1:The AT89C52 timer 0 and the timer 1 working and AT89C51 are same.Timer 2:The timer 2 is 16 fixed time/counters.It already may when timer use, also may take the external event counter use, its working chooses by the special function register T2CON C/T2 position.The timer 2 has three workings: The capture way, the automatic heavy loading (upward or downward counting) the way and the baudrate generator way, the working chooses by the T2CON control position, see also table 4.The timer 2 is composed by two 8 register TH2 and TL2, in the timer working, each machine cycle TL2 register value adds 1, because a machine cycle vibrates the clock constitution by 12, therefore, counting speed for oscilation frequency 1/12.When counting working, when on the T2 pin exterior input signal produces by 1 to 0 drops along, the register value adds 1, under this working, each machine cycle 5SP2 period, carries on the sampling to exterior input. If picks in the first machine cycle the value is 1, but the value which picks in the next machine cycle is 0, then is following close on the next cyclical S3P1 period register adds 1.Because distinguishes 1 to need 2 machine cycles to 0 jumps (24 durations of oscillation), therefore, highest counting speed for oscilation frequency 1/24. In order to guarantee the sampling the accuracy, the request input level maintains at least before the change for a complete cyclical the time, guarantees the input signal at least by sampling one time.Capture way:Under the capture way, chooses two ways through T2CON control position EXEN2.If EXEN2=0, the timer 2 is 16 timers or the counter, when counting overflow, to the T2CON overflow symbolized TF2 sets at the position, simultaneously activates the interrupt.If looks up EXEN2=1, the timer 2 completes the same operation, But when the T2EX pin exterior input signal has 1 to 0 negative jumps, also appears in TH2 and the TL2 value is caught separately to in RCAP2H and RCAP2L.Moreover, the T2EX pin signal jump causes in T2CON EXF2 to set at the position, is similar with TF2, EXF2 also can interrupt exactly.Capture way as shown in Figure 4.Automatic heavy loading (upward or downward counter) way:When timer 2 work in 16 automatic heavy loading ways, can to its programming for upward or the downward counting way, this function may (see Table 5) through special function register T2CON the DCEN position (permission downward counting) choose.When replacement, the DCEN position “0”, the timer 2 defaults establishes as the upward counting. When DCEN sets at the position, the timer 2 already may count upwardly also may the downward counting, this is decided by the T2EX pin value,see also Figure 5, when DCEN=0, the timer 2 automatic setups for the upward counting, under this way, in the T2CON EXEN2 control position have two kind of choices, if EXEN2=0, the timer 2 for the upward counting to the 0FFFFH overflow, sets at the position TF2 activation interrupt, simultaneously 16 counter register RCAP2H and the RCAP2L heavy loading, RCAP2H and the RCAP2L value may by the software initialization.When DCEN sets at the position, the timer 2 already may count upwardly also may the downward counting, this is decided by the T2EX pin value, see also Figure 5, when DCEN=0, the timer 2 automatic setups for the upward counting, under this way, in the T2CON EXEN2 control position have two kind of choices, if EXEN2=0, the timer 2 for the upward counting to the 0FFFFH overflow, sets at the position TF2 activation interrupt, simultaneously 16 counter register RCAP2H and the RCAP2L heavy loading, RCAP2H and the RCAP2L value may by the software initialization.Baudrate generator:When T2CON (Table 3) TCLK and RCLK set at the position, fixed time/the counter 2 takes the baudrate generator use.If fixed time/the counter 2 took thetransmitter or the receiver, its transmission and the receive baudrate may be different, the timer 1 uses in other functions, as shown in Figure 7.If RCLK and TCLK set at the position, then timer 2 work in baudrate generator way.The baudrate generator way and the automatic heavy loading way are similar, under this way, the TH2 turn over causes the timer 2 registers is important the new loading with in RCAP2H and the RCAP2L 16 figures, this value establishes by the software.In the way 1 and the way in 3, the baudrate determined by the timer 2 overflow speeds according to the equation below that,Way 1 and 3 baudrate = timer overflow rate /16The timer already can work in fixed time the way also can work in the counting way, in the majority applications, is the work in fixed time the way (C/T2=0).The timer 2 took when baudrate generator, with as the timer operation is different, when usual achievement timer, (1/12 oscilation frequency) checks the value in each machine cycle to add 1, but took when baudrate generator use, (1/2 oscilation frequency) the register value adds 1 in each condition time. The baudrate formula is as follows:The way 1 and 3 baudrate = oscilation frequency/{32×[65536-(RCAP2H, RCAP2L)]}in the formula (RCAP2H, RCAP2L) is in RCAP2H and RCAP2L 16 does not have the sign digit.The timer 2 took the baudrate generator use electric circuit as shown in Figure 7.In when T2CON RCLK or TCLK=1, the baudrate working only then is effective. In the baudrate generator working, the TH2 turn over cannot cause TF2 to set at theposition, therefore does not have the interrupt.But if EXEN2 sets at the position, also the T2EX end produces by 1 to 0 negative jumps, then can cause EXF2 to set at the position, this time cannot load (RCAP2H, RCAP2L) content in TH2 and TL2.Therefore, when the timer 2 takes the baudrate generator use, T2EX may use as the additional exterior interrupt source.Needs to pay attention, when timer 2 work in baudrate, when moves (TR2=1) as the timer, cannot visit TH2 and TL2.Because this time each condition time timer can add 1, to its read-write will obtain a indefinite value.But however, may read to RCAP2 cannot write, because the write operation will be the reload, the write operation possibly command writes with/or the heavy loading makes a mistake.In visits timer 2 or in front of the RCAP2 register, should (eliminate the timer closure TR2).The programmable clock outputs:The timer 2 may output a dutyfactor through the programming from P1.0 is 50% clock signal, as shown in Figure 8.The P1.0 pin besides is a standard I/O mouth, but also may cause it through the programming to take fixed time/the counter 2 exterior clock inputs and the output dutyfactor 50% clock pulse.When the clock oscilation frequency is 16MHz, outputs the clock frequency range is 61Hz-4MHz.When establishes fixed time/the counter 2 as the clock generator, C/T2(T2CON.1)=0, T2OE(T2MOD.1)=1, must or stops the timer by TR2(T2CON.2) start.The clock output frequency is decided in the oscilation frequency and the timer 2 catches the register (RCAP2H, RCAP2L) reload value, the formula is as follows:The output clock frequency = oscillator frequency/{4×[65536-(RCAP2H, RCAP2L)]}under the clock output way, the timer 2 turn over cannot have the interrupt, this characteristic with took when baudrate generator use is similar.When the timer 2 takes the baudrate generator use, Also may take the clock generator use, but needs to pay attention is the baudrate and the clock output frequency cannot separate the determination, this is because they with use RCAP2H and RCAP2L.AT89C52单片机的介绍AT89C52是美国ATMEL公司生产的低电压，高性能CMOS 8位单片机，片内含8k bytes的可反复擦写的只读程序存储器（PEROM）和256bytes的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，与标准MCS－51指令系统及8052产品引脚兼容，片内置通用8位中央处理器（CPU）和Flash存储单元，功能强大AT89C52单片机适合于许多较为复杂控制应用场合。
毕业论文外文翻译--基于AT89C52单片机的LED显示屏控制系统的设计
附件1：外文资料翻译译文基于AT89C52单片机的LED显示屏控制系统的设计摘要这篇文章介绍了基于AT89C52单片机的LED点阵显示屏的软件和硬件开发过程。
使用一个简单的外部电路来控制像素是32×192的显示屏。
用动态扫描，显示屏可以显示6个32×32的点阵汉字。
显示屏也可以分为两个小的显示屏，它可以显示24个像素是16×16的汉字。
可以通过修改代码来改变显示的内容和字符的滚动功能，而且可以根据需要调整字符的滚速或者暂停滚动。
中文字符代码存储在外部存储寄存器中，内存的大小由需要显示的汉字个数决定。
这种显示屏具有体积小，硬件和电路结构简单的优点。
关键词发光二极管汉字显示AT89C52单片机1.导言随着LED显示屏不断改善和美化人们的生活环境，LED显示屏已经成为城市明亮化，现代化、信息化的一项重要标志。
在大的购物商场，火车站，码头，地铁，大量的管理窗口等，我们经常可以看到LED灯光。
LED商业已成为一个快速增长的新产业，拥有巨大的市场空间和光明前景。
文章，图片，动画和视频通过LED发光显示，并且内容可以变换。
一些显示设备的模块化结构，通常有显示模块，控制系统和电源系统。
显示模块是由LED管组成的点阵结构，进行发光显示，可以显示文章，图片，视频等。
控制系统可以控制区域里LED的亮灭，电源系统为显示屏提供电压和电流。
用电脑，取出字符字节，传送到微控制器，然后送到LED点阵显示屏上进行显示，很多室内和室外显示屏都是通过这个方法进行显示的。
按显示的内容区分，LED点阵屏的显示可分为图形显示、图片显示和视频显示三个部分。
与图片显示屏比较，不管是单色或者彩色的图形显示屏，都没有灰色色差，所以，图形显示不能反映丰富的色彩。
视频显示屏不但可以显示运动、清楚和全彩的图像，也可以显示电视和计算机信号。
虽然三者之间有一些不同，但显示的原理基本一样。
单片机具有优良的性价比，体型小，可靠性高，控制能力强，它广泛用于智能仪器、机电一体化的实时过程控制、机器人、家用电器、模糊控制和通讯系统等。
论文 单片机AT89S52
摘要本设计以单片机AT89S52作为小车的控制核心。
电路分为道路检测与方位控制模块、电机及其驱动模块、平衡检测模块、显示及声光指示模块等几部分。
路面检测采用红外发射∕接收管来检测黑线；电机驱动采用以L298为核心的PWM技术；使用WQ36-10倾角传感器达到小车在板上保持平衡。
小车分阶段显示行驶时间，并在平衡时做出声音报警。
AbstractIn this design, the controller kernel of this dolly is based on MCU AT89S52. The circuit is composed of the following modules: detecting black thread on the road and direction controller module, motor drive module, balance detection module, display and sound-light instruction module. The detection of black thread on the road is realized by reflection infrared shoot/receiver valve; and motor drive module adopts PWM technology which kernel is L298.The WQ36-10, a kind of obliquity transducer, makes the dolly balance on the teeterboard. The dolly displays time every phase and give an alarm when it has balanced.一、方案比较、选择与论证本部分先对几个重要的模块进行不同方案比较、论证，确定最终方案。
基于单片机的居室安全报警系统设计外文参考及翻译
本科生毕业设计（论文）专业外文翻译原文：Microcontroller Based Home Automation System With Security译文：基与单片机的智能家居系统与安全性指导教师：职称：副教授学生姓名：学号： 1002120106专业：电气工程及其自动化院（系）：机电工程学院2014年3月20日Microcontroller Based Home Automation System With SecurityAbstract:With advancement of technology things are becoming simpler and easier for us. Automatic systems are being preferred over manual system. This unit talks about the basic definitions needed to understand the Project better and further defines the technical criteria to be implemented as a part of this project.Keywords-component; Automation, 8051 microcontroller, LDR,LED, ADC, Relays, LCD display, Sensors, Stepper motorI.NTRODUCTIONA home automation system integrates electrical devices in ahouse with each other. The techniques employed in home automation include those in building automation as well as the control of domestic activities, such as home entertainment systems, houseplant and yard watering, pet feeding, changing the ambiance "scenes" for different events (such as dinners or parties), and the use of domestic robots. Devices may be connected through a computer network to allow control by apersonal computer, and may allow remote access from the internet.Typically, a new home is outfitted for home automation during construction, due to the accessibility of the walls, outlets, and storage rooms, and the ability to make design changes specifically to accommodate certain technologies. Wireless systems are commonly installed when outfitting a pre-existing house, as they reduce wiring changes. These communicate through the existing power wiring, radio, or infrared signals with a central controller. Network sockets maybe installed in every room like AC power receptacles. Although automated homes of the future have been staple exhibits for World's Fairs and popular backgrounds in science fiction, complexity, competition between vendors, multiple ncompatible standards and the resulting expense have limited the penetration of home automation to homes of the wealthy or ambitious hobbyists.II.HOME AUTOMATIONHome/office automation is the control of any or all electrical devices in our home or office, whether we are there or away. Home/office automation is one of the most exciting developments in technology for the home that has come along in decades. There are hundreds of products available today that allow us control over the devices automatically, either by remote control; or even by voice command. Home automation (also called domotics) is the residential extension of "building automation". It is automation of the home,housework or household activity. Home automation may include centralized control of lighting, HV AC (heating,ventilation and air conditioning), appliances, and other systems,to provide improved convenience, comfort, energy efficiency and security. Disabled can provide increased quality of life for persons who might otherwise require caregivers or institutional care. Earlier, we looked into the face of future when we talked about automated devices, which could do anything on instigation of a controller, but today it has become a reality.III.NEED OF AUTOMATIONWith advancement of technology things are becoming simpler and easier for us. Automation is the use of control systems and information technologies to reduce the need for human work in the production of goods and services. In the scope of industrialization, automation is a step beyond mechanization. Whereas mechanization provided human operators with machinery to assist them with the muscularrequirements of work, automation greatly decreases the need for human sensory and mental requirements as well. Automation plays an increasingly important role in the world economy and in daily experience. Automatic systems are being preferred over manual ystem. Through this project we have tried to show automatic control of a house as a result of which power is saved to some extent.a) An automated device can replace good amount of human working force, moreover humans are more prone to errors and in intensive conditions the probability of error increases whereas, an automated device can work with diligence,versatility and with almost zero error.Replacing human operators in tasks that involve hard physical or monotonous work.Replacing humans in tasks done in dangerous environments (i.e. fire, space, volcanoes, nuclear facilities,underwater, etc)Performing tasks that are beyond human capabilities of size, weight, speed, endurance, etc.Economy improvement. Automation may improve in economy of enterprises, society or most of humankind. For example, when an enterprise that has invested in automation technology recovers its investment, or when a state or country increases its income due to automation like Germany or Japan in the 20th Century.b) This is why this project looks into construction and implementation of a system involving hardware to control a variety of electrical and electronics system.IV.SUPPY UNITA.Transformer:The main source of power(Fig 1) supply is a transformer. The maximum output power of power supply is dependent on maximum output power of transformer .We determine power from its current and voltage rating. e.g.: if there is a transformer of 12V, 500mA then maximum power delivered by transformer is 6Watt.It means we can drive a load from this transformer up to 6w. In our project our maximum power requirement is 1watt. So to provide this power we use 12V/250mA transformer. The maximum output power of this transformer is 4watt.it means it can easily drive load up to 4 watt.B.RectifierRectifier is a circuit which is used to convert ac to dc.Every electronic circuit requires a dc power supply for rectification. We have used four diodes.C.Input filter:After rectification we obtain dc supply from ac but it is not pure dc it may have some ac ripples .To reduce these ripples we use filters. It comprises of two filters –low frequency ripple filter and high frequency ripple filter. To reduce low frequency ripples we use electrolytic capacitor. The voltage rating of capacitor must be double from incoming dc supply. It blocks dc and passes ripples to ground.D.RegulatorInitial stage of every electronic circuit is power supply system which provides required power to drive the whole system. The specification of power supply depends on the power requirement and this requirement is determined by its rating. The main components used in supply system are.Regulator is a device which provides constant output voltage with varying input voltage. There are two types of regulators(a) Fixed voltage regulator(b) Adjustable regulatorWe have used fixed voltage regulator LM78XX last two digits signify output voltage. The voltage for our system is 5V that is why we have used 7805 regulator which provides 5V from 12V dc.E.Output filter:It is used to filter out output ripple if any.F.Output indicationWe use LED to observe the functioning of our system. If he LED glows it confirms proper functioning of our supply.We have used four power supply units.This supply is for the microcontroller,display and relay unit.The microcontroller requires 5 volt supply to perform any desired task.G.Control UnitTwo control units were used one for internal system and one for external system and these control unit based on ATMEL’sAT89S52 microcontroller(Fig 2). The given capture shows the pins and basic requirement of microcontroller to make it functional. Detailed description of the controller is 100uf / 50v.In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software electable power saving modes. The Idle Mode stops the CPUwhile allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning.Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.The Downloadable Flash can be changed a single byte at a time and is accessible through the SPI serial interface. Holding RESET active forces the SPI bus into a serial programming interface and allows the program memory to be written to or read from unless Lock Bit 2 has been activated.H.FeaturesCompatible with MCS-51™ProductsI.8KbytesofIn-SystemDownloadable Flash MemoryReprogrammableSPI Serial Interface for Program DownloadingEndurance: 1,000 Write/Erase Cycles4.0V to5.5V Operating RangeFully Static Operation: 0 Hz to 33 MHz56 x 8 bit Internal RAM32 Programmable I/O LinesThree 16 bit Timer/CountersEight Interrupt SourcesUll Duplex UART Serial ChannelLow Power Idle and Power Down ModesI .AdvantagesLess power consumptionLow costLess space requiredHigh speedFig 2-Chip BoardAT89S52 is an ATMEL controller with the core of Intel MCS-51. It has same pin configuration as give above. The AT89S52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Downloadable Flash programmable and erasable read only memory and 2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pin out. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Downloadable Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two Data Pointers, three 16-bit timer/counters, a six-vectorJ .Pin DescriptionVCC: Supply voltage. GND: Ground., Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table .Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52.RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled. ALE/PROG: Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note,however,that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN: Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2: Output from the inverting oscillator amplifier.H. Display UnitFig 3-Display UnitLiquid crystal displays (LCD) is an alphanumeric display and widely used in recent years as compared to LEDs. This is due to the declining prices of LCD, the ability to display numbers, characters and graphics, incorporation of a refreshing controller into the LCD, their by relieving the CPU of the task of refreshing the LCD and also the ease of programming for characters and graphics. We have used JHD162A advanced version of HD44780 based LCDs.V.WHAT CAN BE AUTOMATEDA.Virtually anything in the home/office that is powered by electricity can be automated and/or controlled. We can control our electrical devices. The password is given with the help of controller and can be changed by simply making a small change in the program and then burning the program in the controller.B.Counter dependent automatic switching system of roomAfter opening the lock when the person enters the room the counter gets incremented.Now if it is a day then the lights would not be switched on but if it is dark then the lights will automatically switch on. Now whatever may be the number of people entering the room the counter will automatically get incremented by itself and on leaving the room the counter will get decremented but the system will keep on working .Once the counter is zero in other words once everyone leaves the room the switching system will automatically stop working.C.Temperature controlled cooling systemOnce the person has entered the room he would not require to switch on anything everything will just happen automatically. Like if the temperature is high then the fan will switch on, on its own. Else it will remain in off state. This temperature is predefined by us in the controller. But this system will only work if there is a person in the room in other words if the counter is not zero.D.Light saving systemThis light saving system is used in two places for internal section and external section. If a person is not at home or sitting inside the room and it is dark outside then the lights will automatically get switched on and when its day the light will get switched off. This ensures power saving.Fire and Smoke sensorThis part detects any fire or smoke from a fire and set an alarm or an indication.VI. FEATURESPassword Based Locking SystemIn this system we have ensured a safe locking system. On seeing from outside the lock would not be visible but this inbuilt locking system ensures security. This lock can be opened and closed with the help of a password which we will give using a keypad. The door will only open or close only if the password is correct else it will remain in its original state. The lock cannot be broken because to the person standing Future of Automation: Future will be of Automation of all products. Each and every product will be smart devices that we use daily and that will be controlled through a smart chip called microcontrollers. Each and Every home appliances will be controlled either by PC or hand held devices like PDA or mobile handsets. Some examples of it are when you want you can switch on/off Fan of your home by mobile handset or PC.Smart Grid: Home automation technologies are viewed as integral additions to the Smart grid. The ability to control lighting, appliances, HV AC as well as Smart applications(load shedding, demand response, real-time power usage and price reporting) will become vital as Smart Grid initiatives are rolled out.VII. CONCLUSIONAn automated home can be a very simple grouping of controls, or it can be heavilyautomated where any appliance that is plugged into electrical power is remotelycontrolled. Costs mainly include equipment, components, furniture, and custom installation.Ongoing costs include electricity to run the control systems, maintenance costs for the control and networking systems, including troubleshooting, and eventual cost of upgrading as standards change. Increased complexity may also increase maintenance costs for networked devices.Learning to use a complex system effectively may take significant time and training.Control system security may be difficult and costly to maintain, especially if the control system extends beyond the home, for instance by wireless or by connection to the internet or other networks.基与单片机的智能家居系统与安全性摘要：随着技术的进步的东西变得更简单，更容易为我们服务。
at89c52单片机中英文资料对照外文翻译文献综述
D.htmlat89c52单片机中英文资料对照外文翻译文献综述at89c52单片机简介中英文资料对照外文翻译文献综述AT89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。
Storage RAM immediately﹑memoy readROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。
Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
本科毕业设计（论文）外文翻译外文资料翻译译文AT89S52主要性能●与MCS-51单片机产品兼容●8K字节在系统可编程Flash存储器●1000次擦写周期●全静态操作：0Hz～33Hz●三级加密程序存储器●32个可编程I/O口线●三个16位定时器/计数器●八个中断源●全双工UART串行通道●低功耗空闲和掉电模式●掉电后中断可唤醒●看门狗定时器●双数据指针●掉电标识符功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程Flash 存储器。
使用Atmel公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。
片上Flash允许程序存储器在系统可编程，亦适于常规编程器。
在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。
AT89S52具有以下标准功能：8k字节Flash，256字节RAM，32位I/O口线，看门狗定时器，2个数据指针，三个16位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。
另外，AT89S52可降至0Hz静态逻辑操作，支持2种软件可选择节电模式。
空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。
掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。
引脚结构方框图VCC : 电源GND :地P0口：P0口是一个8位漏极开路的双向I/O口。
作为输出口，每位能驱动8个TTL逻辑电平。
对P0端口写“1”时，引脚用作高阻抗输入。
当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。
在这种模式下，P0具有内部上拉电阻。
在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。
程序校验时，需要外部上拉电阻。
P1口：P1 口是一个具有内部上拉电阻的8位双向I/O 口，p1 输出缓冲器能驱动4个TTL 逻辑电平。
对P1端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。
作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。
此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX），具体如下表所示。
在flash 编程和校验时，P1口接收低8位地址字节。
P2 口：P2 口是一个具有内部上拉电阻的8 位双向I/O 口，P2输出缓冲器能驱动4个TTL 逻辑电平。
对P2端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。
作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。
在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVX @DPTR）时，P2口送出高八位地址。
在这种应用中，P2口使用很强的内部上拉发送1。
在使用8位地址（如MOVX @RI）访问外部数据存储器时，P2口输出P2锁存器的内容。
在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。
P3 口：P3口是一个具有内部上拉电阻的8 位双向I/O 口，p2输出缓冲器能驱动4个TTL 逻辑电平。
对P3端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。
作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。
P3口亦作为AT89S52特殊功能（第二功能）使用，如下表所示。
在flash 编程和校验时，P3口也接收一些控制信号。
RST: 复位输入。
晶振工作时，RST脚持续2个机器周期高电平将使单片机复位。
看门狗计时完成后，RST脚输出96个晶振周期的高电平。
特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。
DISRTO默认状态下，复位高电平有效。
ALE/PROG：地址锁存控制信号（ALE）是访问外部程序存储器时，锁存低8位地址的输出脉冲。
在flash编程时，此引脚（PROG）也用作编程输入脉冲。
在一般情况下，ALE 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。
然而，特别强调，在每次访问外部数据存储器时，ALE脉冲将会跳过。
如果需要，通过将地址为8EH的SFR的第0位置“1”，ALE操作将无效。
这一位置“1”，ALE 仅在执行MOVX 或MOVC指令时有效。
否则，ALE 将被微弱拉高。
这个ALE 使能标志位（地址为8EH的SFR的第0位）的设置对微控制器处于外部执行模式下无效。
PSEN :外部程序存储器选通信号（PSEN）是外部程序存储器选通信号。
当 AT89S52从外部程序存储器执行外部代码时，PSEN在每个机器周期被激活两次，而在访问外部数据存储器时，PSEN将不被激活。
EA /VPP:访问外部程序存储器控制信号。
为使能从0000H 到FFFFH的外部程序存储器读取指令，EA必须接GND。
为了执行内部程序指令，EA应该接VCC。
在flash编程期间，EA也接收12伏VPP电压。
XTAL1:振荡器反相放大器和内部时钟发生电路的输入端。
XTAL2:振荡器反相放大器的输出端。
存储器结构MCS-51器件有单独的程序存储器和数据存储器。
外部程序存储器和数据存储器都可以64K寻址。
程序存储器：如果EA引脚接地，程序读取只从外部存储器开始。
对于89S52，如果EA接VCC，程序读写先从内部存储器（地址为0000H～1FFFH）开始，接着从外部寻址，寻址地址为：2000H~FFFFH。
中断AT89S52有6个中断源：两个外部中断（INT0和INT1），三个定时中断（定时器0、1、2）和一个串行中断。
这些中断每个中断源都可以通过置位或清除特殊寄存器IE中的相关中断允许控制位分别使得中断源有效或无效。
IE还包括一个中断允许总控制位EA，它能一次禁止所有中断。
IE.6位是不可用的。
对于AT89S52，IE.5位也是不能用的。
用户软件不应给这些位写1。
它们为AT89系列新产品预留。
定时器2可以被寄存器T2CON中的TF2和EXF2的或逻辑触发。
程序进入中断服务后，这些标志位都可以由硬件清0。
实际上，中断服务程序必须判定是否是TF2 或EXF2激活中断，标志位也必须由软件清0。
定时器0和定时器1标志位TF0 和TF1在计数溢出的那个周期的S5P2被置位。
它们的值一直到下一个周期被电路捕捉下来。
然而，定时器2的标志位TF2在计数溢出的那个周期的S2P2被置位，在同一个周期被电路捕捉下来。
参考资料：1．ATMEL公司AT89S52的技术手册2．深圳市中源单片机发展有限公司AT89C52 Datasheets3．复旦大学出版社单片微型机原理、应用和实验张友德等外文原文AT89S52Features• Compatible with MCS-51® Products• 8K Bytes of In-System Programmable (ISP) Flash Memory• 1000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 33 MHz• Three-level Program Memory Lock• 256 x 8-bit Internal RAM• 32 Programmable I/O Lines• Three 16-bit Timer/Counters• Eight Interrupt Sources• Full Duplex UART Serial Channel• Low-power Idle and Power-down Modes• Interrupt Recovery from Power-down Mode• Watchdog Timer• Dual Data Pointer• Power-off FlagDescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combining a versatile 8-bit CPU with in system programmable Flash on a monolithicchip, the Atmel AT89S52 is a powerful icrocontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following tandard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines,Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance Inputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during ccesses to external program and data memory. In this mode, P0 has int -ernal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur -ing program verification.External pullups are required during program veri- fication.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the ti -mer/counter 2 exte- rnal count input (P1.0/T2) and the timer/counter 2 trigger input(P1.1/T2EX), respectively, as shown in the following table.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses toexternal data memory that use 16-bit ddresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emitsthe contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins,they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out featureis enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ- ency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has no effect if the microco- ntroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to external program memory.When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be ternally latched on reset. EA should be strapped to VCC for internal rogram executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming. XTAL1Input to the inverting oscillator amplifier and input to the nternal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or nactive values of the new bits will always be 0.Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H , RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Timer 2 Operating ModesIn the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0transition, the maximum count rate is 1/24 of the oscillator frequency. To nsure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, whichdisables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemented.User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Reference data:1. the ATMEL company AT89S52 technical manuals2.Shenzhen Development Co., Ltd. AT89C52 Datasheets source SCM3.Fudan University Press, single-chip microprocessor theory, application and testZHANG You-de, etc.。