门电路VHDL语言
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“非”门
library ieee;
use ieee.std_logic_1164.all; entity not1 is
port(a:in std_logic;
b:out std_logic); end entity not1; architecture behav of not1 is begin
b<=not a;
end architecture behav;
“与”门
library ieee;
use ieee.std_logic_1164.all; entity and2 is
port(a,b:in std_logic;
c:out std_logic); end entity and2; architecture behav of and2 is begin
c<=a and b;
end architecture behav;
“与非”门
library ieee;
use ieee.std_logic_1164.all; entity nand2 is
port(a,b:in std_logic;
c:out std_logic); end entity nand2; architecture behav of nand2 is begin
c<=not(a and b);
end architecture behav; “或非”门
library ieee;
use ieee.std_logic_1164.all;
entity nor2 is
port(a,b:in std_logic;
c:out std_logic);
end entity nor2;
architecture one of nor2 is
begin
c<=not(a or b);
end architecture one;
“异或非”门
library ieee;
use ieee.std_logic_1164.all;
entity xor2 is
port(a,b:in std_logic;
c:out std_logic);
end entity xor2;
architecture one of xor2 is
Begin
c<=not( ( (not a)and b)or(a
and(not b) ) );
end architecture one;
D触发器
library ieee;
use ieee.std_logic_1164.all;
entity dffa is
port(D,clk,clr:in std_logic;
Q:out std_logic);
end entity dffa;
architecture behave of dffa is
begin
process(clk,D,clr)
begin
if clr='1' then Q<='0';
Elsif clk'event and clk='1'
then Q<=D;
end if;
end process;
end architecture behave;
T触发器
library ieee;
use ieee.std_logic_1164.all;
entity tffa is
port(T,clk,clr: in std_logic;
Q: buffer std_logic);
end entity tffa;
architecture behave of tffa is
begin
process(clk,T,clr)
begin
if clk'event and clk='1'then
if clr='1' then Q<='0';
Elsif t='1'then Q<=not Q;
else Q<=Q;
End if;
end if;
end process;
end architecture behave;
JK触发器
library ieee;
use ieee.std_logic_1164.all;
entity jk is
port(J,K,clk, in std_logic;
Q: buffer std_logic);
end entity tffa;
architecture behave of jk is
begin
process(clk,J,K)
begin
if clk'event and clk='1'then
Q<=( (J and(not Q) )or( (not
K)and Q) );
end if;
end process;
end architecture behave;
移位寄存器
library ieee;
use ieee.std_logic_1164.all; use
ieee.std_logic_unsigned.all; entity reg is
port(clk,din, dir: in std_logic;
op: out std_logic);
end entity reg;
architecture a of reg is
signal q:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if clk'event and clk='1'then
if dir='0' then q(0)<=din;
for i in 1 to 7 loop
q(i)<=q(i-1);
end loop;
else q(7)<=din;
for i in 1 to 7 loop
q(i-1)<=q(i);
end loop;
end if;
end if;
end process;
op<=q(7)when dir='0'else
q(0);
end architecture a; 分频电路
library ieee;
use ieee.std_logic_1164.all;
use
ieee.std_logic_unsigned.all;
entity divf is
port(clk: in std_logic;
q: out std_logic);
end entity divf;
architecture a of divf is
signal rst:std_logic;
signal qn:std_logic_vector(2
downto 0);
begin
process(clk,rst)
begin
if rst='1'then qn<="000";
elsifclk'event and clk='1'then
qn<=qn+1;
end if;
end process;
rst<='1'when qn=6 else'0';
q<= qn(2);
end architecture a;
74LS160计数器
library ieee;
use ieee.std_logic_1164.all;
use
ieee.std_logic_unsigned.all;
entity ls74160 is
port(clk,rst,ena,pe:in
std_logic;
d:in std_logic_vector(3 downto
0);
count:out std_logic_vector(3
downto 0);
co:out std_logic);
end;
architecture behave of ls74160
is
signal temp:std_logic_vector
(3 downto 0);
begin
process(clk,rst,ena,pe)
begin
if (rst='1')then
temp<="0000";
elsif(clk'eventandclk='1')then
if ena='1'then
if pe='1'then temp<=d;
elsif temp="1001"then
temp<="0000";
co<='1';
else temp<=temp+1;
co<='0';
end if;
end if;
end if;
end process;
count<=temp;
end behave;