CPU设计实验报告

武汉大学计算机学院计算机科学与技术专业CPU设计实验报告实验名称:开放式实验CPU设计课题名称: 计算机组成原理班级: 计科2班指导教师：***组长:组员:二零一五年三月目录目录 (2)1 实验环境(张航宇) (4)1.1 Quartus Ⅱ介绍 (4)1.2 硬件描述语言（VHDL） (4)1.3实验的主要成果 (4)2 实验要求(彭阳坤) (5)2. 1 指令格式要求 (5)2. 2 指令流程及微信号序列分析 (5)2.2.1 ADD指令分析 (5)2.2.2 ADC指令分析 (5)2.2.3 SUB指令分析 (6)2.2.4 SBC指令分析 (6)2.2.5 INC指令分析 (6)2.2.6 DEC指令分析 (6)2.2.7 SHL指令分析 (7)2.2.8 SHR指令分析 (7)2.2.9 MOVR指令分析 (7)2.2.11 MOVD指令分析 (7)2.2.12 LDRR指令分析 (8)2.2.13 STRR指令分析 (8)2.2.14 JMP指令分析 (8)2.2.15 JRZ指令分析 (8)2.2.16 JRC指令分析 (9)3.部件仿真实验(彭阳坤) (10)3.1 八个通用寄存器设计与仿真 (10)3.1.1 设计代码 (10)3.1.2 RTL连接图 (16)3.1.3 仿真过程 (16)3.2算术逻辑单元设计与仿真 (17)3.2.1 设计代码 (17)3.2.2 RTL连接图 (22)3.2.3 仿真过程 (23)4. CPU设计(彭阳坤) (24)4.1取指设计 (24)4.2 时序节拍设计 (25)4.3指令译码的设计 (26)4.4执行部分设计 (29)4.5存储器部分设计 (31)4.6通用寄存器组设计 (32)4.7寄存器输出设计 (38)4.8顶层实体设计 (38)5. 测试报告(张航宇) (42)5.1规则文件 (42)5.2测试文件 (42)5.3指令测试 (44)6 实验总结 (46)6.1 彭阳坤的小结 (46)6.1.1 实验收获 (46)6.1.2 建议与意见 (46)6.2张航宇的小结 (46)6.2.1 实验收获 (46)6.2.2 建议与意见 (47)参考资料 (47)1 实验环境(张航宇)1.1 Quartus Ⅱ介绍QuartusⅡ提供了方便的设计输入方式、快速的编译和直接易懂的器件编程。

能够支持逻辑门数在百万门以上的逻辑器件的开发，并且为第三方工具提供了无缝接口。

QuartusⅡ支持的器件有：Stratix Ⅱ、Stratix GX、Stratix、Mercury、MAX3000A、MAX 7000B、MAX 7000S、MAX 7000AE、MAX Ⅱ、FLEX6000、FLEX10K、FLEX10KA、FLEX10KE、Cyclone、Cyclone Ⅱ、APEX Ⅱ、APEX20KC、APEX20KE和ACEX1K系列。

QuartusⅡ软件包的编程器是系统的核心，提供功能强大的设计处理，设计者可以添加特定的约束条件来提高芯片的利用率。

1.2 硬件描述语言（VHDL）VHDL语言是一种用于电路设计的高级语言。

它在80年代的后期出现。

最初是由美国国防部开发出来供美军用来提高设计的可靠性和缩减开发周期的一种使用范围较小的设计语言。

VHDL翻译成中文就是超高速集成电路硬件描述语言，主要是应用在数字电路的设计中。

它在中国的应用多数是用在FPGA/CPLD/EPLD的设计中。

当然在一些实力较为雄厚的单位，它也被用来设计ASIC。

VHDL主要用于描述数字系统的结构，行为，功能和接口。

除了含有许多具有硬件特征的语句外，VHDL的语言形式、描述风格以及语法是十分类似于一般的计算机高级语言。

VHDL的程序结构特点是将一项工程设计，或称设计实体（可以是一个元件，一个电路模块或一个系统）分成外部（或称可视部分,及端口)和内部（或称不可视部分），既涉及实体的内部功能和算法完成部分。

在对一个设计实体定义了外部界面后，一旦其内部开发完成后，其他的设计就可以直接调用这个实体。

这种将设计实体分成内外部分的概念是VHDL系统设计的基本点。

1.3实验的主要成果熟悉对Quartus和VHDL的使用，完成一个16位8个寄存器的简单CPU，实现18条指令。

2 实验要求(彭阳坤)2. 1 指令格式要求2. 2 指令流程及微信号序列分析2.2.1 ADD指令分析2.2.2 ADC指令分析2.2.3 SUB指令分析2.2.4 SBC指令分析2.2.5 INC指令分析2.2.6 DEC指令分析2.2.7 SHL指令分析2.2.8 SHR指令分析2.2.9 MOVR指令分析2.2.11MOVD指令分析2.2.12 LDRR指令分析STRR指令分析2.2.13指令分析2.2.16 JRC指令分析3.部件仿真实验(彭阳坤)3.1 八个通用寄存器设计与仿真3.1.1 设计代码①寄存器reglibrary ieee;use ieee.std_logic_1164.all;entity reg is port(reset: in std_logic;d_input: in std_logic_vector(15 downto 0);clk: in std_logic;write: in std_logic;sel: in std_logic;q_output: out std_logic_vector(15 downto 0));end reg;architecture a OF reg isbeginprocess(reset,clk)beginIF reset = '0' thenq_output <= x"0000";elsif clk'event and clk = '0' then --时钟下降沿触发if sel ='1' and write = '1' thenq_output <= d_input;end if;end if;end process;end a;②3-8译码器Decoder_3_to_8.vhdlibrary ieee;use ieee.std_logic_1164.all;entity decoder_3_to_8 isport (sel: in std_logic_vector(2 downto 0);sel00: out std_logic;sel01: out std_logic;sel02: out std_logic;sel03: out std_logic;sel04: out std_logic;sel05: out std_logic;sel06: out std_logic;sel07: out std_logic);end decoder_3_to_8;architecture behavioral of decoder_3_to_8 isbeginsel00 <= (not sel(2)) and (not sel(1)) and (not sel(0));sel01 <= (not sel(2)) and (not sel(1)) and sel(0) ;sel02 <= (not sel(2)) and sel(1) and (not sel(0)) ;sel03 <= (not sel(2)) and sel(1) and sel(0) ;sel04 <= sel(2) and (not sel(1)) and (not sel(0));sel05 <= sel(2) and (not sel(1)) and sel(0);sel06 <= sel(2) and sel(1) and (not sel(0));sel07 <= sel(2) and sel(1) and sel(0);end behavioral;③8选1选择器mux_8_to_1.vhdlibrary ieee;use ieee.std_logic_1164.all;entity mux_8_to_1 isport (input0,input1,input2,input3,input4,input5,input6,input7: in std_logic_vector(15 downto 0);sel: in std_logic_vector(2 downto 0);out_put: out std_logic_vector(15 downto 0));end mux_8_to_1;architecture behavioral of mux_8_to_1 isbeginmux: process(sel, input0, input1, input2, input3,input4,input5,input6,input7) begincase sel iswhen "000" =>out_put <= input0;when "001" =>out_put <= input1;when "010" =>out_put <= input2;when "011" =>out_put <= input3;when "100" =>out_put <= input4;when "101" =>out_put <= input5;when "110" =>out_put <= input6;when "111" =>out_put <= input7;end case;end process;end behavioral;④通用寄存器组regfilelibrary ieee;use ieee.std_logic_1164.all;use work.exp_cpu_components.all;entity regfile isPort ( DR: in std_logic_vector(2 downto 0); --目的寄存器号SR: in std_logic_vector(2 downto 0); --源寄存器号reset: in std_logic;write: in std_logic; --写寄存器信号clk: in std_logic;d_input: in std_logic_vector(15 downto 0); --写寄存器的数据change_z: in std_logic; --如果为1，则重新设置z标志change_c: in std_logic;c_in: in std_logic;z_in: in std_logic;output_DR: out std_logic_vector(15 downto 0);output_SR: out std_logic_vector(15 downto 0);c_out: out std_logic;z_out: out std_logic);end regfile;architecture struct of regfile issignal reg00, reg01, reg02,reg03,reg04,reg05,reg06,reg07: std_logic_vector(15 downto 0); signal sel00, sel01, sel02,sel03,sel04,sel05,sel06,sel07: std_logic;beginz_c_proc: process(reset,clk) --对指令执行结束后的z、c标志进行处理beginif reset = '0' thenz_out <= '0';c_out <= '0';elsif clk'event and clk = '0' thenif change_z = '1' thenz_out <= z_in;end if;if change_c = '1' thenc_out <= c_in;end if;end if;end process;Areg00: reg port map( --寄存器R0reset => reset,d_input => d_input,clk => clk,write => write,sel => sel00,q_output => reg00);Areg01: reg port map( --寄存器R1reset => reset,d_input => d_input,clk => clk,write => write,sel => sel01,q_output => reg01);Areg02: reg port map( --寄存器R2reset => reset,d_input => d_input,clk => clk,write => write,sel => sel02,q_output => reg02);Areg03: reg port map( --寄存器R3 reset => reset,d_input => d_input,clk => clk,write => write,sel => sel03,q_output => reg03);Areg04: reg port map( --寄存器R4 reset => reset,d_input => d_input,clk => clk,write => write,sel => sel04,q_output => reg04);Areg05: reg port map( --寄存器R5 reset => reset,d_input => d_input,clk => clk,write => write,sel => sel05,q_output => reg05);Areg06: reg port map( --寄存器R6 reset => reset,d_input => d_input,clk => clk,write => write,sel => sel06,q_output => reg06);Areg07: reg port map( --寄存器R7 reset => reset,d_input => d_input,clk => clk,write => write,sel => sel07,q_output => reg07);des_decoder: decoder_3_to_8 port map( --3 —4译码器sel => DR,sel00 => sel00,sel01 => sel01,sel02 => sel02,sel03 => sel03,sel04 => sel04,sel05 => sel05,sel06 => sel06,sel07 => sel07);muxA: mux_8_to_1 port map( --目的寄存器读出8选1选择器input0 => reg00,input1 => reg01,input2 => reg02,input3 => reg03,input4 => reg04,input5 => reg05,input6 => reg06,input7 => reg07,sel => DR,out_put => output_DR);muxB: mux_8_to_1 port map( --源寄存器读出8选1选择器input0 => reg00,input1 => reg01,input2 => reg02,input3 => reg03,input4 => reg04,input5 => reg05,input6 => reg06,input7 => reg07,sel => SR,out_put => output_SR);end struct;3.1.2 RTL连接图3.1.3 仿真过程仿真结果正确3.2算术逻辑单元设计与仿真3.2.1 设计代码Exe_unit.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;use work.exp_cpu_components.all;entity exe_unit isport(t1: in std_logic;op_code: in std_logic_vector(2 downto 0);zj_instruct: in std_logic;cj_instruct: in std_logic;pc: in std_logic_vector(15 downto 0);pc_inc: in std_logic_vector(15 downto 0);c_in: in std_logic; --以前指令产生的进位Cz_in: in std_logic; --以前指令产生的ZMem_Write: in std_logic; --为1时，写存储器c_tmp: out std_logic;z_tmp: out std_logic;c_z_j_flag: out std_logic; --为1时进行条件转移r_sjmp_addr: in std_logic_vector(15 downto 0); --相对转移地址DW_intruct: in std_logic;sjmp_addr: out std_logic_vector(15 downto 0); --条件转移指令的转移地址SR_data: in std_logic_vector(15 downto 0);DR_data: in std_logic_vector(15 downto 0);Mem_Addr: out std_logic_vector(15 downto 0);cl_stc: in std_logic_vector(1 downto 0); --Stc clc 标记result: out std_logic_vector(15 downto 0) --运算结果);end exe_unit;architecture behav of exe_unit issignal A,B :std_logic_vector(15 downto 0);signal result_t: std_logic_vector(16 downto 0);beginc_z_j_flag <= ((not c_in) and cj_instruct) or ((not z_in) and zj_instruct);A <= DR_data;B <= SR_data;sjmp_addr <= pc_inc + r_sjmp_addr;Mem_Addr_proc: process(t1,SR_data,pc,DW_intruct) --选择存储器地址Mem_Addr beginif t1 = '1' thenMem_Addr <= pc;elseif DW_intruct = '1' thenMem_Addr <= pc_inc;elsif Mem_Write = '1' thenMem_Addr <= DR_data;elseMem_Addr <= SR_data;end if;end if;end process;alu_proc:process(op_code,A,B)begincase op_code iswhen "000" =>result_t <= ('0' & A) + ('0' & B);when "001" =>result_t <= ('0' & A) + ('0' & B)+ c_in;when "010" =>result_t <= ('0' & A) - ('0' & B);when "011" =>result_t <= ('0' & A) - ('0' & B)- c_in;when "100" =>result_t <= ('0' & A) + '1';when "101" =>result_t <= ('0' & A) - '1';when "110" =>result_t <= A & '0';when "111" =>result_t <= "00" & A(15 downto 1);end case;end process;result <= result_t(15 downto 0);c_tmp <= (cl_stc(1) and result_t(16))xor (not cl_stc(1) and cl_stc(0));--if (cl_stc(1)='1') then-- c_tmp <= result_t(16);--else-- c_tmp <= cl_stc(0);--end if;z_tmp <= (not result_t(15)) and (not result_t(14)) and(not result_t(13)) and (not result_t(12)) and(not result_t(11)) and (not result_t(10)) and(not result_t(9)) and (not result_t(8)) and(not result_t(7)) and (not result_t(6)) and(not result_t(5)) and (not result_t(4)) and(not result_t(3)) and (not result_t(2)) and(not result_t(1)) and (not result_t(0));end behav;decoder_unit.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;use work.exp_cpu_components.all;entity decoder_unit isport (IR: in std_logic_vector(15 downto 0);SR: out std_logic_vector(2 downto 0);DR: out std_logic_vector(2 downto 0);op_code: out std_logic_vector(2 downto 0);zj_instruct: out std_logic;cj_instruct: out std_logic;lj_instruct: out std_logic;DRWr: buffer std_logic; --为1时写DR寄存器Mem_Write: out std_logic;DW_intruct: buffer std_logic;change_z: out std_logic;change_c: out std_logic;sel_memdata: out std_logic; --为1时存储器的读出数据作为写入DR的数据r_sjmp_addr: out std_logic_vector(15 downto 0); --相对转移地址cl_stc: out std_logic_vector(1 downto 0) --Stc clc 标记);end decoder_unit;architecture behav of decoder_unit isbeginSR <= IR(7 downto 5);DR <= IR(10 downto 8);sel_memdata <= not IR(15) and IR(14) and (IR(12) xor IR(11));change_z <= (not IR(15)) and (not IR(14)) and IR(1);change_c <= (not IR(15)) and (not IR(14)) and IR(2);DRWr_proc: process(IR) --修改DRWrbeginif IR(15)='0' and IR(14) = '0' then --算术逻辑指令if IR(15) ='1' thenDRWr <= '1';elseDRWr <= '0';end if;elsif IR(10) = '1' and IR(9) = '0' then --MVRD DR,DATA;LDR DR,SR DRWr <= '1';elseDRWr <= '0';end if;end process;sj_addr_proc: process(IR) --条件转移指令的相对转移地址从8位扩展到16位beginif IR(10) ='1' thenr_sjmp_addr <= "11111111" & IR(10 downto 3);elser_sjmp_addr <= "00000000" & IR(10 downto 3);end if;end process;M_instruct:process(IR)begincase IR(15 downto 11) iswhen "01001" | "01100" => --jmp addr;mvrd dr,dataMem_Write <= '0';DW_intruct <= '1';when "01011" => -- str sr,drMem_Write <= '1';DW_intruct <= '0';when others =>Mem_Write <= '0';DW_intruct <= '0';end case;end process;ALUOP_CODE_PROC: P ROCESS(IR) --计算指令beginif IR(15 downto 14) = "00" thenop_code <= IR(13 downto 11);elseop_code <= "111";end if;end process;Jinstruct_PROC: process(IR) --jmp jnc jnzbegincase IR(15 downto 11) iswhen "01100" => --jmp adrzj_instruct <= '0';cj_instruct <= '0';lj_instruct <= '1';when "01111" => --jnc addrzj_instruct <= '0';cj_instruct <= '1';lj_instruct <= '0';when "01101" => --jnz addrzj_instruct <= '1';cj_instruct <= '0';lj_instruct <= '0';when others =>zj_instruct <= '0';cj_instruct <= '0';lj_instruct <= '0';end case;end process;Clc_Stc:process(IR)beginif IR(15)='1' thenif IR(11)='0' thencl_stc <= "00";elsecl_stc <= "01";end if;elsecl_stc <="10";end if;end process;end behav;3.2.2 RTL连接图3.2.3 仿真过程仿真正确4. CPU设计(彭阳坤)4.1取指设计取指部分instru_fetch.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;use work.exp_cpu_components.all;entity instru_fetch isport(reset,clk: in std_logic;data_read: in std_logic_vector(15 downto 0); --存储器读出的数lj_instruct: in std_logic; --长转移指令DW_intruct: in std_logic;c_z_j_flag: in std_logic; --为1时进行条件转移sjmp_addr: in std_logic_vector(15 downto 0); --条件转移指令的转移地址t1,t3: buffer std_logic;pc: buffer std_logic_vector(15 downto 0);pc_inc: buffer std_logic_vector(15 downto 0);IR: out std_logic_vector(15 downto 0));end instru_fetch;architecture behav of instru_fetch issignal start,t2: std_logic;beginIR_poc: process(reset,t2)beginif reset = '0' thenIR <= x"7000"; --nop指令elsif t2'event and t2 = '1' thenIR <= data_read;end if;end process;process(reset,clk)beginif reset = '0' thenstart <= '1';elseif clk'event and clk ='0' thenstart <= '0';end if;end if;end process;process(reset,clk)beginif reset = '0' thent1 <= '0';t2 <= '0';t3 <= '0';elsif clk'event and clk = '1' thent1 <= start or t3;t2 <= t1;t3 <= t2;end if;end process;pc_inc <= pc + '1'; --为取双字指令的第2个字或者计算相对转移地址做准备PC_proc: process(reset,t3)beginif reset = '0' thenpc <= x"0000";elsif t3'event and t3 = '0' thenif lj_instruct = '1' thenpc <= data_read;elsif c_z_j_flag ='1' thenpc <= sjmp_addr;elsif DW_intruct = '1' thenpc <= pc + "10";elsepc <= pc_inc;end if;end if;end process;end behav;4.2 时序节拍设计4.3指令译码的设计指令译码部分decoder_unit.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;use work.exp_cpu_components.all;entity decoder_unit isport (IR: in std_logic_vector(15 downto 0);SR: out std_logic_vector(2 downto 0);DR: out std_logic_vector(2 downto 0);op_code: out std_logic_vector(2 downto 0);zj_instruct: out std_logic;cj_instruct: out std_logic;lj_instruct: out std_logic;DRWr: buffer std_logic; --为1时写DR寄存器Mem_Write: out std_logic;DW_intruct: buffer std_logic;change_z: out std_logic;change_c: out std_logic;sel_memdata: out std_logic; --为1时存储器的读出数据作为写入DR的数据r_sjmp_addr: out std_logic_vector(15 downto 0); --相对转移地址cl_stc: out std_logic_vector(1 downto 0) --Stc clc 标记);end decoder_unit;architecture behav of decoder_unit isbeginSR <= IR(7 downto 5);DR <= IR(10 downto 8);sel_memdata <= not IR(15) and IR(14) and (IR(12) xor IR(11));change_z <= (not IR(15)) and (not IR(14)) and IR(1);change_c <= (not IR(15)) and (not IR(14)) and IR(2);DRWr_proc: process(IR) --修改DRWrbeginif IR(15)='0' and IR(14) = '0' then --算术逻辑指令if IR(15) ='1' thenDRWr <= '1';elseDRWr <= '0';end if;elsif IR(10) = '1' and IR(9) = '0' then --MVRD DR,DATA;LDR DR,SR DRWr <= '1';elseDRWr <= '0';end if;end process;sj_addr_proc: process(IR) --条件转移指令的相对转移地址从8位扩展到16位beginif IR(10) ='1' thenr_sjmp_addr <= "11111111" & IR(10 downto 3);elser_sjmp_addr <= "00000000" & IR(10 downto 3);end if;end process;M_instruct:process(IR)begincase IR(15 downto 11) iswhen "01001" | "01100" => --jmp addr;mvrd dr,dataMem_Write <= '0';DW_intruct <= '1';when "01011" => -- str sr,drMem_Write <= '1';DW_intruct <= '0';when others =>Mem_Write <= '0';DW_intruct <= '0';end case;end process;ALUOP_CODE_PROC: PROCESS(IR) --计算指令beginif IR(15 downto 14) = "00" thenop_code <= IR(13 downto 11);elseop_code <= "111";end if;end process;Jinstruct_PROC: process(IR) --jmp jnc jnz begincase IR(15 downto 11) iswhen "01100" => --jmp adrzj_instruct <= '0';cj_instruct <= '0';lj_instruct <= '1';when "01111" => --jnc addrzj_instruct <= '0';cj_instruct <= '1';lj_instruct <= '0';when "01101" => --jnz addrzj_instruct <= '1';cj_instruct <= '0';lj_instruct <= '0';when others =>zj_instruct <= '0';cj_instruct <= '0';lj_instruct <= '0';end case;end process;Clc_Stc:process(IR)beginif IR(15)='1' thenif IR(11)='0' thencl_stc <= "00";elsecl_stc <= "01";end if;elsecl_stc <="10";end if;end process;end behav;4.4执行部分设计执行部分exe_unit.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;use work.exp_cpu_components.all;entity exe_unit isport(t1: in std_logic;op_code: in std_logic_vector(2 downto 0);zj_instruct: in std_logic;cj_instruct: in std_logic;pc: in std_logic_vector(15 downto 0);pc_inc: in std_logic_vector(15 downto 0);c_in: in std_logic; --以前指令产生的进位Cz_in: in std_logic; --以前指令产生的ZMem_Write: in std_logic; --为1时，写存储器c_tmp: out std_logic;z_tmp: out std_logic;c_z_j_flag: out std_logic; --为1时进行条件转移r_sjmp_addr: in std_logic_vector(15 downto 0); --相对转移地址DW_intruct: in std_logic;sjmp_addr: out std_logic_vector(15 downto 0); --条件转移指令的转移地址SR_data: in std_logic_vector(15 downto 0);DR_data: in std_logic_vector(15 downto 0);Mem_Addr: out std_logic_vector(15 downto 0);cl_stc: in std_logic_vector(1 downto 0); --Stc clc 标记result: out std_logic_vector(15 downto 0) --运算结果);end exe_unit;architecture behav of exe_unit issignal A,B :std_logic_vector(15 downto 0);signal result_t: std_logic_vector(16 downto 0);beginc_z_j_flag <= ((not c_in) and cj_instruct) or ((not z_in) and zj_instruct);A <= DR_data;B <= SR_data;sjmp_addr <= pc_inc + r_sjmp_addr;Mem_Addr_proc: process(t1,SR_data,pc,DW_intruct) --选择存储器地址Mem_Addr beginif t1 = '1' thenMem_Addr <= pc;elseif DW_intruct = '1' thenMem_Addr <= pc_inc;elsif Mem_Write = '1' thenMem_Addr <= DR_data;elseMem_Addr <= SR_data;end if;end if;end process;alu_proc:process(op_code,A,B)begincase op_code iswhen "000" =>result_t <= ('0' & A) + ('0' & B);when "001" =>result_t <= ('0' & A) + ('0' & B)+ c_in;when "010" =>result_t <= ('0' & A) - ('0' & B);when "011" =>result_t <= ('0' & A) - ('0' & B)- c_in;when "100" =>result_t <= ('0' & A) + '1';when "101" =>result_t <= ('0' & A) - '1';when "110" =>result_t <= A & '0';when "111" =>result_t <= "00" & A(15 downto 1);end case;end process;result <= result_t(15 downto 0);c_tmp <= (cl_stc(1) and result_t(16))xor (not cl_stc(1) and cl_stc(0));--if (cl_stc(1)='1') then-- c_tmp <= result_t(16);--else-- c_tmp <= cl_stc(0);--end if;z_tmp <= (not result_t(15)) and (not result_t(14)) and(not result_t(13)) and (not result_t(12)) and(not result_t(11)) and (not result_t(10)) and(not result_t(9)) and (not result_t(8)) and(not result_t(7)) and (not result_t(6)) and(not result_t(5)) and (not result_t(4)) and(not result_t(3)) and (not result_t(2)) and(not result_t(1)) and (not result_t(0));end behav;4.5存储器部分设计存储器部分memory_unit.vhdlibrary ieee;use ieee.std_logic_1164.all;use work.exp_cpu_components.all;entity memory_unit isport(reset: in std_logic;clk,t3: in std_logic;Mem_addr: in std_logic_vector(15 downto 0);Mem_Write: in std_logic;sel_memdata: in std_logic; --为1时存储器的读出数据作为写入DR的数据SR_data: in std_logic_vector(15 downto 0); --写存储器的数据result: in std_logic_vector(15 downto 0); --运算结果rw: out std_logic;ob: inout std_logic_vector(15 downto 0);ar: out std_logic_vector(15 downto 0);data_read: buffer std_logic_vector(15 downto 0); --从存储器读出的指令或者数据DR_data_out: out std_logic_vector(15 downto 0) --写入DR的数据);end memory_unit;architecture behav of memory_unit isbeginar <= Mem_addr;R_W_Memory_proc: process(reset,ob,SR_data,clk,t3,Mem_Write) --读写存储器处理beginif reset = '0' thenrw <= '1';ob <= "ZZZZZZZZZZZZZZZZ"; --将存储器数据总线置为高阻，读存储器 elseif Mem_Write = '1' and t3 = '1' thenob <= SR_DATA; --写存储器rw <= clk;elseob <= "ZZZZZZZZZZZZZZZZ"; --将存储器数据总线置为高阻，读存储器rw <= '1';data_read <= ob;end if;end if;end process;sele_DR_proc: process(sel_memdata,data_read,result)beginif sel_memdata = '1' thenDR_data_out <= data_read; --存储器数据作为写DR的数据elseDR_data_out <= result; --运算结果作为写DR的数据end if;end process;end behav;4.6通用寄存器组设计①寄存器reglibrary ieee;use ieee.std_logic_1164.all;entity reg is port(reset: in std_logic;d_input: in std_logic_vector(15 downto 0);clk: in std_logic;write: in std_logic;sel: in std_logic;q_output: out std_logic_vector(15 downto 0));end reg;architecture a OF reg isbeginprocess(reset,clk)beginIF reset = '0' thenq_output <= x"0000";elsif clk'event and clk = '0' then --时钟下降沿触发if sel ='1' and write = '1' thenq_output <= d_input;end if;end if;end process;end a;②3-8译码器Decoder_3_to_8.vhdlibrary ieee;use ieee.std_logic_1164.all;entity decoder_3_to_8 isport (sel: in std_logic_vector(2 downto 0);sel00: out std_logic;sel01: out std_logic;sel02: out std_logic;sel03: out std_logic;sel04: out std_logic;sel05: out std_logic;sel06: out std_logic;sel07: out std_logic);end decoder_3_to_8;architecture behavioral of decoder_3_to_8 isbeginsel00 <= (not sel(2)) and (not sel(1)) and (not sel(0));sel01 <= (not sel(2)) and (not sel(1)) and sel(0) ;sel02 <= (not sel(2)) and sel(1) and (not sel(0)) ;sel03 <= (not sel(2)) and sel(1) and sel(0) ;sel04 <= sel(2) and (not sel(1)) and (not sel(0));sel05 <= sel(2) and (not sel(1)) and sel(0);sel06 <= sel(2) and sel(1) and (not sel(0));sel07 <= sel(2) and sel(1) and sel(0);end behavioral;③8选1选择器mux_8_to_1.vhdlibrary ieee;use ieee.std_logic_1164.all;entity mux_8_to_1 isport (input0,input1,input2,input3,input4,input5,input6,input7: in std_logic_vector(15 downto 0);sel: in std_logic_vector(2 downto 0);out_put: out std_logic_vector(15 downto 0));end mux_8_to_1;architecture behavioral of mux_8_to_1 isbeginmux: process(sel, input0, input1, input2, input3,input4,input5,input6,input7) begincase sel iswhen "000" =>out_put <= input0;when "001" =>out_put <= input1;when "010" =>out_put <= input2;when "011" =>out_put <= input3;when "100" =>out_put <= input4;when "101" =>out_put <= input5;when "110" =>out_put <= input6;when "111" =>out_put <= input7;end case;end process;end behavioral;④通用寄存器组regfilelibrary ieee;use ieee.std_logic_1164.all;use work.exp_cpu_components.all;entity regfile isPort ( DR: in std_logic_vector(2 downto 0); --目的寄存器号SR: in std_logic_vector(2 downto 0); --源寄存器号reset: in std_logic;write: in std_logic; --写寄存器信号clk: in std_logic;d_input: in std_logic_vector(15 downto 0); --写寄存器的数据change_z: in std_logic; --如果为1，则重新设置z标志change_c: in std_logic;c_in: in std_logic;z_in: in std_logic;output_DR: out std_logic_vector(15 downto 0);output_SR: out std_logic_vector(15 downto 0);c_out: out std_logic;z_out: out std_logic);end regfile;architecture struct of regfile issignal reg00, reg01, reg02,reg03,reg04,reg05,reg06,reg07: std_logic_vector(15 downto 0); signal sel00, sel01, sel02,sel03,sel04,sel05,sel06,sel07: std_logic;beginz_c_proc: process(reset,clk) --对指令执行结束后的z、c标志进行处理beginif reset = '0' thenz_out <= '0';c_out <= '0';elsif clk'event and clk = '0' thenif change_z = '1' thenz_out <= z_in;end if;if change_c = '1' thenc_out <= c_in;end if;end if;end process;Areg00: reg port map( --寄存器R0reset => reset,d_input => d_input,clk => clk,。