2014.9摩尔及米利型状态机的VerilogHDL描述方法

例1：MOORE 型状态机
设某个控制器的状态转换图如下所示： 输入：in 、时钟clk 、和复位信号
输出：out
用Verilog
将NS 、 OL 、 CS module statmach(clk, in, reset, out); input clk, reset; //时钟、复位信号 input in; //输入 output out; reg out; //输出
reg current_state; //现态寄存器
reg next_state; //次态寄存器，NS 与CS 分开描述时必须定义
parameter s0 = 0, s1 = 1; //状态编码
always @( current_state or in )
begin
case (current_state) s0: if(in) next _state<=s1;
else if (!in) next _state<=s0 s1:
if(in) next _state<=s0; else if (!in) next _state<=s1default: next _state<=s0； endcase
end
always @(posedge clk ) begin if (reset)
current_state <= s0;
else current_state<= next end
always @( current_state )
in=0
状态编码：S0=0，S1=1。

in=0
时钟CS NS OL 复位
begin case (current_state) s0: out <= 0;
s1:
out <= 1; default:
out <= x;
endcase end endmodule
将CS 与NS 混合描述，OL 单独描述：
module statmach(clk, in, reset, out); input clk, reset; //时钟、复位信号 input in; //输入
output out; //输出 reg out;
reg current_state; //现态寄存器
parameter s0 = 0, s1 = 1; //状态编码
always @(posedge clk ) begin if (reset) current_state = s0; else case (current_state) s0:
if (in) current_state = s1;
else if (!in)
current_state = s0;
s1: if (in) current_state = s0; else if (!in) current_state = s1;
default: current_state = s0;
endcase end
in=0
OL
时钟CS
NS
OL
MOORE 型状态机结构图
复位
always @(current_state ) begin
case (current_state) s0: out = 0; s1: out = 1;
default:
out = x;
endcase end
endmodule
将CS 、NS 、OL 均混合描述：
module statmach(clk, in, reset, out); input clk, reset; //时钟、复位信号 input in; //输入
output out; //输出 reg out;
reg current_state; //现态寄存器
parameter s0 = 0, s1 = 1; //状态编码
always @(posedge clk ) begin if (reset) current_state = s0; else case (current_state) s0:
begin out = 0;
if (in) current_state = s1;
else if (!in)
s1:
begin out = 1; if (in) current_state = s0; else if (!in) current_state = s1; end
default: current_state = s0;
endcase
OL
in=0
时钟CS
NS
OL
MOORE 型状态机结构图
复位
end
endmodule
例2：MEALY 型状态机
状态转换图：
将CS 与NS 混合描述，OL 单独描述：
（无法全部混合描述） module statmach(clk, in, reset, out);
input clk, reset; //时钟、复位信号 input in; //输入 output out; //输出 reg out;
reg current_state; //现态寄存器
parameter s0 = 0, s1 = 1; //状态编码
always @(posedge clk ) begin if (reset) current_state = s0; else case (current_state) s0:
if (in) current_state = s1;
else if (!in)
current_state = s0;
s1: if (in) current_state = s0; else if (!in) current_state = s1;
default: current_state = s0;
endcase end
in=0
in=0/out=0
in=0/out=1
always @(
begin case (current_state ) s0:
if(in) out = 1; s1:
if(in) out = 0;
default:
out = x;
endcase end
endmodule
例3：带流水线的MEALY 型状态机
将CS 、NS 与OL 混合描述： module statmach(clk, in, reset, out); input clk, reset; //时钟、复位信号 input in; //输入
output out; //输出 reg out;
reg current_state; //现态寄存器
parameter s0 = 0, s1 = 1; //状态编码
in=0/out=1
always @(posedge clk ) begin if (reset) current_state = s0; else case (current_state) s0:
if (in)begin
out = 1;
current_state = s1;end else begin out = 0;
current_state = s0; end
s1: if (in)begin out = 0;
current_state = s0;end else begin
out = 1;current_state = s1; end
default: begin current_state = s0; out = x; end
endcase end
endmodule
in=0/out=1。