基于Cadence的信号完整性仿真步骤
cadence信号完整性仿真步骤
IntroductionConsider the proverb, “It takes a village to raise a child.” Similarly, multiple design team members participate in assuring PCB power integrity (PI) as a design moves from the early concept phase to becoming a mature product. On the front end, there’s the electrical design engineer who is responsible for the schematic. On the back end, the layout designer handles physical implemen-tation. Typically, a PI analysis expert is responsible for overall PCB PI and steps in early on to guide the contributions of others. How quickly a team can assure PCB PI relates to the effectiveness of that team. In this paper, we will take a look at currently popular analysis approaches to PCB PI. We will also introduce a team-based approach to PCB PI that yieldsadvantages in resource utilization and analysis results.Common Power Integrity Analysis MethodsThere are two distinct facets of PCB PI – DC and AC. DC PI guarantees thatadequate DC voltage is delivered to all active devices mounted on a PCB (oftenusing IR drop analysis). This helps to assure that constraints are met for currentdensity in planar metals and total current of vias and also that temperatureconstraints are met for metals and substrate materials. AC PI concerns thedelivery of AC current to mounted devices to support their switching activitywhile meeting constraints for transient noise voltage levels within the powerdelivery network (PDN). The PDN noise margin (variation from nominalvoltage) is a sum of both DC IR drop and AC noise.DC PI is governed by resistance of the metals and the current pulled from thePDN by each mounted device. Engineers have, for many years, applied resistivenetwork models for approximate DC PI analysis. Now that computer speedsare faster and larger addressable memory is available, the industry is seeingmuch more application of layout-driven detailed numerical analysis techniquesfor DC PI. Approximation occurs less, accuracy is higher, and automation ofHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsBy Brad Brim, Sr. Staff Product Engineer, Cadence Design SystemsAssuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process.ContentsIntroduction (1)Common Power IntegrityAnalysis Methods (1)Applying a Team-Based Approachto Power Integrity Analysis (3)Summary (6)For Further Information (7)whole-design analysis and postprocessing results are commonly available commercially. In fact, DC PI analysis for PCB designs has become a “signoff” requirement for many OEMs. See Figure 1 (left) for typical results for current density.Since metal conductivity is temperature-dependent, DC IR drop is a nonlinear analysis. IR drop results can vary by more than 20% when temperature effects are considered, according to case studies for high-power designs. There is, however, a way to accurately characterize PCB IR drop while assuring that the PDN noise margin isn’twasted. Using a DC analysis tool that provides capabilities such as electrical/thermal co-simulation, perform a linear electrical analysis at ambient temperature; take the resulting power loss and apply it to perform a linear thermal analysis. Then, perform another linear electrical analysis with consideration of the localized temperature-dependent conductivity. This process converges in just a few iterations to yield a desired result. See Figure 1 for an illustration of this solution, as implemented in the Cadence ® Sigrity ™ PowerDC ™DC analysis tool.TemperatureLoss DensityPlane Current Surface TemperatureElectrical Analysis Thermal AnalysisFigure 1: Current density (left) and temperature distribution (right) for a PCB design due to DC powerdelivery as two linear solutions are iteratively linked to address nonlinear electro-thermal analysis.AC PI is governed by voltage regulator modules, loop inductances, decoupling capacitors (decaps), and plane capacitance. AC PI effects tend to be global in nature due to plane resonances, plane-to-plane coupling, and shared reference planes. As such, this calls for full-board analysis, as well as more resource-intensive analysis algorithms. A hybrid of circuit theory and electromagnetic (EM) analyses is the most commonly applied AC PI analysis for PCBs. This type of analysis is available in the frequency domain to extract S-parameters, using a tool such as Cadence Sigrity PowerSI ™ frequency-domain electrical analysis solution. It’s also available in the time domain to directly generate transient waveforms, using a tool such as Cadence Sigrity Speed2000™ time-domain analysis solution. With the proper tools, an engineer can, in tens of minutes, accurately characterize the PDNbehavior of even the largest and most complex PCBs from DC to multi-gigahertz using single- to low double-digit gigabytes of memory.Transient PI analysis may seem attractive because it directly yields noise waveforms; however, in reality, it is less commonly applied than frequency-domain impedance analysis. “Target impedance” profiles are applied as PIconstraints. Lower impedance corresponds to lower transient noise. Without direct vendor specification, reasonable target impedance may be estimated based on device specifications for voltage ripple and AC switching current. See Figure 2 for a comparison of frequency-domain and time-domain results. In this comparison, the Cadence Sigrity OptimizePI ™ tool was used to significantly reduce an impedance peak near 800MHz by applying an alternate set of decaps to mount for a DIMM module. This solution reduced peak-to-peak PDN noise for the optimized design by 12% and the component and manufacturing cost of the decap implementation by 21%.Figure 2: Impedance profile and transient PDN noise of a DIMM before and after thedecap implementation was optimized.Applying a Team-Based Approach to Power Integrity AnalysisTraditionally, PI experts have performed pre-layout decap selections and initial IR drop analyses. This is a substantial time investment at the front end of a design for a back-end-focused expert. By applying a more collaborative approach, a design team can make better use of its resources and expertise, and generate more impactful results.A team could set up simple analyses that yield actionable results and that could be performed by other members of the PI team. This PCB PI team would ideally consist of three key members: design engineer, layout designer, and PI analysis expert, as shown in Figure 3.Design Engineer•Can start with either BOM or schematic•Apply Power Feasibility Editor for DeCap selection and PIconstraint definitionLayout Designer•Can start as early asfloorplanning stage•First order analysis directlyon layout•Analyze, edit, re-analyze•DeCap placement guidanceand DRCPI Analysis Expert•Can start at any stage•Leverages setup and datafrom rest of team•Signoff capable detailedanalysisFigure 3: Roles and responsibilities of the PCB PI design team.There is now a tool available on the market that supports team-based PCB PI analysis. Cadence Allegro® SigrityPI is the industry’s first front-to-back, constraint-based PI approach for PCB and IC package designs. This tool differs from other solutions in the way that it accesses existing analysis algorithms and how the analysis resultsare applied. In addition, the tool also provides PI-focused infrastructure support of non-analysis tasks. As a result, design engineers and layout designers can contribute earlier and more effectively to PCB PI. The DC and AC PI analysis capabilities described in the previous section are available in the associated Power Integrity Signoff and Optimization Option.PCB design engineers are responsible for front-end tasks. They must generate an initial Bill of Materials (BOM)to set in motion cost feasibility studies and assure electrical design intent by generating circuit schematics. They typically work independently of DC PI concerns. However, to support AC PI, design engineers must add decaps and include them in the BOM and the schematic. Some device vendors provide datasheet guidance for decap selection (type and/or quantity), but many do not. Even with datasheet guidance, it is tedious for design engineers to assemble and interpret the specifications for each device, instantiate all the unique components, assure they appear logically in the schematic, etc. No mechanism has existed for physical placement guidance to be communicated for back-end application.With constraint-based design methods, engineers gain a uniform interface for design-intent information and for automating a broad class of tasks across front-to-back flows. PI [electrical] constraint sets (PI Csets) have been added to save all component-level PI information. Design engineers may apply PI Csets to quickly and completely define PI design intent for all mounted components. PI Csets also automate instantiation of components and inclusion in the BOM.Refer to Figure 4 for an example of a PI Cset in Allegro Sigrity PI. PI Csets contain information for each power rail, including decap component names, quantity of each component, package type, and physical placement guidance.Figure 4: PI constraint set contents viewed from the constraint manager.PI Cset creation is automated by the tool’s Power Feasibility Editor, which provides a mechanism to enter datasheet decap selection and physical placement guidance. Figure 5 shows a view of the tool’s Power Feasibility Editor. In addition to placement guidance, a PI Cset communicates to the layout designer component and power rail associ-ation for decaps, helping the designer perform more reliable placement.Figure 5: Single-point analysis results in the Power Feasibility Editor.The Power Feasibility Editor also provides access to approximate and detailed pre-layout analysis for selectionand placement of decaps. High-level specifications are made to generate target impedance profiles when device vendors do not provide them. An approximate PI analysis called “single-point” is provided for interactive decap selection. For more detailed pre-layout, the tool provides access to the data in the Cadence Sigrity OptimizePI tool. The engineer simply clicks a button within the Power Feasibility Editor to generate PI Csets.Figure 6: Split-screen view of layout (left) and IR drop analysis results (right).Unlike design engineers, layout designers are concerned with DC PI issues. Layout designers control metal shapes and vias and these, in turn, control PI behaviors for DC IR drop and current flow. Layout designers can intuitively understand and act upon analysis results for these DC PI effects. The Allegro Sigrity PI tool provides access within the layout environment to the setup and results display for DC IR drop and current constraint analyses. DC analysis is fast, though not conducted in real time in order to enable dynamic updating of analysis results as layout updates are made.The tool provides a split-screen view, as shown in Figure 6, to support a fixed view of analysis results as layout designers dynamically make updates to address IR drop or current constraint issues. The two views are synchro-nized for operations that affect the display, such as layer changes, zoom, and pan. Layout designers can apply this split-screen view of DC analysis results as they craft an initial layout, before the PI analysis expert gets involved.As a more effective method to communicate where PI issues exist in the design, the split-screen view can also be applied with detailed analysis results performed separately by PI analysis experts. In fact, to more quickly verify improved PI performance, the layout designer can launch the same detailed analysis performed by the PI analyst. Layout designers strongly influence AC PI success with their placement of decaps. Decaps placed close to a device generally benefit PI, but restrict routing channels due to decap mounting vias. Decaps placed too far from a device will be ineffective at providing switching current to the device and will negatively affect PI. Present design methods do not typically provide decap placement guidance, including information as simple as which device is associated with a decap. By conveying design intent, previously described PI Csets enable more effective placement of decaps by layout designers. The associated device and power rail and placement guidance are all specified in the PI Cset.A decap placement mode is implemented to support layout designers, as shown in Figure 7. Simply select a mounted component and a power rail, and then cycle through a point-and-click placement process. The selected device is highlighted and three optional visual placement guidance displays are available: device to decap distance for top layer, device to decap distance for bottom layer, and decap effective radius. The first two are defined in the PI Cset and are conceptually familiar. The decap effective radius is the maximum distance at which the decap will be maximally effective. It is a function of the stack-up and decap mounting parasitics as well as the decap value and its intrinsic parasitics. It is dynamically computed as the cursor moves due to local availability of metal shapes on the associated power and ground layers.Decap Placement GuidanceTop-sideSetbackDistance*DecapEffectiveRadiusBottom-sideSetbackDistanceFigure 7: Layout view during decap placement for device U0501 with top (yellow) and bottom (blue)setback distances and decap effective radius (white circle) displayedTo ease the setup for detailed PI analysis, design intent and analysis setup information specified by design engineers and layout designers is available to PI analysis. PI Csets serve as a convenient mechanism to communicate updated placement guidance or requirements for updates on decap selection (either type or quantity) for a specific device instance or all devices to which a PI Cset is applied. Changes to PI Csets also convey information back to the design engineer and enable automated update of the schematic and BOM.SummaryWhile current PCB PI analysis tools are continuing to serve the design community well, they are even more effective when combined with a front-to-back, constraint-based approach. Under this type of methodology, each design team member can more efficiently accomplish his or her individual tasks and communicate design intent infor-mation to colleagues for increased efficiency of the overall PCB design flow. This approach provides access toactionable analysis results where they are most impactful. It also leverages earlier defined analysis setup infor-mation for the PI expert, and eases communication of design changes from his or her back-end role to front-end colleagues.For Further InformationTo learn more about Cadence Allegro Sigrity PI solution, visit: /products/sigrity/Pages/ solution.aspxCadence Design Systems enables global electronic design innovation and plays an essential role in thecreation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to designand verify today’s mobile, cloud and connectivity applications. © 2014 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks and OptimizePI,PowerDC, PowerSI, Sigrity, and Speed2000 are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders.。
cadence信号完整性仿真步骤.
IntroductionConsider the proverb, “It takes a village to raise a child.” Similarly, multiple design team members participate in assuring PCB power integrity (PI as a design moves from the early concept phase to becoming a mature product. On the front end, there’s the electrical design engineer who is responsible for the schematic. On the back end, the layout designer handles physical implemen-tation. Typically, a PI analysis expert is responsible for overall PCB PI and steps in early on to guide the contributions of others. How quickly a team can assure PCB PI relates to the effectiveness of that team. In this paper, we will take a look at currently popular analysis approaches to PCB PI. We will also introduce a team-based approach to PCB PI that yieldsadvantages in resource utilization and analysis results.Common Power Integrity Analysis MethodsThere are two distinct facets of PCB PI – DC and AC. DC PI guarantees thatadequate DC voltage is delivered to all active devices mounted on a PCB (oftenusing IR drop analysis. This helps to assure that constraints are met for currentdensity in planar metals and total current of vias and also that temperatureconstraints are met for metals and substrate materials. AC PI concerns thedelivery of AC current to mounted devices to support their switching activitywhile meeting constraints for transient noise voltage levels within the powerdelivery network (PDN. The PDN noise margin (variation from nominalvoltage is a sum of both DC IR drop and AC noise.DC PI is governed by resistance of the metals and the current pulled from thePDN by each mounted device. Engineers have, for many years, applied resistivenetwork models for approximate DC PI analysis. Now that computer speedsare faster and larger addressable memory is available, the industry is seeingmuch more application of layout-driven detailed numerical analysis techniquesfor DC PI. Approximation occurs less, accuracy is higher, and automation ofHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsBy Brad Brim, Sr. Staff Product Engineer, Cadence Design SystemsAssuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process.ContentsIntroduction . (1)Common Power IntegrityAnalysis Methods . (1)Applying a Team-Based Approachto Power Integrity Analysis . (3)Summary (6)For Further Information . (7)whole-design analysis and postprocessing results are commonly available commercially. In fact, DC PI analysis for PCB designs has become a “signoff” requirement for many OEMs. See Figure 1 (left for typical results for current density.Since metal conductivity is temperature-dependent, DC IR drop is a nonlinear analysis. IR drop results can vary by more than 20% when temperature effects are considered, according to case studies for high-power designs. There is, however, a way to accurately characterize PCB IR drop wh ile assuring that the PDN noise margin isn’twasted. Using a DC analysis tool that provides capabilities such as electrical/thermal co-simulation, perform a linear electrical analysis at ambient temperature; take the resulting power loss and apply it to perform a linear thermal analysis. Then, perform another linear electrical analysis with consideration of the localized temperature-dependent conductivity. This process converges in just a few iterations to yield a desired result. See Figure 1 for an illustration of this solution, as implemented in the Cadence® Sigrity™ PowerDC™DC analysis tool.TemperatureLoss DensityPlane CurrentSurface TemperatureElectrical AnalysisThermal AnalysisFigure 1: Current density (left and temperature distribution (right for a PCB design due to DC powerdelivery as two linear solutions are iteratively linked to address nonlinear electro-thermal analysis.AC PI is governed by voltage regulator modules, loop inductances, decoupling capacitors (decaps, and plane capacitance. AC PI effects tend to be global in nature dueto plane resonances, plane-to-plane coupling, and shared reference planes. As such, this calls for full-board analysis, as well as more resource-intensive analysis algorithms. A hybrid of circuit theory and electromagnetic (EM analyses is the most commonly applied AC PI analysis for PCBs. This type of analysis is available in the frequency domain to extract S-parameters, using a tool such as Cadence Sigrity PowerSI™ frequency-domain electrical analysis solution. It’s also available in the time domain to directly generate transient waveforms, using a tool such as Cadence Sigrity Speed2000™ time-domain analysis solution. With the proper tools, an engineer can, in tens of minutes, accurately characterize the PDNbehavior of even the largest and most complex PCBs from DC to multi-gigahertz using single- to low double-digit gigabytes of memory.Transient PI analysis may seem attractive because it directly yields noise waveforms; however, in reality, it is less commonly applied than frequency-domain impedance analysis. “Target impedance” profiles are applied as PIconstraints. Lower impedance corresponds to lower transient noise. Without direct vendor specification, reasonable target impedance may be estimated based on device specifications for voltage ripple and AC switching current. See Figure 2 for a comparison of frequency-domain and time-domain results. In this comparison, the Cadence Sigrity OptimizePI ™ tool was used to significantly reduce an impedance peak near 800MHz by applying an alternate set of decaps to mount for a DIMM module. This solution reduced peak-to-peak PDN noise for the optimized design by 12% and the component and manufacturing cost of the decap implementation by 21%. 2How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsFigure 2: Impedance profile and transient PDN noise of a DIMM before and after thedecap implementation was optimized.Applying a Team-Based Approach to Power Integrity AnalysisTraditionally, PI experts have performed pre-layout decap selections and initial IR drop analyses. This is a substantial time investment at the front end of a design for a back-end-focused expert. By applying a more collaborativeapproach, a design team can make better use of its resources and expertise, and generate more impactful results.A team could set up simple analyses that yield actionable results and that could be performed by other members of the PI team. This PCB PI team would ideally consist ofthree key members: design engineer, layout designer, and PI analysis expert, as shown in Figure 3.Design Engineer•Can start with either BOM or schematic•Apply Power Feasibility Editor for DeCapselection and PIconstraint definitionLayout Designer•Can start as early as floorplanning stage •First order analysis directly on layout•Analyze, edit, re-analyze•DeCap placement guidanceand DRCPI Analysis Expert•Can start at any stage•Leverages setup and data from rest of team•Signoff capable detailed analysis Figure 3: Roles and responsibilities of the PCB PI design team. 3How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsThere is now a tool available on the market that supports team-based PCB PI analysis. Cadence A llegro® Sigrity PI is the industry’s first front-to-back, constraint-based PI approach for PCB and IC package designs. This tool differs from other solutions in the way that it accesses existing analysis algorithms and how the analysis results are applied. In addition, the tool also provides PI-focused infrastructure support of non-analysis tasks. As a result, design engineers and layout designers can contribute earlierand more effectively to PCB PI. The DC and AC PI analysis capabilities described in the previous section are available in the associated Power Integrity Signoff and Optimization Option.PCB design engineers are responsible for front-end tasks. They must generate an initial Bill of Materials (BOM to set in motion cost feasibility studies and assure electrical design intent by generating circuit schematics. They typically work independently of DC PI concerns. However, to support AC PI, design engineers must add decaps and include them in the BOM and the schematic. Some device vendors provide datasheet guidance for decap selection (type and/or quantity, but many do not. Even with datasheet guidance, it is tedious for design engineers toassemble and interpret the specifications for each device, instantiate all the unique components, assure they appear logically in the schematic, etc. No mechanism has existed for physical placement guidance to be communicated for back-end application.With constraint-based design methods, engineers gain a uniform interface for design-intent information and for automating a broad class of tasks across front-to-back flows. PI [electrical] constraint sets (PI Csets have been added to save all component-level PI information. Design engineers may apply PI Csets to quickly and completely define PI design intent for all mounted components. PI Csets also automate instantiation of components and inclusion in the BOM.Refer to Figure 4 for an example of a PI Cset in Allegro Sigrity PI. PI Csets contain information for each power rail,including decap component names, quantity of each component, package type, and physical placement guidance.Figure 4: PI constraint set contents viewed from the constraint manager.PI Cset creation is automated by the tool’s Power Feasibility Editor, which providesa mechanism to enter datasheet decap selection and physical placement guidance. Figure5 shows a view of the tool’s Power Feasibility Editor. In addition to placement guidance,a PI Cset communicates to the layout designer component and power rail associ-ation for decaps, helping the designer perform more reliable placement. 4How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsFigure 5: Single-point analysis results in the Power Feasibility Editor.The Power Feasibility Editor also provides access to approximate and detailed pre-layout analysis for selection and placement of decaps. High-level specifications are made to generate target impedance profiles when device vendors do not provide them. An approximate PI analysis called “single-point” is provided for interactive decap selection. For more detailed pre-layout, the tool provides access to the data in the Cadence Sigrity OptimizePI tool.The engineer simply clicks a button within the Power Feasibility Editor to generate PI Csets.Figure 6: Split-screen view of layout (left and IR drop analysis results (right.Unlike design engineers, layout designers are concerned with DC PI issues. Layout designers control metal shapes and vias and these, in turn, control PI behaviors for DC IR drop and current flow. Layout designers can intuitively understand and act upon analysis results for these DC PI effects. The Allegro Sigrity PI tool provides access within the layout environment to the setup and results display for DC IR drop and current constraint analyses. DC analysis is fast, though not conducted in real time in order to enable dynamic updating of analysis results as layout updates are made. 5How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results The tool provides a split-screen view, as shown in Figure 6, to support a fixedview of analysis results as layout designers dynamically make updates to address IR drop or current constraint issues. The two views are synchronized for operations that affect the display, such as layer changes, zoom, and pan. Layout designers can apply this split-screen view of DC analysis results as they craft an initial layout, before the PI analysis expert gets involved. As a more effective method to communicate where PI issues exist in the design, the split-screen view can also be applied with detailed analysis results performed separately by PI analysis experts. In fact, to more quickly verify improved PI performance, the layout designer can launch the same detailed analysis performed by the PI analyst. Layout designers strongly influence AC PI success with their placement of decaps. Decaps placed close to a device generally benefit PI, but restrict routing channels due to decap mounting vias. Decaps placed too far from a device will be ineffective at providing switching current to the device and will negatively affect PI. Present design methods do not typically provide decap placement guidance, including information as simple as which device is associated with a decap. By conveying design intent, previously described PI Csets enable more effective placement of decaps by layout designers. The associated device and power rail and placement guidance are all specified in the PI Cset. A decap placement mode is implemented to support layout designers, as shown in Figure 7. Simply select a mounted component and a power rail, and then cycle through a point-and-click placement process. The selected device is highlighted and three optional visual placement guidance displays are available: device to decap distance for top layer, device to decap distance for bottom layer, and decap effective radius. The first two are defined in the PI Cset and are conceptually familiar. The decap effective radius is the maximum distance at which the decap will be maximally effective. It is a function of the stack-up and decap mounting parasitics as well as the decap value and its intrinsic parasitics. It is dynamically computed as the cursor moves due to local availability of metal shapes on the associated power and ground layers. Decap Placement Guidance Top-side Setback Distance * Decap Effective Radius Bottom-side Setback Distance Figure 7: Layout view during decap placement for device U0501 with top (yellow andbottom (blue setback distances and decap effective radius (white circle displayed To ease the setup for detailed PI analysis, design intent and analysis setup information specified by design engineers and layout designers is available to PI analysis. PI Csets serve as a convenient mechanism to communicate updated placement guidance or requirements for updates on decap selection (either type or quantity for a specific device instance or all devices to which a PI Cset is applied. Changes to PI Csets also convey information back to the design engineer and enable automated update of the schematic and BOM. Summary While current PCB PI analysis tools are continuing to serve the design community well, they are even more effective when combined with a front-to-back, constraint-based approach. Under this type of methodology, each design team member can more efficiently accomplish his or her individual tasks and communicate design intent information to colleagues for increased efficiency of the overall PCB design flow. This approach provides access to 6How a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results actionable analysis results where they are most impactful. It also leverages earlier defined analysis setup information for the PI expert, and eases communication of design changes from his or her back-end role to front-end colleagues. For Further Information To learn more about Cadence Allegro Sigrity PI solution, visit:/products/sigrity/Pages/ solution.aspx Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design and verify to day’s mobile, cloud and connectivity applications. © 2014 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks and OptimizePI, PowerDC, PowerSI, Sigrity, and Speed2000 are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 1932 01/14 CY/DM/PDF。
allegro SI 信号完整性仿真介绍
基于Cadence Allegro SI 16.3的信号完整性仿真信号完整性是指信号在信号线上的质量。
信号具有良好的信号完整性是指当在需要的时候，具有所必需达到的电压电平数值。
差的信号完整性不是由某一因素导致的，而是由板级设计中多种因素共同引起的。
特别是在高速电路中，所使用的芯片的切换速度过快、端接元件布设不合理、电路的互联不合理等都会引起信号的完整性问题。
具体主要包括串扰、反射、过冲与下冲、振荡、信号延迟等。
信号完整性问题由多种因素引起，归结起来有反射、串扰、过冲和下冲、振铃、信号延迟等，其中反射和串扰是引发信号完整性问题的两大主要因素。
反射和我们所熟悉的光经过不连续的介质时都会有部分能量反射回来一样，就是信号在传输线上的回波现象。
此时信号功率没有全部传输到负载处，有一部分被反射回来了。
在高速的PCB中导线必须等效为传输线，按照传输线理论，如果源端与负载端具有相同的阻抗，反射就不会发生了。
如果二者阻抗不匹配就会引起反射，负载会将一部分电压反射回源端。
根据负载阻抗和源阻抗的关系大小不同，反射电压可能为正，也可能为负。
如果反射信号很强，叠加在原信号上，很可能改变逻辑状态，导致接收数据错误。
如果在时钟信号上可能引起时钟沿不单调，进而引起误触发。
一般布线的几何形状、不正确的线端接、经过连接器的传输及电源平面的不连续等因素均会导致此类反射。
另外常有一个输出多个接收，这时不同的布线策略产生的反射对每个接收端的影响也不相同，所以布线策略也是影响反射的一个不可忽视的因素。
串扰是相邻两条信号线之间的不必要的耦合，信号线之间的互感和互容引起线上的噪声。
因此也就把它分为感性串扰和容性串扰，分别引发耦合电流和耦合电压。
当信号的边沿速率低于1ns时，串扰问题就应该考虑了。
如果信号线上有交变的信号电流通过时，会产生交变的磁场，处于磁场中的相邻的信号线会感应出信号电压。
一般PCB板层的参数、信号线间距、驱动端和接收端的电气特性及信号线的端接方式对串扰都有一定的影响。
用Cadence进行信号完整性
用Cad ence进行信号完整性(SI)仿真流程第一章在Allegro 中准备好进行SI 仿真的PCB 板图1）在Cadence 中进行SI 分析可以通过几种方式得到结果：Allegro 的PCB 画板界面，通过处理可以直接得到结果，或者直接以*.brd 存盘。
使用SpecctreQuest 打开*.brd，进行必要设置，通过处理直接得到结果。
这实际与上述方式类似，只不过是两个独立的模块，真正的仿真软件是下面的SigXplore 程序。
直接打开SigXplore 建立拓扑进行仿真。
2）从PowerPCB 转换到Allegro 格式在PowerPCb 中对已经完成的PCB 板，作如下操作：在文件菜单，选择Export 操作，出现File Export 窗口，选择ASCII 格式*.asc 文件格式，并指定文件名称和路径（图1.1）。
图1.1 在PowerPCB 中输出通用ASC 格式文件图1.2 PowerPCB 导出格式设置窗口点击图1.1 的保存按钮后出现图1.2 ASCII 输出定制窗口，在该窗口中，点击“Select All”项、在Expand Attributes 中选中Parts 和Nets 两项，尤其注意在Format 窗口只能选择PowerPCB V3.0 以下版本格式，否则Allegro 不能正确导入。
3）在Allegro 中导入*.ascPCB 板图在文件菜单，选择Import 操作，出现一个下拉菜单，在下拉菜单中选择PADS 项，出现PADS IN 设置窗口（图1.3），在该窗口中需要设置3 个必要参数：图1.3 转换阿三次文件参数设置窗口i. 在的一栏那填入源asc 文件的目录ii. 在第二栏指定转换必须的pads_in.ini 文件所在目录（也可将此文件拷入工作目录中，此例）iii. 指定转换后的文件存放目录然后运行“Run”，将在指定的目录中生成转换成功的.brd 文件。
CADENCE仿真流程
CADENCE仿真流程1.设计准备在进行仿真之前，需要准备好设计的原理图和布局图。
原理图是电路的逻辑结构图，布局图是电路的物理结构图。
此外，还需要准备好电路的模型、方程和参数等。
2.确定仿真类型根据设计需求，确定仿真类型，包括DC仿真、AC仿真、时域仿真和优化仿真等。
DC仿真用于分析直流电路参数，AC仿真用于分析交流电路参数，而时域仿真则用于分析电路的时间响应。
3.设置仿真参数根据仿真类型，设置仿真参数。
例如，在DC仿真中，需要设置电压和电流源的数值；在AC仿真中，需要设置信号源的频率和幅度；在时域仿真中，需要设置仿真的时间步长和仿真时间等。
4.模型库选择根据设计需求，选择合适的元件模型进行仿真。
CADENCE提供了大量的元件模型，如晶体管、二极管、电感、电容等。
5.确定分析类型根据仿真目标，确定分析类型，例如传输功能分析、噪声分析、频率响应分析等。
6.仿真运行在仿真运行之前，需要对电路进行布局和连线。
使用CADENCE提供的工具对电路进行布局和连线，并生成物理设计。
7.仿真结果分析仿真运行后，CADENCE会生成仿真结果。
利用CADENCE提供的分析工具对仿真结果进行分析，观察电路的性能指标。
8.优化和修改根据仿真结果，对电路进行优化和修改。
根据需要，可以调整电路的拓扑结构、参数和模型等，以改进电路的性能。
9.再次仿真和验证根据修改后的电路，再次进行仿真和验证，以确认电路的性能指标是否得到改善。
最后需要注意的是，CADENCE仿真流程并不是一成不变的，根据具体的设计需求和仿真目标，流程可能会有所调整和修改。
此外，CADENCE还提供了许多其他的工具和功能，如电路板设计、封装设计、时序分析等，可以根据需要进行使用。
Cadence SI信号完整性仿真技术
Cadence PCB SI仿真流程——孙海峰高速高密度多层PCB板的SI/EMC(信号完整性/电磁兼容)问题长久以来一直是设计者所面对的最大挑战。
然而，随着主流的MCU、DSP和处理器大多工作在100MHz以上(有些甚至工作于GHz级以上)，以及越来越多的高速I/O埠和RF前端也都工作在GHz级以上，再加上应用系统的小型化趋势导致的PCB 空间缩小问题，使得目前的高速高密度PCB板设计已经变得越来越普遍。
许多产业分析师指出，在进入21世纪以后，80%以上的多层PCB设计都将会针对高速电路。
高速讯号会导致PCB板上的长互连走线产生传输线效应，它使得PCB设计者必须考虑传输线的延迟和阻抗搭配问题，因为接收端和驱动端的阻抗不搭配都会在传输在线产生反射讯号，而严重影响到讯号的完整性。
另一方面，高密度PCB板上的高速讯号或频率走线则会对间距越来越小的相邻走线产生很难准确量化的串扰与EMC问题。
SI和EMC的问题将会导致PCB设计过程的反复，而使得产品的开发周期一再延误。
一般来说，高速高密度PCB需要复杂的阻抗受控布线策略才能确保电路正常工作。
随着新型组件的电压越来越低、PCB板密度越来越大、边缘转换速率越来越快，以及开发周期越来越短，SI/EMC挑战便日趋严峻。
为了达到这个挑战的要求，目前的PCB设计者必须采用新的方法来确保其PCB设计的可行性与可制造性。
过去的传统设计规则已经无法满足今日的时序和讯号完整性要求，而必须采取包含仿真功能的新款工具才足以确保设计成功。
Cadence的Allegro PCB SI提供了一种弹性化且整合的信号完整性问题解决方案，它是一种完整的SI/PI(功率完整性)/EMI问题的协同解决方案，适用于高速PCB设计周期的每个阶段，并解决与电气性能相关的问题。
Allegro PCB SI信号完整性分析的操作步骤，就是接下来将要介绍的。
一、Allegro PCB SI分析前准备：1、准备需要分析的PCB，如下图；2、SI分析前的相关设置，执行T ools/Setup Advisor,进入Database Setup Advisor 对话框，进行SI分析前的设置；（1）设置PCB叠层的材料、阻抗等，点击Edit Cross section，进入叠层阻抗等设置界面。
CADENCE仿真步骤
CADENCE仿真步骤
Cadence是一款电路仿真软件，它可以帮助设计师创建、分析和仿真
电子电路。
本文将介绍Cadence仿真的步骤。
1.准备仿真结构：第一步是准备仿真结构。
我们需要编写表示电路的Verilog或VHDL代码，然后将它们编译到Cadence Integrated Circuit (IC) Design软件中。
这会生成许多文件，包括netlist和verilog等文件，这些文件将用于仿真。
2.定义仿真输入输出信号：接下来，我们需要定义仿真的输入信号和
输出信号。
输入信号可以是电压、电流、时间和其他可测量的变量。
我们
需要定义输入信号的模拟和数字值，以及输出信号的模拟和数字值。
3.定义参数：参数是仿真中用于定义仿真设计的变量，这些变量可以
是仿真中电路的物理参数，如电阻、电容、时延、输入电压等，也可以是
算法参数，如积分步长等。
4.运行仿真：在所有参数和信号都设置完成后，我们可以运行仿真。
在运行仿真之前，可以使用自动参数检查来检查参数是否正确。
然后，使
用“开始仿真”命令即可启动仿真进程。
5.结果分析：在仿真结束后，我们可以使用结果分析器来查看输出信
号的模拟和数字值，以及仿真中电路的其他特性，如暂态分析、稳态分析、功率分析等。
以上就是Cadence仿真步骤。
基于Cadence软件高速PCB设计的信号完整性仿真
基于Cadence软件高速PCB设计的信号完整性仿真
邓素辉;谭子诚;鄢秋荣;刘明萍;周辉林
【期刊名称】《实验室研究与探索》
【年(卷),期】2017(036)012
【摘要】基于Cadence软件的PCB SI工具,对高速PCB信号完整性常见问题中的反射和串扰进行了仿真分析.演示了具体的仿真步骤,给出了仿真波形.仿真结果表明,使用不同的端接匹配方式实现了信号反射问题的改善,使用改变线间距的方法减少了信号串扰.直观的展示了PCB仿真设计能够改善信号完整性问题,可用于EDA 设计的本科教学实验演示.
【总页数】5页(P116-120)
【作者】邓素辉;谭子诚;鄢秋荣;刘明萍;周辉林
【作者单位】南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031
【正文语种】中文
【中图分类】TN41
【相关文献】
1.基于信号完整性的高速PCB设计方法 [J], 王婷
2.高速PCB设计中信号完整性的仿真与分析 [J], 肖汉波
3.基于信号完整性的高速数据采集存储器PCB设计与仿真 [J], 王乐;裴东兴;崔春
生
4.基于Cadence_Allegro的高速PCB设计信号完整性分析与仿真 [J], 覃婕;阎波;林水生
5.基于信号完整性分析的高速PCB设计 [J], 梁龙
因版权原因，仅展示原文概要，查看原文内容请购买。
基于Cadence软件高速PCB设计的信号完整性仿真
基于Cadence软件高速PCB设计的信号完整性仿真邓素辉;谭子诚;鄢秋荣;刘明萍;周辉林【摘要】The common signal integrity (SI) problems of signal reflection and crosstalk in high-speed PCB were studied by using the analysis tool of PCB SI in the Cadence software.The simulation steps were given in detail and the waveforms of the simulation were shown.The results show that several methods of termination matching can be applied to solve the reflection problems.Adjusting the line spacing can effectively reduce the signal crosstalk phenomenon.The improvements of signal integrity in PCB were displayed obviously,the method is very helpful in undergraduates' teaching of the EDA design.%基于Cadence软件的PCB SI工具,对高速PCB信号完整性常见问题中的反射和串扰进行了仿真分析.演示了具体的仿真步骤,给出了仿真波形.仿真结果表明,使用不同的端接匹配方式实现了信号反射问题的改善,使用改变线间距的方法减少了信号串扰.直观的展示了PCB仿真设计能够改善信号完整性问题,可用于EDA设计的本科教学实验演示.【期刊名称】《实验室研究与探索》【年(卷),期】2017(036)012【总页数】5页(P116-120)【关键词】高速PCB;信号完整性;反射;串扰【作者】邓素辉;谭子诚;鄢秋荣;刘明萍;周辉林【作者单位】南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031【正文语种】中文【中图分类】TN410 引言随着电子产品朝着高速率、高密度、小体积的方向发展，电子系统设计领域已经进入GHz及以上的设计领域。
Cadence-SI-Simulation
Cadence仿真介绍第一部分：仿真流程第二部分：IBIS模型IBIS模型和SPICE模型比较：SPICE模型：（1）电压/电流/时间等关系从器件图形、材料特性得来，建立在低级数据的基础上（2）每个buffer中的器件分别描述/仿真（3）仿真速度很慢（4）包含芯片制造工艺信息IBIS模型：（1）电压/电流/时间关系建立在IV/VT数据曲线上（2）没有包括电路细节（3）仿真速度快，是SPICE模型的25倍以上（4）不包含芯片内部制造工艺信息基于上述原因，对于在系统级的设计，我们更倾向于使用IBIS模型。
目前IBIS主要使用的有V1.1，V2.1，V3.2及V4.0等版本。
模型结构如下图：C_pkg，R_pkg，L_pkg为封装参数；C_comp为晶片pad电容；Power_Clamp，GND_Clamp 为ESD结构的V/I曲线。
输出模型比输入模型多一个pull-up，pull-down的V/T曲线。
Cadence的model integrity工具负责对IBIS模型进行语法检查、编辑以及进行DML格式转换。
Cadence仿真不直接使用IBIS模型，而必须先把IBIS转换成DML。
<实例操作演示>第三部分：电路板设置电路板设置包括：（1）叠层设置；（2）DC电压设置；（3）器件设置；（4）模型分配；上述步骤可以通过setup advisor向导设置。
1，叠层设置2，DC电压设置3，器件设置4，模型分配电阻、电容、电感等无源器件的模型可以通过建立ESPICE模型来获得。
<实例操作演示>第四部分：设置仿真参数模型分配完成后，就可以进行仿真了。
在进行仿真之前，需要对仿真的参数进行设置。
Pulse cycle count：通过指定系统传输的脉冲数目来确定仿真的持续时间。
Pulse Clock Frequency：确定仿真中用来激励驱动器的脉冲电压源的频率。
Pulse Duty cycle：脉冲占空比。
cadence仿真步骤
CDNLive! Paper – Signal Integrity (SI) for Dual Data Rate (DDR) InterfacePrithi Ramakrishnan iDEN Subscriber Group Plantation, FlPresented atIntroductionThe need for Signal Integrity (SI) analysis for printed circuit board (PCB) design has become essential to ensure first time success of high-speed, high-density digital designs. This paper will cover the usage of Cadence’s Allegro PCB SI tool for the design of a dual data rate (DDR) memory interface in one of Motorola’s products. Specifically, this paper will describe the following key phases of the high-speed design process: Design set-up Pre-route SI analysis Constraint-driven routing Post-route SI analysisDDR interfaces, being source synchronous in nature, feature skew as the fundamental parameter to manage in order to meet setup and hold timing margins. A brief overview of source synchronous signaling and its challenges is also presented to provide context.Project BackgroundThis paper is based on the design of a DDR interface in an iDEN Subscriber Group phone that uses the mobile Linux Java platform. The phone is currently in the final stages of system and factory testing, and is due to be released in the market at the end of August 2007 for Nextel international customers. The phone has a dual-core custom processor with an application processor (ARM 11) and a baseband processor (StarCore) running at 400MHz and 208MHz respectively. The processor has a NAND and DDR controller, both supporting 16-bit interfaces. The memory device used is a multi-chip package (MCP) with stacked NAND (512Mb) and DDR (512Mb) parts. The NAND device is run at 22MHz and the DDR at 133MHz. The interface had to be supported over several memory vendors, and consequently had to account for the difference in timing margins, input capacitances, and buffer drive strengths between different dies and packages. As customer preference for smaller and thinner phones grows, the design and placement of critical components and modules has become more challenging. In addition to incorporating various sections such as Radio Frequency (RF), Power Management, DC, Audio, Digital ICs, and sub-circuits of these modules, design engineers must simultaneously satisfy the rigid placement requirements for components such as speakers, antennas, displays, and cameras. As such, there are very few options and little flexibility in terms of placement of the components. This problem was further accentuated by the fact that several layers of the 10 layer board (3-4-3 structure with one ground plane and no power planes) were reserved for power, audio, and other high frequency (RF) nets, leaving engineers with few layers to choose from for digital circuitry.Figure 1. Memory Interface routes With the DDR interface data switching at 266MHz, we had very tight margins — 600ps for data/DQS lines, 280ps for the address lines, and 180ps for control lines. However, with the NAND interface we had larger margins that were on the order of a few tens of nanoseconds. In these situations, choosing a higher drive strength and using terminators of appropriate values (to meet rise times and avoid overshoot/undershoot) has become a common practice in DDR designs. However, due to the lack of space on the board, we were not in a position to use terminators. Therefore, we used programmable buffers on our processor, and with the help of Cadence SI tools were able to fine-tune the design. Our group migrated from using Mentor Graphics to Cadence SI during this project. As one might expect, this made the task of designing a high speed DDR interface even more challenging. To help overcome this, we worked extensively with Cadence Services, where Ken Willis supported us on the SI portion of the design.The Source Synchronous Design ChallengeBefore discussing the specifics of the Motorola DDR interface, a brief overview of source synchronous signaling is provided here for context. Historically, digital interfaces have utilized “common clock” signaling, as shown in the figure below.Clock DriverTcoInterconnect Delay D0 D1 D2 D0 D1 D2DriveReceiveFigure 2. Common clock designWith common clock interfaces, the clock signal is provided to the driving and receiving components from an external component. The magnitude of the driver’s Tco (time from clock to output valid) and the interconnect delay between the driving and receiving components becomes a limiting factor in the timing of the interface. From a practical standpoint, it becomes increasingly challenging to implement interfaces of this type above several hundred megahertz. In order to accommodate requirements for faster data rates, source synchronous signaling emerged as the new paradigm. This is illustrated in the figure below.StrobeD 0 D 1D 0 D 1DriveReceiveFigure 3. Source synchronous design.In a source synchronous interface, the “clock” is provided locally by the driving component, and is generally called a “strobe” signal. The relationship between the strobe and its associated data bits is known as it leaves the driving component, with setup and hold margins pre-established as the signals are put onto the bus.TsetupTholdFigure 4. Timing diagram. This essentially takes the driver’s Tco as well as the magnitude of the interconnect delay between the driving and receiving chip out of the timing equation altogether. The timing challenge then becomes to manage the skew between the data and strobe signals such that the setup and hold requirements at the receiving end are still met.Technical ApproachThe general technical approach used in this project can be broken down into the following key phases of the high-speed design process: Design set-up Pre-route SI analysis Constraint-driven routing Post-route SI analysisFirst the PCB design database is set up to enable analysis with Allegro PCB SI. Before routing is performed, initial trade-offs are examined at the placement stage, and constraints are captured to facilitate constraint-driven routing. When routing is completed, detailed analysis is performed, interconnect delays extracted, and setup/hold margins are computed. Any adjustments required are fed back to the layout designer, and the postroute analysis is repeated. This basic process is diagrammed below.Design Setup SI Models Pre-Route AnalysisStartConstraints RoutingPost-Route AnalysisnoMargins OK?yes EndFigure 5. SI design process flow. Detail on the major design phases are provided in the subsequent sections. Design Setup By virtue of its direct integration with the Allegro PCB layout database, Allegro SI analysis requires that the design be set up to facilitate the automated extraction, circuit building, netlisting, simulation, and analysis that it performs. This essentially means adding the needed intelligence to the physical Allegro database that allows the tool to do its job. This setup involves the following: Cross section DC nets Device definitions SI models By definition, SI analysis involves the modeling of interconnect parasitics. In order to do this accurately, the tool needs to know the properties and characteristics of the materials used in the PCB stack-up. This information is defined in the Cross Section form, as shown below.It is crucial to get this data correct, as it will be fed to the 2D field solver to model interconnect parasitics during the extraction process. The best source for this detailed information is generally from the PCB fabricator. Layer thickness, dielectric constant, and loss tangent are all critical parameters for the cross section definition. In order for circuit extraction to be done properly, the tool needs to know about DC nets in the design, and what their associated voltage levels are. This accomplishes two main things in the setup; a) enables voltage sources to be injected properly in the extracted circuits, and b) avoids having the tool needlessly trying to extract extremely large DC nets, and hanging up the analysis process. Take the example of a parallel resistor termination. Allegro SI will encounter the resistor as it walks the signal net to be extracted. The tool will look up the SI model assigned to this resistor, splice in the resistor subcircuit, and continue extracting whatever is on the other side of the resistor. If this is a large DC net (ex. VTT), the desire is for the tool to put a voltage source at the 2nd resistor pin, complete the circuit, and simulate the signal. To do this properly, the tool relies on a VOLTAGE property to exist on the DC net, with a numeric value defined. In the absence of the VOLTAGE property, the tool will simply continue to extract, which in the case of a 2000 pin ground net, would be a large waste of computational time. To identify DC nets, clicking “Logic > Identify DC Nets” will spawn the following form.All DC nets in the design should be identified, to fully optimize SI analysis. These can be identified up front in the schematic, as well as in the physical layout as shown here. The next step in the design set-up process is to verify that the logical “CLASS” and “PINUSE” attributes for the devices in the design are defined appropriately. These attributes originate from the schematic symbol libraries and are passed into the Allegro physical layout environment. In an ideal methodology, these libraries would be defined properly and would require no edits. However, this is not always the case, and as these attributes have a bearing on the behavior of the SI analysis, it is worth mention here. The “CLASS” attribute is used to distinguish between different types of components in the PCB design. Legal values of “CLASS” are listed below: IC – This is used for digital integrated circuits, which contain drivers and/or receivers. These types of components are modeled with an SI model of the type “IbisDevice”. When the automated circuit building algorithms in Allegro PCB SI encounter a model of this type, it looks up the buffer model (driver, receiver, or bidirectional) assigned to the pin in question, and inserts it into the circuit along with its associated package parasitics. IO – A component with CLASS = IO is intended for components that connect off-card to other physical layout designs, such as connectors. These components can be associated with a “DesignLink”, which provides netlisting to other physical designs and enables multi-board SI analysis. So circuit building algorithms expect to jump from a device of CLASS=IO to a similar device on a different physical layout. DISCRETE – For devices of this class, circuit building algorithms expect to traverse “through” the component, from one pin to another, inserting a subcircuit in-between. A good example of this would be a series resistor.If CLASS attributes are not set up properly in the source schematic libraries, they can be edited in the physical layout database for analysis by using the form shown below, launched from the “Logic > Parts List” menu pick.The “PINUSE” attribute also impacts the behavior of the SI analysis, as the tool uses this information to determine if a pin is a driver, receiver, bidirectional, or passive pin. As with the “CLASS” attribute, in an ideal methodology this is defined properly in the schematic libraries, and no editing is required in physical layout. “PINUSE” can be modified in two main ways for SI purposes. The most straightforward way is to ensure that the IOCell models used in the IbisDevice models assigned to components have the appropriate Model Type for the signals they are associated to. When SI models are assigned to components, the tool will check for conflicts between the model and the PINUSE it finds for the component in the design, and will use the SI model to automatically override the PINUSE found in the drawing. So if the correct pin types are found in the SI models, the layout will automatically inherit those settings. For components not explicitly modeled, their PINUSE can be set using the form shown below, launched from the “Logic > Pin Type” menu pick.Signal Integrity (SI) models can be assigned using the “Signal Model Assignment” form, shown below.Upon clicking “OK” the selected models will be assigned to the components and saved directly in the layout database. As mentioned previously, “PINUSE” attributes will be synced up, with the SI models superseding attributes in the original layout drawing.Pre-Route SI AnalysisPerforming pre-route analysis is a key part of the high-speed design process. Once critical component placement has been done, Manhattan distances can be used to estimate trace lengths, and can provide a realistic picture of how routed interconnect will potentially perform.Before simulations are run for critical signals, the timing of the interface must be well understood. To accomplish this, we will first sketch timing diagrams for each signal group and then extract a representative signal for analysis. Next, we will explore Z0, layer assignments, drive strength, route lengths, spacing, and terminations for these nets.To sketch the timing diagrams, we first analyze the memory interface. The memory interface consists of both DDR and NAND signals and has around seventy nets. To simplify the analysis of the interface, we first divide these nets based on function and then simulate one net from each group. Accordingly, we select one signal from each of the following groups —clock_ddr, strobe_ddr , data_ddr, control_ddr, address_ddr, control_nand, and data_nand — for our pre-route simulations.To understand the timing relations in the interface, we should look at the following operations between the memory device and the processor — read, write, address write, and control operations. Next, we identify the nets involved and the clocking reference signal for each of these operations. We then calculate the worst case slack available from the setup and hold numbers available in the data sheets. In particular, we adopted the worst case numbers across four different memory vendors, to ensure robustness of the manfactured system in the field..1.ReadDuring the read operation, the memory drives the data and DQS lines. The processor has a delay line (a series of buffers which can be tapped at different points), which is used to delay the DQS signal so that it samples the data at quarter of the cycle. The processor also offers programming options that allow us to apply an offset to the quarter cycle, enabling us to meet our setup and hold times. Hence, the processor self-corrects forstrobe/data skew using this delay line. The granularity of this delay line is 30 ps; that is, each of the buffers of the delay line contributes 30 ps of delay. The data lines 0-7 are clocked with respect to the DQS0 strobe signal, and the data lines 8-15 are clocked with respect to DQS1. Data and strobe lines should be clustered, with the matching constraints determined by the write cycle.2.WriteFigure 7. Write operation at memory interface.During the write operation, both data and DQS are driven by the processor. Data is latched at both the positive and the negative edges of the DQS signals. Here again, data bits 0-7 are clocked by DQS0 and data bits 8-15 are clocked by DQS1. The setup and hold times available as these signals come out of the DDR controller are 1.58ns and 1.7ns respectively and the corresponding times required at the memory to ensure correct operation is 0.9ns. Hence, the slack available for routing is the lesser of 1.58ns – 0.9ns or 1.7ns – 0.9ns, which comes out to be 0.68ns. This amounts to an allowable ~85mm mismatch between the data lines. In addition, we need to make sure that length of the DQS lines is around the average of all the data lines. The data mask signals DQM0 and DQM1 also come into play during the write operation and we should group them along with the respective data lines.3.Address busFigure 8. Address bus operation at memory interface.Both address and clock lines are driven by the processor. The address bits 0-12 are clocked by the differential clock and latched at the positive edge of the clock. The setup and hold times available for these signals from the DDR controller are 1.78ns and 4.22ns respectively and the corresponding times required at the memory to ensure correct operation is 1.5ns for both. Hence the worst case slack for routing is 0.28ns and we have to try to match our signals to meet these numbers. The 0.28ns slack amounts to ~14mm mismatch between the address lines and the clock.4.Control linesFigure 9. Control lines at memory interface.The control signals are clocked by the differential clock and latched at the positive edge of the clock. The setup and hold times coming out of the DDR controller are 1.64ns and 4.04ns respectively. The setup and hold times required at the memory to ensure correct operation is 1.5ns. Hence, the worst case slack for routing is 0.14ns and we have to try and match our signals to meet these numbers. The 0.14 ns slack amounts to ~7mm mismatch between the control lines and the clock.In addition, CLK to DQS skew is around 600 ps. With regards to the NAND lines, setup and hold numbers are in the order of tens of ns and hence routing them as short as possible based on their Manhattan lengths would suffice.To complete pre-route analysis, SigXplorer must be setup for these tasks:a. Extract a topology file for single net analysis. To bring up the net in SigXplorer, it is essential that the models are assigned, as described in Section 2, to each of the drivers, receivers, and components in the signal path.b. Set up parameters for extraction and simulate using SigXplorer.c. Perform measurements using SigWaveThe following screenshots of SigXplorer show this process in detail.Figure 10. SigXplorer screenshots.Since at this point none of the nets in the design are routed we need to set the percent Manhattan section for unrouted interconnect models. We should then select the net, as shown in the next screenshot, for analysis.Analyze Æ SI/EMI Sim Æ PreferencesThe speed at which the signal travels in the trace, where C is 3 x 108 m/s and E reff is the effective dielectric constant seen in the interconnectSets the default lengthfor unrouted transmission linesAt this point, it is important to check if your driver and receiver pins are set correctly. The net chosen in the above example is a data net, it is bi-directional, hence it can be driven both by the memory device as well as the processor. The view topology icon can be clicked to export this net in SigXplorer.The tool extracts the net along with drivers, receivers and strip lines on various layers of the board. Before you start the simulation, you must set the stimulus frequency, pulse step offset, and cycle count. This can be set in the following GUI.Analyze Æ PreferencesBoth the memory device and the processor have programmable drive strengths. The buffer model can bechanged to pick up the various drive strengths that are available in the dml models of the devices till we observe satisfactory waveforms in SigWave.Analyze Æ SI/EMI Sim Æprobeinvokes SigXplorerMake sure you check you driver and load pinsSigXplorer allows you to sweep any of the parameters such as the thickness, length, drive strengths and displays corresponding settle/switch delays, monotonicity, and glitch tolerance for the corresponding simulation. It also allows adding components such as resistors and capacitors and let’s us sweep their values. We added a resistor in series with our clock in or to get rid of ringing in the rising edge. The tool let us determine what values were suitable for this resistor. As shown in the next figure the waveform corresponding to our simulation can bebrought up on SigWave.driverreceiverYou can observe the rise/fall times, look for noise margins, overshoot/undershoot of the receiver waveform. The constraints we develop in the pre-route simulation will be used by the routing tool to ensure correct first time results. This leads to our next section; Constraint-driven routing.Constraint-driven routingOnce pre-route analysis has been done, and trade-offs have been examined, signal wiring constraints need to be developed to drive the constraint-driven routing process. With the DDR interface being point-to-point between the processor and memory, we translated our timing requirements into length constraints to make the routing as straightforward as possible. We also assigned layer constraints for our DDR signals. Both the length and the layer constraints can be directly applied to the constraint manager before the routing process starts.For our particular design, we determined the following layer assignments from the results of the pre-route simulations, taking into account the layer’s characteristic impedance per our stack-up:Layer 6 Æ ground planeLayer 7 Æ clock, add, ctrlLayer 8 Æ data, strobeLayer 9 Æ NAND interfaceBefore we set up our design for auto-routing, we routed the differential clock lines manually on the layers closest to the ground plane. For the rest of the nets, the layer constraints can be created as shown in the following snapshots of the constraint manager.Electrical Constraint Set Æ WiringRight click on board Æ Create new constraintName the constraint (ex. ECSET1)We choose one layer with horizontal orientation and one with vertical for each of our layer sets. You can form groups from the available layer sets and create a new constraint. This constraint, which we define as ECSET1, can be easily read back in the constraint manager and applied to the relevant net group, as shown in the following snapshot.We determined from pre-route analysis the slack available for each of our net groups; however, before we translate these into length constraints it is important to get a report of the Manhattan lengths of each of these signals. To illustrate this, we will focus on the address signals. The Manhattan report of the address lines showed that the shortest lines were 6mm and the longest were 17mm. Accordingly, the minimum length constraint must be longer than 6mm and the maximum length constraint must be longer than 17mm. Additionally, from our timing diagrams, we determined that the maximum spread can be no more than 14mm. Following these restrictions, we set the minimum and maximum length limits for the address line are 11.99 mmto 18.99 mm (shown in the constraint editor window below). Based on the layout designer's recommendations, we were able to constrain a bit tighter (7mm margin) and produce better margins.To enter the length constraint, we open the Net Æ Routing ÆTotal etch length section of the constrain manager. We followed this procedure for all the other net groups. The snapshot that follows shows length constraints associated with the address lines. Here, the key is to not to over-constrain your design, but at the same time have enough constraints so the timing and signal integrity parameters are met. Over-constraining the design severely inhibits the auto-router and may leave large portions of the design (as much as 90%) un-routed.Post-Route SI AnalysisOnce the design is fully routed, detailed simulations can be run for post-route verification. The goal at this phase is to determine final margins over all corners, and find and correct any SI or timing-related issues before the board is released for fabrication. Before starting simulation, it is important to verify that the design is properly routed and that it meets the specifications/constraints. In particular, it is essential to verify that the design does not include dangling and partially-routed/un-routed nets. We must also verify that all the nets meet the length constraints assigned to them. The Constraint Manager window helps identify nets that are in violation (shown in red) and nets that are in compliance (in green). For convenience and clarity, the Constraint Manager also reports the actual route length and the Manhattan lengths for each net.The next step is to bring up the physical layout and visually inspect the nets to ensure that each net is routed in its appropriate layer, or run DRCs if the signals were explicitly limited to specific layers in Physical Constraint Sets. When test points are associated with a net, we must manually verify that the points are in line with the nets (and are not stubs hanging off the nets). Note that when using the simpler Total_Etch_Length constraint, the auto-router can meet routing length constraints for the net, even when there are stubs in the design. These stubs can produce undesirable effects such as reflections and hence this step is important. If there are too manycritical signals to check manually on larger designs, this check can be automated by using an explicit topology and stub length constraints. After manual inspection, we begin post–route simulation and generate reports to analyze the design. We then export the reports to an Excel spreadsheet to facilitate analysis.We generated both delay and reflection reports. The delay report provides information on timing parameters such as propagation delay, switch and settle rise and fall times. The reflection report presents data on signal integrity parameters such as overshoot, undershoot, noise margin, monotonicity, and glitch. Preparing the design for post-route simulation involves the selection of various options in the SI\EMI Sim preferences list. The following screen display describes this process.In the form above, we set up the frequency of the stimulus and the duty cycle. We also set up V meas as thereference for delay calculations. Choosing the reference as V meas , rather than V IH and V IL , makes analysis much easier and is in accordance with the memory datasheet. We chose V meas as 0.9V which is half of the peak-to-peak voltage swing (1.8V).Now that the design is routed, we need to set the parameters for routed interconnects. Here you can specify the minimum coupling distance for nets for the tool to recognize it as a differential pair. This can be done by invoking Analyze Æ SI ÆPref ÆInterconnect Models.Analyze Æ SI/EMI Sim Æ preferencesThe preceding screenshot shows the option that allows us to select the delay and reflection reports. In this form, we also choose all three simulation modes — fast, typical, and slow — to cover all corner cases. In our experience, running typical mode simulations were not enough to determine final timing margins over process, voltage, and temperature. So, we exported the reports to an Excel spread sheet and analyzed the results. Reflection and delay reports simulate only a primary net and none of its neighbors. As a result, these reports do not take into consideration the parasitics of the power and ground pins.Timing > Control typNote:All timings in ns unless labelled otherwise.Component Timingdriving to MemoryTsetup 1.64Tsetup 1.5Thold 4.04Thold 1.5Skew_max = 1.64 - 1.5 = 140ps between clock and controlSkew_max=0.14Clock/Strobe RelationshipsSdram_Ctrl<6:7> is differential clockInterconnect TimingXNet Drvr Rcvr PropDly SettleRise SettleFall AvgSettleSDRAM_CTRL<6>U800 V2_UU2164 C7_U2160.142029 1.13851 1.20538 1.172XNet Drvr Rcvr PropDly SettleRise SettleFall MinSettle MaxSettle MinSettleSkew MaxSettleSkew MaxSkew MarginSDRAM_CTRL<0>U800U21640.1118 1.191 1.235 1.104 1.2350.0680.0630.0680.072SDRAM_CTRL<10>U800U21640.1254 1.165 1.207SDRAM_CTRL<11>U800U21640.1114 1.141 1.187SDRAM_CTRL<12>U800U21640.1217 1.178 1.221SDRAM_CTRL<13>U800U21640.1067 1.114 1.153SDRAM_CTRL<14>U800U21640.09823 1.104 1.143SDRAM_CTRL<2>U800U21640.1274 1.163 1.205SDRAM_CTRL<3>U800U21640.09163 1.108 1.153SDRAM_CTRL<8>U800U21640.1081 1.137 1.182SDRAM_CTRL<4>U800U21640.06959 1.143 1.247SDRAM_CTRL<5>U800U21640.0862 1.169 1.285The preceding spreadsheet was created with data from delay reports and was used to analyze the control lines with respect to the clock. The clock signal in our design is called SDRAM_CTRL<6>. The sheet also lists the driver (U800, the processor), receiver (U2164, memory device), propagation delay (0.142029 ns), settle rise (1.13851 ns), and settle fall (1.20538 ns) values. The average settle delay (1.172 ns) is calculated by averaging the settle rise and settle fall numbers.The control nets SDRAM<0> to SDRAM_CTRL <14> are listed next to the corresponding drivers, receivers, propagation delays, settle rise and settle fall delays. We then look for the minimum and maximum delays of all the settle rise and settle fall delays. These are listed under maximum settle delay (1.235 ns) and minimum settle delay (1.104 ns) respectively. Using these numbers, we calculate the maximum settle skew (0.063 ns), which is the difference between the maximum settle delay (1.235ns) and the average settle time (1.172 ns) of the clock signal. We also calculate the minimum settle skew (0.063 ns), which is the difference between the minimum settle delay (1.104ns) and the average settle time (1.172 ns) of the clock signal. Subtracting the maximum of these two skews, which in our case is 0.068 ns, from the total skew available (0.140 ns) gives the margin (0.072 ns) for these nets.。
基于Cadence的信号完整性仿真步骤
目录1.仿真前的准备工作 (2)1.1找到需要仿真的芯片的IBIS模型 (2)1.2模型转换（IBIS→DML） (2)1.3添加模型到Cadence的模型库中 (5)2. 对电路板进行设置（Setup Advisor） (7)2.1准备好要仿真的电路板 (7)2.2调用参数设置向导 (7)2.3叠层设置 (8)2.4设置DC电压值 (9)2.5器件设置（Device Setup） (10)2.6 SI模型分配 (12)2.7 SI检查（SI Audit） (16)2.8完成参数设置 (18)3.进行信号完整性仿真（反射） (19)3.1开始仿真 (19)3.2选择所要仿真的网络 (19)3.3提取网络的拓扑结构 (20)3.4给驱动端U8添加激励信号 (21)3.5设置激励信号的参数 (22)3.6执行反射仿真 (22)3.7仿真结果 (22)1.仿真前的准备工作1.1找到需要仿真的芯片的IBIS模型一般可以从芯片制造商网站上找到，如果没有，可能要通过其它途径获得如从SPICE模型中提取。
1.2模型转换 （IBIS→DML）将IBIS模型转换为DML模型，运用Cadence的Model Integrity工具将IBIS模型转化为Cadence能识别的DML模型，并验证仿真模型。
（1）单击“开始”按钮→“所有程序”→“Allegro SPB 15.5”→“Model Integrity”，如图1-1所示：图1-1 Model Integrity工具窗口（2）选择“File”→“Open”，打开一个IBIS模型如图1-2所示：图1-2 打开一个IBIS模型（3）在“Physical View”栏中，单击IBIS文件“sn74avca16245”→选择菜单栏里的“Options”→“Translation Options Editor”→弹出“Translation Options”窗口，如图1-3所示：图1-3 Translation Options窗口（4）默认选择“Make model names unique”，这个设置为每个IOCell模型名附加IBIS文件名。
cadence信号完整性分析精要总结
第1章 高速电路基础要点1、 高速电路的定义：数字逻辑电路的频率达到或超过50MHZ ，而且工作在这个频率之上的电路占整个系统的1/3以上，就可以称为高速电路。
2、 高速信号实质：信号传输时间大于数字信号驱动端上升时间的1/2，则可以认为是高速信号并产生传输线效应，实质是，：传输时间小于上身时间的一半时，那么在本次信号状态改变前，接收端的反射信号就已经到达驱动端，不会引起逻辑错误，反之，大于一半时，接收端的反射信号就可能会与下一次驱动端的输出信号进行叠加，若反射信号很强，就可能会影响下一次输出的正常逻辑。
3、 高信号的确定：Tr 表示信号上升时间，Tpd 表示传输延迟，若Tr>4Tpd,信号在安全区域，若2 Tpd<T r≤4 Tpd,信号在不确定区域，若Tr ≤2 Tpd ，信号落在问题区域，设计需保证信号落在安全区域。
4、 传输线：传输线上由两个具有一定长度的导体组成的回路的连接线，有时也称延迟线，传输线上每一点都有不同的电势。
（可以理解为机械波的振动，或电场吸纳促使电子移动导致电位变化模型，需要时间，故不同点电位不一致，不深按纠）5、 传输线的确定：信号传输路径长度大于信号波长的1%，或接收端元器件是边缘敏感，或系统没有过冲和下冲容限，此时虚认为传输路径是传输线。
（实质：边沿时间、波形变化时间、传输时间三者很接近时就必须考虑为传输线）零碎常识：(1)、PCB 上走线等效电阻阻值约为0.25～0.55Ω(2)、空气电信号传播速度85ps/in ，空气介电常数约为1，真空为1.(2)、FR4内层布线180ps/in ，介电常数为4.5；外层：140～180,2.8～4.56、反射系数：Z L 是当次传播负载端等效阻抗，Z O 当次传播输出端等效阻抗。
ρL =OL O L Z Z Z Z + ７、反射电压：反射系数乘ρL 以输入电压Vi 。
即Vf=ρL *Vi注：上表达式是乘以输入电压，即得反射电压，不在需要与1或原始量进行加减运算。
CADENCE仿真步骤
Cadence SPECCTRAQuest 仿真步骤[摘要]本文介绍了Cadence SPECCTRAQuest在高速数字电路的PCB设计中采用的基于信号完整性分析的设计方法的全过程。
从信号完整性仿真前的环境参数的设置，到对所有的高速数字信号赋予PCB板级的信号传输模型，再到通过对信号完整性的计算分析找到设计的解空间，这就是高速数字电路PCB板级设计的基础。
[关键词]板级电路仿真I/O Buffer Information Specification（IBIS）1 引言电路板级仿真对于今天大多数的PCB板级设计而言已不再是一种选择而是必然之路。
在相当长的一段时间，由于PCB仿真软件使用复杂、缺乏必需的仿真模型、PCB仿真软件成本偏高等原因导致仿真在电路板级设计中没有得到普及。
随着集成电路的工作速度不断提高，电路的复杂性不断增加之后，多层板和高密度电路板的出现等等都对PCB板级设计提出了更新更高的要求。
尤其是半导体技术的飞速发展，数字器件复杂度越来越高，门电路的规模达到成千上万甚至上百万，现在一个芯片可以完成过去整个电路板的功能，从而使相同的PCB上可以容纳更多的功能。
PCB已不仅仅是支撑电子元器件的平台，而变成了一个高性能的系统结构。
这样，信号完整性在PCB板级设计中成为了一个必须考虑的一个问题。
传统的PCB板的设计依次经过电路设计、版图设计、PCB制作等工序，而PCB的性能只有通过一系列仪器测试电路板原型来评定。
如果不能满足性能的要求，上述的过程就需要经过多次的重复，尤其是有些问题往往很难将其量化，反复多次就不可避免。
这些在当前激烈的市场竞争面前，无论是设计时间、设计的成本还是设计的复杂程度上都无法满足要求。
在现在的PCB板级设计中采用电路板级仿真已经成为必然。
基于信号完整性的PCB仿真设计就是根据完整的仿真模型通过对信号完整性的计算分析得出设计的解空间，然后在此基础上完成PCB设计，最后对设计进行验证是否满足预计的信号完整性要求。
CADENCE仿真流程
CADENCE仿真流程第一章进行SI仿真的PCB板图的准备仿真前的准备工作主要包括以下几点：1、仿真板的准备●原理图设计；●PCB封装设计；●PCB板外型边框（Outline）设计，PCB板禁止布线区划分（Keepouts）；●输出网表（如果是用CADENCE的Concept HDL设计的原理图，可将网表直接Expot 到BRD文件中；如果是用PowerPCB设计的板图，转换到allegro中的板图，其操作见附录一的说明）；●器件预布局（Placement）：将其中的关键器件进行合理的预布局，主要涉及相对距离、抗干扰、散热、高频电路与低频电路、数字电路与模拟电路等方面；●PCB板布线分区（Rooms）：主要用来区分高频电路与低频电路、数字电路与模拟电路以及相对独立的电路。
元器件的布局以及电源和地线的处理将直接影响到电路性能和电磁兼容性能；2、器件模型的准备●收集器件的IBIS模型（网上下载、向代理申请、修改同类型器件的IBIS模型等）●收集器件的关键参数，如T co、Tsetup、Tholdup等及系统有关的时间参数T clock、Tskew、Tjitter●对IBIS模型进行整理、检查、纠错和验证。
3、确定需要仿真的电路部分，一般包括频率较高，负载较多，拓扑结构比较复杂（点到多点、多点到多点），时钟电路等关键信号线第二章IBIS模型的转化和加载CADENCE中的信号完整性仿真是建立在IBIS模型的基础上的，但又不是直接应用IBIS 模型，CADECE的软件自带一个将IBIS模型转换为自己可用的DML（Device Model Library）模型的功能模块，本章主要就IBIS模型的转换及加载进行讲解。
1、IBIS模型到DML模型的转换在Allegro窗口中选择Analyse\SI/EMI SIM\Library，打开“signal analyze library browser”窗口，在该窗口的右下方点击“Translate →”按钮，在出现的下拉菜单中选择“ibis2signois”项，出现“Select IBIS Source File”窗口（图1），选择想要进行转换的源IBIS文件，按下“打开”按钮，出现转换后文件名及路径设置窗口（缺省设置为和源IBIS文件同名并同路径放置，但此处文件名后缀为dml），设置后按下“保存”按钮，出现保存确定窗口（图2）,点击OK按钮即可，随后会出现一个“messages”窗口，该窗口中的报告文件说明在模型转换过程中出现的问题，对其中的“warning”可不用在意，但如果出现“error”则必须进行修改后重新进行模型格式转化直到没有“error”出现为止，此时转换得到的dml文件才是有效的。
CADENCE仿真步骤
CADENCE仿真步骤1.电路设计：首先，需要使用电路设计软件（例如OrCAD）绘制电路原理图。
在设计电路时，应该合理选择电路元件，确保其参数和规格满足设计要求。
2.创建电路网络：在CADENCE中创建电路网络是第一步。
通过将电路原理图导入到CADENCE中，可以建立电路的模型。
在建立电路网络时，应定义元件的参数值，并将其连接起来。
3.定义仿真设置：在进行仿真之前，需要设置仿真参数。
这些参数包括仿真类型（例如直流、交流、蒙特卡罗等）、仿真步长、仿真时间等。
此外，还可以设置其他参数，如故障分析、参数扫描等。
4. 运行仿真：设置好仿真参数后，可以开始运行仿真了。
CADENCE 提供了多种仿真工具，如PSpice、Spectre等，可以根据不同的需求选择适合的工具。
在仿真过程中，CADENCE会使用电路元件的模型计算电路参数，根据仿真设置提供的信息生成相应的结果。
5.分析仿真结果：一旦仿真完成，CADENCE会生成仿真结果文件。
通过分析仿真结果，可以评估电路设计的性能。
常见的仿真结果包括电流、电压、功耗、频率响应等。
可以将仿真结果与预期结果进行比较，找出设计中的问题并进行优化。
6.优化电路设计：根据仿真结果，可以对电路设计进行调整和优化。
优化可以包括选择不同的元件、调整元件参数、改变电路拓扑等。
通过不断迭代仿真和优化，可以逐步改进电路设计，使其达到预期的性能指标。
7.验证仿真结果：当设计经过一系列的优化后，需要验证仿真结果是否可靠。
一种常用的验证方法是进行物理验证，即将最终的电路设计制作出来并测量其实际性能。
通过比较实际测量结果与仿真结果，可以验证仿真的准确性，并进行必要的修正。
8. 导出设计文件：一旦电路设计完成并验证通过，就可以将设计文件导出，准备进一步的生产制造。
将设计文件导出为标准的格式（如Gerber文件），可以将其发送给制造商进行生产。
总结：CADENCE仿真步骤包括电路设计、创建电路网络、定义仿真设置、运行仿真、分析仿真结果、优化电路设计、验证仿真结果和导出设计文件。
利用Cadence Allegro进行PCB级的信号完整性仿真
收稿日期利用Cade nce Al l e gro进行PCB级的信号完整性仿真Si gnal I nt e gri t y Si m ul ati on wi th Al l e g ro f or PCB Board D e s i g n李新¬É¸ÉÎ张琳ºÈÁÎǬÉÎ西安电子科技大学西安 西安大唐电信有限公司西安¸ÉÄÉÁεÎÉÖÅÒÓÉÔÙ ¸ÉcÁÎ £ÈÉÎÁ ¸ÉcÁΤÁÔÁÎÇ´ÅÌÅÃÏÍ ¸ÉcÁÎ £ÈÉÎÁ摘要在高速°£¢设计过程中 仅仅依靠个人经验布线 往往存在巨大的局限性"利用£ÁÄÅÎÃÅ的¡ÌÌÅÇÒÏ软件包对电路进行°£¢级的仿真 可以最优化线路布局 极大地提高电路设计质量 从而缩短设计周期"本文结合作者的实际设计经验 介绍使用£ÁÄÅÎÃÅ的一般步骤并列举在使用过程中所发现的一些问题"关键词高速°£¢布线¡ÌÌÅÇÒÏ文件转换信号完整性仿真随着信息宽带化和高速化的发展 以前的低速°£¢已完全不能满足日益增长信息化发展的需要 而高速°£¢的出现将对硬件人员提出更高的要求 仅仅依靠自己的经验去布线 会顾此失彼 造成研发周期过长 浪费财力物力 生产出来的产品不稳定"一般认为高速°£¢是指其数字信号边沿上升时间小于倍信号传输时延 这种高速°£¢的信号线必须按照传输线理论去设计 否则将会严重影响信号的完整性"£ÁÄÅÎÃÅ公司针对°£¢¤ÅÓÉÇγÔÕÄÉÏ发布一个功能非常实用的高速电路设计及信号完整性分析的工具选件¡¬¬¥§²¯°£¢"利用这个仿真软件能够根据叠层的排序 °£¢的介电常数 介质的厚度 信号层所处的位置以及线宽等等来判断某一°£¢线条是否属于微带线!带状线!宽带耦合带状线 并且根据不同的计算公式自动计算出信号线的阻抗以及信号的反射!串绕!电磁干扰等等 从而可以对布线进行约束以保证°£¢的信号完整性"下面根据我们的具体实践 介绍其基本使用方法"由于我们在实际设计过程中 通常使用¯²£¡¤进行电路前期设计 得到的是电路的ÍÁØ文件"为了利用£ÁÄÅÎÃÅ进行电路仿真 首先需要将¯²£¡¤的ÍÁØ文件转换为¡¬¬¥§²¯的ÂÒÄ文件"完成这一转换的工具是£ÁÄÅÎÃÅ公司提供的一组附件 该附件包含 个文件 分别是¬ÁÙÏÕÔ1ÃÔÌ ¬ÁÙÏÕÔ1ÆÎÔ ÌÁÙÏÕÔ1ÉÎÉ和´ÏÁÌÌÅÒÏ1ÅØÅ"使用时 需要设置好路径和环境变量 然后运行´ÏÁÌÌÅÇÒÏ1ÅØÅ文件 在提示下输入所要转换的ÍÁØ文件名 就可以将ÍÁØ文件转换为ÂÒÄ文件"但是需要特别注意的是 转换后的ÂÒÄ文件与原来的ÍÁØ文件相比有一些隐蔽性的问题 列举如下首先 元件的焊盘名和封装名会出现问题 在¯²£¡¤中合法的命名规则在¡¬¬¥§²¯中则可能不合法"例如 在¯²£¡¤中可这样定义一个封装名/³¢§¡ø 1 ø¬ ø· ø° 0 但是在转换至¡¬2¬¥§²¯的ÂÒÄ文件时会转变为/³¢2§¡ ¬ · ° 0 而在¯²£¡¤中定义的焊盘名/ ¤´© 1 ¸ 1 0在转换至¡¬¬¥§²¯的ÂÒÄ文件时会转变为/ ¤´© ¿ ¸ ¿ 0"即 它将封装名的/ø0删掉 而将焊盘名的/10改为/¿0"有的焊盘名如果与¡¬¬¥§²¯中的一些关键字重名 必须将其改名才能转换成功"第二 它会给°£¢自动加上默认叠层 然而¯²2£¡¤中没有叠层的选项"第三 它不能将原来的各种线宽!间距带到¡¬2¬¥§²¯中"第四 在将¯²£¡¤的ÍÁØ文件转换至¡¬¬¥2§²¯的ÂÒÄ文件后 有时会发现转换后的ÂÒÄ文件在¡¬¬¥§²¯中虽然能够正常打开 但是却不能正常存盘 它只能将°£¢的ÂÒÄ文件存为31³¡¶文件"解决的方法是在¤¯³环境下执行ÄÂÆÉØ命令纠正该错误"第五 转换至¡¬¬¥§²¯的ÂÒÄ文件的装焊层有些元件值没有带过来 因此不能在¡¬¬¥§²¯的ÂÒÄ文件中输出装焊图"第六 也是最重要的一点 在¡¬¬¥§²¯中自动加上叠层后 将原来的通孔焊盘按照默认叠层结构自动改变 如果要调整叠层结构 就必须对每一个通孔焊盘进行修改 否则会出现很严重的后果"因为在¡¬2¬¥§²¯中每一层都定义了各种焊盘 根据不同的层5现代电子技术6 年第 期总第 期仿真与测试进行选择 相比之下 ¯²£¡¤只在平面层上才定义热焊盘"在成功转到¡¬¬¥§²¯之后 还需要做些仿真前的准备"首先是根据器件的¤ÁÔÁÓÈÅÅÔ对器件的©¢©³进行检查 检查的内容包括¹察看©¢©³库是否有语法上的错误 这个可以在将©¢©³文件转换成ÄÍÌ文件报告时看出 或是在转换后的ÄÍÌ文件上 用¡¬¬¥§²¯的工具中的ÄÍÌÃÈÅÃË选项进行检查º管脚的输入!输出类型是否正确»¶©!¶´曲线是否有明显的非单调性!不连续性或其他明显的错误¼对所有的管脚模型是否都有ÁØ ÉÎ ´ÙÐÉ2ÃÁÌ值以及它们的关系是否正确 如果只有´ÙÐÉÃÁÌ值 那么仿真的时候只能用´ÙÐÉÃÁ̽所有的输出和双向管脚模型是否都有测试负载值 即£ÒÅÆ ²ÒÅÆ ¶ÒÅÆ和¶ÍÅÁÓ 如果是纯容性测试负载 可以没有²ÒÅƾ在标准测试负载情况下 ¶´的上升和下降的波形是否达到了¶ÍÅÁÓ的值¿©¢©³库的管脚是否与器件的¤ÁÔÁÓÈÅÅÔ管脚相一致"做完这些检查之后 就要对相应的器件指定各自的©¢©³库"而对离散器件 则要手工加上³°©£¥库"接着 需要指定¤£网线的电压值 这是为以后抽取模型时 不至于把¤£网线当成是信号网线"再下一步进行叠层编辑时 还需要同制板厂商联系 让他们给出满足需要的°£¢各层的介电常数!介质厚度!铜皮厚度以及叠层的顺序 上述参数要填在叠层表中"做完准备工作后 就可以抽取网线的拓扑结构进行信号完整性仿真了"仿真分为 种 一种是数据线仿真 一种是时钟线仿真 这都是在同步电路下进行的"仿真时 应该从器件的¤ÁÔÁÓÈÅÅÔ中查找以下的参数 ´ÃÏ1ÍÉÎ ´ÃÏ1ÍÁØ ´ÃÙÃÌÅ ´ÓÅÔÕÐ1ÍÉÎ ´ÈÏÌÄ1ÍÉÎ 从所提供的时钟的¤ÁÔÁÓÈÅÅÔ中查找´ÓËÅ×1ÃÌË ´ÊÉÔ 另外还需要估计°£¢的´ÓËÅ×1Ðà给出余量´ÍÁÒÇÉÎ"然后根据以下两个计算公式计算两个参数´ÓÅÔÔÌÅÄÅÌÁÙ1ÍÁØ和´Ó×ÉÔÃÈÄÅÌÁÙ1ÍÉÎ"这两个算式分别为´ÓÅÔÔÌÅÄÅÌÁÙ1ÍÁØ[´ÃÙÃÌÅ ´ÃÏ1ÍÁØ ´ÓÅÔÕÐ1ÍÉδÓËÅ×1ÃÌË ´ÓËÅ×1Ðà´ÊÉÔ ´ÁÄÊ ´Ó×ÉÔÃÈÄÅÌÁÙ1ÍÉÎ\´ÈÏÌÄ ´ÃÏ1ÍÉÎ ´ÓËÅ×1ÐôÓËÅ×1ÃÌË经过仔细分析 发现该公式确实已考虑得非常周全 把上升和下降沿的细微时间以及沿的细小抖动也包含在内 这可能也是£ÁÄÅÎÃÅ的°£¢软件中最核心最精华的部分"通过公式算出´ÓÅÔÔÌÅÄÅÌÁÙ1ÍÁØ ´Ó×ÉÔÃÈÄÅÌÁÙ1ÍÉÎ后 需要和根据拓扑结构仿真出来的´ÓÅÔÔÌÅÄÅÌÁÙ1ÍÁØ ´Ó×ÉÔÃÈÄÅÌÁÙ1ÍÉÎ值进行比较 以便用来调整参数"这些参数包括 布线长度 线阻抗 线速 增加减电阻!电容 节点的位置以及线的连接方式等"时钟线还需考虑它的单调性"参数调节是不能随心所欲的 不仅要找一定的规律 还要考虑到°£¢叠层的参数设置及一些现实所允许的值"这样才能找到适合实际°£¢的!比较理想的拓扑结构 否则如果在自动布线完成后才发现拓扑结构有问题 就需要来回进行修改"还要注意一点 就是所有以上参数都必须在最坏情况下找出它们的最大范围"所谓最坏情况是指 在仿真´ÓÅÔÔÌÅÄÅÌÁÙ1ÍÁØ数据时 必须是在ÓÌÏ×的环境下 而仿真´Ó×ÉÔÃÈÄÅÌÁÙ1ÍÉÎ数据时 必须在ÆÁÓÔ的环境下进行"在我们仿真的过程中 还发现有些器件的´ÃÏ1ÍÉÎ和´ÃÏ1ÍÁØ是在不同的测试条件下测试的 在仿真时还要改变ÄÍÌ库的测试环境值 才能测出更准确的值"调整好拓扑结构后 千万别忘了填写拓扑结构的限制表 限制表里头才是最终起作用的限制条件"接下来只要将填好限制后的拓扑结构加在同类网线上 然后转到³°¥£´²¡中进行自动布线"³°¥£´²¡会尽量根据限制自动布线 但是 最后在¡¬¬¥§²¯中做检查时 会发现有一些¤²£报告是因为没有按照限制完成布线 它会提示限制是多长 而实际只布了多长"这时 一种解决方法是删除所有线 改变器件位置 重新自动布线 再一种就需要改变拓扑结构 如果两种方法都失败了 就要考虑到换性能更好的器件"按照以上方法 一块高质量信号完整性的高速°£¢就已基本完成"通过使用£ÁÄÅÎÃÅ软件进行信号完整性的仿真 我们体会到该软件具有很强的实用性 对于硬件设计人员来说 是一种不可多得的设计工具 对高速°£¢来说尤为如此"当然 对于这样一个高智能仿真软件 使用起来也并不那么容易 如果对它的内部计算不甚了解 很有可能会因为一两个参数或选项的错误而导致仿真结果失败"希望本文能够起到一定的帮助作用"参考文献£ÁÄÅÎÃÅ£ÏÒÐ ¡ÌÌÅÇÒÏ°£¢¬ÁÙÏÕÔ³ÙÓÔÅÍ´ÒÁÉÎÉÎÇÁÕÎÁÌ£ÁÄÅÎÃÅ£ÏÒÐ ¡ÌÌÅÇÒÏÏÎÌÉÎÅÒÅÆÅÒÅÎÃÅÍÁÎÕÁÌÓ ²ÏÙ¬ÅÖÅÎÔÈÁÌ ³ÉÇÎÁÌ©ÎÔÅÇÒÉÔÙ¢ÏÁÒĤÅÓÉÇÎ ³ÉÍÕÌÁÔÉÏδÅÃÈÎÉÑÕÅÓ利用£ÁÄÅÎÃÅ¡ÌÌÅÇÒÏ进行°£¢级的信号完整性仿真收稿日期COR D I C算法在D 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CADENCE仿真步骤
Cadence SPECCTRAQuest 仿真步骤[摘要]本文介绍了Cadence SPECCTRAQuest在高速数字电路的PCB设计中采用的基于信号完整性分析的设计方法的全过程。
从信号完整性仿真前的环境参数的设置，到对所有的高速数字信号赋予PCB板级的信号传输模型，再到通过对信号完整性的计算分析找到设计的解空间，这就是高速数字电路PCB板级设计的基础。
[关键词]板级电路仿真I/O Buffer Information Specification（IBIS）1 引言电路板级仿真对于今天大多数的PCB板级设计而言已不再是一种选择而是必然之路。
在相当长的一段时间，由于PCB仿真软件使用复杂、缺乏必需的仿真模型、PCB仿真软件成本偏高等原因导致仿真在电路板级设计中没有得到普及。
随着集成电路的工作速度不断提高，电路的复杂性不断增加之后，多层板和高密度电路板的出现等等都对PCB板级设计提出了更新更高的要求。
尤其是半导体技术的飞速发展，数字器件复杂度越来越高，门电路的规模达到成千上万甚至上百万，现在一个芯片可以完成过去整个电路板的功能，从而使相同的PCB上可以容纳更多的功能。
PCB已不仅仅是支撑电子元器件的平台，而变成了一个高性能的系统结构。
这样，信号完整性在PCB板级设计中成为了一个必须考虑的一个问题。
传统的PCB板的设计依次经过电路设计、版图设计、PCB制作等工序，而PCB的性能只有通过一系列仪器测试电路板原型来评定。
如果不能满足性能的要求，上述的过程就需要经过多次的重复，尤其是有些问题往往很难将其量化，反复多次就不可避免。
这些在当前激烈的市场竞争面前，无论是设计时间、设计的成本还是设计的复杂程度上都无法满足要求。
在现在的PCB板级设计中采用电路板级仿真已经成为必然。
基于信号完整性的PCB仿真设计就是根据完整的仿真模型通过对信号完整性的计算分析得出设计的解空间，然后在此基础上完成PCB设计，最后对设计进行验证是否满足预计的信号完整性要求。
基于Cadence的电源完整性仿真步骤
基于Cadence的电源完整性仿真步骤1、设置电路板的参数用PI模式打开要仿真的电路板，仿真其CPU_1.8V电源平面的完整性。
1.1调用设置向导在PI中选择“Analyze”—>“Power Integrity”出现提示对话框，点击“确定”后出现设置向导窗口。
1.2板框（Board Outline）点击“Next”进入设置向导里的“Board Outline”窗口PI需要一个板框来进行布局和电源平面提取。
如果板框不完整或不存在，则上图右上角会有信息提示。
1.3Stack-up设置点击“Next”进入设置向导里的“Stack-up”窗口。
PI需要叠层关系来计算电源对从而为平面建模。
如果叠层不存在或者不包含平面层，则屏幕右上角会有信息显示。
在这里可以调整叠层关系（Edit stack-up）或从另一个设计中导入（Import stack-up）。
屏幕右上角有相应的示意图，如图：当不勾选“Physical view”时，各层厚度平均显示；勾选后各层按比例显示。
1.4DC Net-Plane Association点击“Next”进入设置向导里的“DC Net-Plane Association”窗口，如图：PI 在估算去耦电容之前需要给每一个需要仿真的电源平面分配DC电压，在这里可以调整现有的电压分配。
同一层的分割平面会有不同的“shape”，因此每个“shape”都有一个不同的DC网络。
1.5DC Power Pair Setup点击“Next”进入设置向导里的“DC Power Pair Setup”窗口，如图：在进行PI 之前，电源和地平面必须成对。
一个地可以被多个平面共享，但一次只能分析一对平面。
在“Plane 1”栏中选择要分析的平面，在“Plane 2”栏中选择对应的平面，选中的平面对将在右边的叠层视图中高亮。
点击“Add”创建对应的平面对。
1.6选择去耦电容点击“Next”，如图：1.7选择电容模型点击“Next”，如图：选好所用的电容模型后，点击“Finish”完成对电路板参数的设置，弹出“Power Integrity Design&Analyze”窗口，如图：2、单节点仿真可以通过运行单节点仿真来验证选择的电容数量能否在频率范围内维持目标阻抗。
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目录1.仿真前的准备工作 (2)1.1找到需要仿真的芯片的IBIS模型 (2)1.2模型转换（IBIS→DML） (2)1.3添加模型到Cadence的模型库中 (5)2. 对电路板进行设置（Setup Advisor） (7)2.1准备好要仿真的电路板 (7)2.2调用参数设置向导 (7)2.3叠层设置 (8)2.4设置DC电压值 (9)2.5器件设置（Device Setup） (10)2.6 SI模型分配 (12)2.7 SI检查（SI Audit） (16)2.8完成参数设置 (18)3.进行信号完整性仿真（反射） (19)3.1开始仿真 (19)3.2选择所要仿真的网络 (19)3.3提取网络的拓扑结构 (20)3.4给驱动端U8添加激励信号 (21)3.5设置激励信号的参数 (22)3.6执行反射仿真 (22)3.7仿真结果 (22)1.仿真前的准备工作1.1找到需要仿真的芯片的IBIS模型一般可以从芯片制造商网站上找到，如果没有，可能要通过其它途径获得如从SPICE模型中提取。
1.2模型转换 （IBIS→DML）将IBIS模型转换为DML模型，运用Cadence的Model Integrity工具将IBIS模型转化为Cadence能识别的DML模型，并验证仿真模型。
（1）单击“开始”按钮→“所有程序”→“Allegro SPB 15.5”→“Model Integrity”，如图1-1所示：图1-1 Model Integrity工具窗口（2）选择“File”→“Open”，打开一个IBIS模型如图1-2所示：图1-2 打开一个IBIS模型（3）在“Physical View”栏中，单击IBIS文件“sn74avca16245”→选择菜单栏里的“Options”→“Translation Options Editor”→弹出“Translation Options”窗口，如图1-3所示：图1-3 Translation Options窗口（4）默认选择“Make model names unique”，这个设置为每个IOCell模型名附加IBIS文件名。
单击“OK”，关闭“Translation Options”窗口。
（5）在“Physical View”栏中，单击IBIS文件“sn74avca16245”→单击鼠标右键→选择“IBIS to DML”（如图1-4所示）,系统会提示是否重写→选择“是”（如图1-5所示），重写文档。
这时在原先IBIS文件的目录下面会生成相应的DML模型（如图1-6所示）。
图1-4 IBIS→DML转换窗口图1-5 模型转换提示框图1-6 转换好的DML模型1.3添加模型到Cadence的模型库中将转换好的DML模型加载到Cadence的模型库中，在Allegro PCB SI 610中，选择“Analyze”→“SI/EMI Sim”→“Library”，如图1-7所示。
窗口分上下两个部分，上半部分是器件模型库；下半部分是互连模型库，包括传输线模型和Via模型。
当提取网络的拓扑结构时，互连模型会自动创建。
这里主要是加载器件的模型。
图1-7将DML模型加载到Cadence的模型库中在这里要完成两项工作：（1） 把所用到的模型加到模型库中。
选择“Add existing library”→“Local Library”,如图1-8所示：图1-8 添加模型（单个）选择相应的模型后，选择“打开”，这种方法只能一个一个的添加。
如果要添加的模型比较多可以选择“Add existing library”→“Local Library Path”，如图1-9所示：图1-9添加模型（批量）选择模型所在的文件夹，选择“OK”，这样整个文件夹中的模型都会添加到模型库中。
（2） 创建自己的库文件，以后本次仿真新创建的信号模型如电阻、电容的模型会自动保存到该库文件中。
选择“Create new library”，如图1-10所示：图1-10 Create new library窗口输入文件名，选择保存路径后，选择“保存”。
新建的库也会被添加到模型库中。
2.对电路板进行设置（Setup Advisor）下面以UL2项目的PCB板为例介绍，对其中的地址信号A15进行信号完整性仿真。
2.1准备好要仿真的电路板用Allegro PCB SI 610打开UL2的PCB板—BE7366MS01-11-9.brd。
如图2-1所示：图2-1 UL2的PCB板图2.2调用参数设置向导选择“Tools”→“Setup Advisor”，弹出“Database Setup Advisor”窗口，如图2-2所示：图2-2 Database Setup Advisor窗口2.3叠层设置进行叠层设置，确定电路板层面，包括每层的材料、类型、名称、厚度、线宽和阻抗信息，并确定PCB的物理和电气特性。
（1） 在图2-2中，单击“Next”弹出“Database Setup Advisor-Cross_section”窗口，如图2-3所示：图2-3 Database Setup Advisor-Cross_section窗口（2） 单击“Edit Cross-section”弹出“Layout Cross Section”窗口，如图2-4所示：图2-4 Layout Cross Section窗口在系统中，整个电路板的厚度是一个固定值，所以不要改变它。
在这里可以设置每一层的厚度，层面的类型，绝缘层的介电常数，线宽等等，并能计算出相应的特性阻抗值。
¾Mode 当“Differential Mode”被选择时，线宽、阻抗、差分阻抗、差分间距、差分耦合的模式都是相关联的。
根据改变的值，编辑器都会弹出菜单，允许进一步进行准确设置。
¾Material 从下拉菜单中选择材料。
¾Loss Tangent 根据绝缘层的功率因数补偿角的正切，指定当前选择的绝缘层的介电损失。
¾Type 层面的类型，包含SURFACE、CONDUCTOR、DIELECTRIC、PLANE等。
¾Thickness 分配给每个层的厚度。
¾Line Width 确定布线层的布线宽度。
¾Impedance 分配给每个层的阻抗。
参数设置完成后，单击“OK”，关闭“Layout Cross Section”窗口。
“Database Setup Advisor”窗口将再次显示。
2.4设置DC电压值（1）点击“Next”弹出“Data Setup Advisor -DC Nets”窗口，如图2-5所示：图2-5 Data Setup Advisor -DC Nets窗口（2）单击“Identify DC Nets”，弹出“Identify DC Nets”窗口，如图2-6所示：图2-6 Identify DC Nets窗口（3）在“Net”列表中选择网络如“GND_EARTH”，在“Voltage”栏双击“NONE”输入相应的电压值如0，并按下“Tab”键。
再如选择“VCC285”，在“Voltage”栏双击“NONE”输入相应的电压值如2.85，并按下“Tab”键。
（4）单击“OK”，关闭“Identify DC Nets”窗口。
“Database Setup Advisor”窗口将再次显示。
注意：如果有的网络与提取的网络无关，则可以不分配电压属性。
2.5器件设置（Device Setup）（1）单击“Next”，弹出“Data Setup Advisor –Device Setup”窗口，如图2-7所示：图2-7 Data Setup Advisor –Device Setup窗口（2）单击“Device Setup”，弹出“Device Setup”窗口，如图2-8所示：确定哪一个元件是连接器（Connectors），哪一个元件是分立元件（Discretes），并相应地确定器件的“Class”和“Pinuse”。
¾器件类（Device Class）IC是能分配IBIS模型的有源器件每个管脚的PINUSE必须是IN、OUT、BI、NC、GROUND、POWER、OCA、OCLDISCRETE是无源器件（电阻、电容、电导）每个管脚的PINUSE必须是UNSPECIO=INPUT/OUTPUT每个管脚的PINUSE必须是UNSPEC¾PINUSEPCB SI使用PINUSE来确定Sigxplorer/Signoise仿真的缓冲器类型Input、Output、Bidirectional、UNSPEC、Power、Ground对于IO和DISCRETE器件的PINUSE必须是UNSPEC都是无源器件图2-8 器件类设置窗口PCB SI使用Device Class来确定元件类型。
IC的类指定为有源器件，比如驱动器或接收器。
DISCRETE的类指定为无源器件，比如电阻、电容、电感。
IO的类指定为输入或者输出器件，比如连接器。
在UL2项目中，连接器都是以CN标识的，因此在Connector 栏中应输入CN*。
对于仿真，处理这些信息很重要。
当执行仿真时PCB SI使用PINUSE属性值。
例如，不小心把电阻PINUSE分配为OUT，PCB SI会假定电阻是一个驱动元件并为电阻分配一个默认的信号模型。
在电阻的Allegro器件文件创建过程中，Device Class分配不正确，就能导致上述错误。
（3）设置完成后，单击“OK”，保存修改返回“Database Setup Advisor-Device Setup”窗口，并弹出一个元件变化的状态报告，如图2-9所示：图2-9 元件变化的状态报告2.6 SI模型分配（1）单击“Next”，弹出“Data Setup Advisor –SI Models”窗口，如图2-10所示：图2-10 Data Setup Advisor –SI Models窗口（2）单击“Signal Model Assignment”→弹出提示信息（有的DC网络没有分配电压值），如图2-11所示：图2-11（3）单击“是”，弹出“Signal Model Assignment”窗口，如图2-12所示：¾Device 可以手动或自动为器件分配模型。
¾Bond Wires 定位并为Bondwire连接分配Trace模型。
¾RefDesPins 为指定管脚分配IOCell模型。
图2-12 Signal Model Assignment窗口（4）手动分配元件模型这里只对地址线A15进行仿真，该网络连接了五个器件分别是U8、U32、U38、U40、U45。