hdb3编译码器仿真设计程序
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity hdb3 is
port(codein: in std_logic;
clk : in std_logic;
clr : in std_logic;
hdb3 : out std_logic_vector(1 downto 0);
codeout1: out std_logic;
codeout2:out std_logic);
end hdb3;
architecture rtl of hdb3 is
signal codeout: std_logic_vector(1 downto 0);
signal count0 : integer:=0;
signal codeoutv: std_logic_vector(1 downto 0);
signal s0 : std_logic_vector(4 downto 0):="00000"; signal s1 : std_logic_vector(4 downto 0):="00000"; signal clkb : std_logic;
signal count1 : integer range 1 downto 0;
signal codeoutb: std_logic_vector(1 downto 0);
signal flagv : integer range 1 downto 0;
signal firstv : integer range 0 to 1;
signal flag1b : integer range 1 downto 0;
component dff --调用元件dff
port (d : in std_logic;
clk : in std_logic;
q : out std_logic);
end component;
begin
add_v:process(clk,clr) --插入V符号进程 begin
if(rising_edge(clk)) then
if(clr='1') then
codeoutv<="00"; --用00代表0
count0<=0;
else
case codein is
when '1'=>
codeoutv<="01"; --用01代表1
count0<=0;
if(count0=3)then --当有4个连续0时插入V
codeoutv<="11"; --用11代表V
count0<=0;
else
count0<=count0+1;
codeoutv<="00";
end if;
when others=>
codeoutv<="00";
count0<=count0;
end case;
end if;
end if;
end process add_v;
s0(0)<=codeoutv(0);
s1(0)<=codeoutv(1);
ds11: dff port map(s1(0),clk,s1(1)); --调用库中的D触发器来实现延迟作用
ds01: dff port map(s0(0),clk,s0(1));
ds12: dff port map(s1(1),clk,s1(2));
ds02: dff port map(s0(1),clk,s0(2));
ds13: dff port map(s1(2),clk,s1(3));
ds03: dff port map(s0(2),clk,s0(3));
bclk: clkb<=not clk;
add_b:process(clkb) --插入符号B进程
begin
if(rising_edge(clkb)) then
if(codeoutv="11") then
if(firstv=0) then
count1<=0;
firstv<=1;
s1(4)<=s1(3);
s0(4)<=s0(3);
else
if(count1=0) then --用10代表B
s1(4)<='1';
s0(4)<='0';
count1<=0;
else
s1(4)<=s1(3);
s0(4)<=s0(3);
end if;
end if;
elsif(codeoutv="01") then
count1<=count1+1;
s1(4)<=s1(3);
s0(4)<=s0(3);
else
s1(4)<=s1(3);
s0(4)<=s0(3);
count1<=count1;
end if;
end if;
end process add_b;
codeoutb<=s1(4)&s0(4);
output:process(clk) --单极性变双极性进程 begin
if(rising_edge(clk)) then
if((codeoutb="01")or(codeoutb="10"))then --1 or B if(flag1b=1) then
codeout<="11";
flag1b<=0;
else
codeout<="01";
flag1b<=1;
end if;
elsif(codeoutb="11") then ---V
if(flag1b=1) then
codeout<="01";
else
codeout<="11";
end if;
else
codeout<="00";
flag1b<=flag1b;
end if;
end if;
hdb3<=codeout;
end process output;
end rtl;
8.2 附录二 HDB3码译码器程序