hdb3编译码器仿真设计程序

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity hdb3 isport(codein: in std_logic;clk : in std_logic;clr : in std_logic;hdb3 : out std_logic_vector(1 downto 0);codeout1: out std_logic;codeout2:out std_logic);end hdb3;architecture rtl of hdb3 issignal codeout: std_logic_vector(1 downto 0);signal count0 : integer:=0;signal codeoutv: std_logic_vector(1 downto 0);signal s0 : std_logic_vector(4 downto 0):="00000"; signal s1 : std_logic_vector(4 downto 0):="00000"; signal clkb : std_logic;signal count1 : integer range 1 downto 0;signal codeoutb: std_logic_vector(1 downto 0);signal flagv : integer range 1 downto 0;signal firstv : integer range 0 to 1;signal flag1b : integer range 1 downto 0;component dff --调用元件dffport (d : in std_logic;clk : in std_logic;q : out std_logic);end component;beginadd_v:process(clk,clr) --插入V符号进程 beginif(rising_edge(clk)) thenif(clr='1') thencodeoutv<="00"; --用00代表0count0<=0;elsecase codein iswhen '1'=>codeoutv<="01"; --用01代表1count0<=0;if(count0=3)then --当有4个连续0时插入Vcodeoutv<="11"; --用11代表Vcount0<=0;elsecount0<=count0+1;codeoutv<="00";end if;when others=>codeoutv<="00";count0<=count0;end case;end if;end if;end process add_v;s0(0)<=codeoutv(0);s1(0)<=codeoutv(1);ds11: dff port map(s1(0),clk,s1(1)); --调用库中的D触发器来实现延迟作用ds01: dff port map(s0(0),clk,s0(1));ds12: dff port map(s1(1),clk,s1(2));ds02: dff port map(s0(1),clk,s0(2));ds13: dff port map(s1(2),clk,s1(3));ds03: dff port map(s0(2),clk,s0(3));bclk: clkb<=not clk;add_b:process(clkb) --插入符号B进程beginif(rising_edge(clkb)) thenif(codeoutv="11") thenif(firstv=0) thencount1<=0;firstv<=1;s1(4)<=s1(3);s0(4)<=s0(3);elseif(count1=0) then --用10代表Bs1(4)<='1';s0(4)<='0';count1<=0;elses1(4)<=s1(3);s0(4)<=s0(3);end if;end if;elsif(codeoutv="01") thencount1<=count1+1;s1(4)<=s1(3);s0(4)<=s0(3);elses1(4)<=s1(3);s0(4)<=s0(3);count1<=count1;end if;end if;end process add_b;codeoutb<=s1(4)&s0(4);output:process(clk) --单极性变双极性进程 beginif(rising_edge(clk)) thenif((codeoutb="01")or(codeoutb="10"))then --1 or B if(flag1b=1) thencodeout<="11";flag1b<=0;elsecodeout<="01";flag1b<=1;end if;elsif(codeoutb="11") then ---Vif(flag1b=1) thencodeout<="01";elsecodeout<="11";end if;elsecodeout<="00";flag1b<=flag1b;end if;end if;hdb3<=codeout;end process output;end rtl;8.2 附录二 HDB3码译码器程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hdb3 isport(out0:in std_logic;out1:in std_logic;clock:in std_logic;data_out:out std_logic);end hdb3 ;architecture rtl of hdb3 issignal reg0:std_logic_vector(4 downto 0);signal reg1:std_logic_vector(4 downto 0);beginprocess(clock)beginif rising_edge(clock)thenif out1='1' and out0='0' and reg0(4 downto 1)="0001" and reg1(4 downto 1)="0000" thenreg0<="00001";reg1<="00000";elsif out1='1' and out0='1' and reg0(4 downto 1)="0001" and reg1(4 downto 1)="0001" thenreg0<="00001";reg1<="00000";elsif out1='1' and out0='1' and reg0(4 downto 2)="001" and reg1(4 downto 2)="001" thenreg0<="0000"&reg0(1);reg1<="0000"&reg1(1);elsif out1='1' and out0='0' and reg0(4 downto 2)="001" and reg1(4 downto 2)="000" thenreg0<="0000"&reg0(1);reg1<="0000"&reg1(1);elsereg0<=out1&reg0(4 downto 1);reg1<=out0&reg1(4 downto 1);end if;end if;end process;process(clock)beginif rising_edge(clock) thenif reg0(0)='1' or reg1(0)='1' then data_out<='1';elsedata_out<='0';end if;end if;end process;end rtl;。