并行乘法器-南京理工大学紫金学院vhdl实验报告-eda

EDA技术与应用实验报告实验名称：并行乘法器姓名：学号：班级：通信时间：2013南京理工大学紫金学院电光系一、实验目的1、学习包集和元件例化语句的使用。

2、学习FLU（全加器单元）电路的设计。

3、学习并行乘法电路的设计。

二、实验原理并行乘法器的电路原理图如下图所示，主要由全加器和与门构成。

并行乘法器原理图三、实验内容1、and_2library ieee;use ieee.std_logic_1164.all;entity and_2 isport (a,b:in std_logic;y:out std_logic);end and_2;architecture and_2 of and_2 isbeginy <= a and b;end and_2;2、faulibrary ieee;use ieee.std_logic_1164.all;entity fau isport (a,b,cin:in std_logic;s,cout:out std_logic);end fau;architecture fau of fau isbegins <= a xor b xor cin;cout <= (a and b)or(a and cin)or(b and cin);end fau;3、top_rowlibrary ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity top_row isport (a:in std_logic;b:in std_logic_vector(3 downto 0);sout,cout:out std_logic_vector(2 downto 0);p:out std_logic);end top_row;architecture structural of top_row isbeginU1: component and_2 port map(a,b(3),sout(2));U2: component and_2 port map(a,b(2),sout(1));U3: component and_2 port map(a,b(1),sout(0));U4: component and_2 port map(a,b(0),p);cout(2) <= '0';cout(1) <= '0';cout(0) <= '0';end structural;4、mid_rowlibrary ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity mid_row isport (a:in std_logic;b:in std_logic_vector(3 downto 0);sin,cin:in std_logic_vector(2 downto 0);sout,cout:out std_logic_vector(2 downto 0);p:out std_logic);end mid_row;architecture structural of mid_row issignal and_out:std_logic_vector(2 downto 0);beginU1: component and_2 port map(a,b(3),sout(2));U2: component and_2 port map(a,b(2),and_out(2));U3: component and_2 port map(a,b(1),and_out(1));U4: component and_2 port map(a,b(0),and_out(0));U5: component fau port map(sin(2),cin(2),and_out(2), sout(1), cout(2));U6: component fau port map(sin(1),cin(1),and_out(1), sout(0), cout(1));U7: component fau port map(sin(0),cin(0),and_out(0), p, cout(0));end structural;5、lower_rowlibrary ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity lower_row isport (sin,cin:in std_logic_vector(2 downto 0);p:out std_logic_vector(3 downto 0));end lower_row;architecture structural of lower_row issignal local:std_logic_vector(2 downto 0);beginlocal(0) <= '0';U1: component fau port map(sin(0),cin(0),local(0), p(0),local(1));U2: component fau port map(sin(1),cin(1),local(1), p(1),local(2));U3: component fau port map(sin(2),cin(2),local(2), p(2),p(3));end structural;6、my_componentslibrary ieee;use ieee.std_logic_1164.all;package my_components iscomponent and_2 isport (a,b:in std_logic; y:out std_logic);end component;component fau isport (a,b,cin:in std_logic; s,cout:out std_logic); end component;component top_row isport (a:in std_logic;b:in std_logic_vector(3 downto 0);sout,cout:out std_logic_vector(2 downto 0);p:out std_logic);end component;component mid_row isport (a:in std_logic;b:in std_logic_vector(3 downto 0);sin,cin:in std_logic_vector(2 downto 0);sout,cout:out std_logic_vector(2 downto 0);p:out std_logic);end component;component lower_row isport (sin,cin:in std_logic_vector(2 downto 0);p:out std_logic_vector(3 downto 0));end component;end my_components;7、multiplierlibrary ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity multiplier isport (a,b:in std_logic_vector(3 downto 0);prod:out std_logic_vector(7 downto 0));end multiplier;architecture structural of multiplier istype matrix is array (0 to 3)ofstd_logic_vector (2 downto 0);signal s,c:matrix;beginU1: component top_row port map (a(0),b,s(0),c(0),prod(0));U2: component mid_row port map (a(1),b,s(0),c(0),s(1), c(1),prod(1));U3: component mid_row port map (a(2),b,s(1),c(1),s(2), c(2),prod(2));U4: component mid_row port map (a(3),b,s(2),c(2),s(3), c(3),prod(3));U5: component lower_row port map(s(3),c(3),prod(7 downto 4));end structural;8、仿真9、把multiplier代码改为百位、十位、个位输出代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.my_components.all;entity multiplier isport (a,b:in std_logic_vector(3 downto 0);hun,ten,one:out std_logic_vector(3 downto 0)); end multiplier;architecture structural of multiplier istype matrix is array (0 to 3)ofstd_logic_vector (2 downto 0);signal s,c:matrix;signal p:std_logic_vector(7 downto 0);beginU1: component top_row port map (a(0),b,s(0),c(0),p(0));U2: component mid_row port map (a(1),b,s(0),c(0),s(1), c(1),p(1));U3: component mid_row port map (a(2),b,s(1),c(1),s(2), c(2),p(2));U4: component mid_row port map (a(3),b,s(2),c(2),s(3), c(3),p(3));U5: component lower_row port map(s(3),c(3),p(7 downto 4));process(p)variable temp:std_logic_vector(7 downto 0);beginif p >"1100_0111" thenhun <="0010";temp:=p-"1100_1000";elsif p>"0110_0011" thenhun <="0001";temp:=p-"0110_0100";elsehun <="0000";temp:=p;end if;if temp>"0101_1001" thenten <="1001";temp:=temp-"0101_1010"; elsif temp>"0100_1111" then ten <="1000";temp:=temp-"1010_0000"; elsif temp>"0100_0101" then ten <="0111";temp:=temp-"0100_0110"; elsif temp>"0011_1011" then ten <="0110";temp:=temp-"0011_1100"; elsif temp>"0011_0001" then ten <="0101";temp:=temp-"0011_0010"; elsif temp>"0010_0111" then ten <="0100";temp:=temp-"0010_1000"; elsif temp>"0001_1101" then ten <="0011";temp:=temp-"0001_1110"; elsif temp>"0001_0011" then ten <="0010";temp:=temp-"0001_0100"; elsif temp>"0000_1001" then ten <="0001";temp:=temp-"0000_1010"; elseten <="0000";temp:=temp;end if;one <=temp(3 downto 0);end process;end structural;四、小结与体会通过本次实验，我对包集和元件例化语句的使用有了更深刻的了解。