高速串行接口技术详解

Deframer
Integrated System Design Lab.
Clock recovery
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Link Component
▪ Phase-locked Loop (PLL)
CKi ( fin )
Phase error Loop- Vctr Voltage-Controlled
Detector
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Computing System
▪ High-speed I/O is needed everywhere
Display Long distance Switch
Graphic Disk LAN
CPU
North Bridge
South Bridge
Memory Local I/O
SAN
Integrated System Design Lab.
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Digital System Performance
▪ Performance bottleneck
– The cost of arithmetic operation is cheap now
Computation - bound
Communication - bound
“Pentium Pro”
Core
▪ Single trace ▪ Plesiochronous ▪ Clock embedded in data ▪ Clock & data recovery
Integrated System Design Lab.
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Parallel vs. Serial
Hardware Co mplexity
▪ High-speed, low voltage swing interface
Termination
VTT
( R = Z0 )
VRR
Driver
Channel Z0 Z0
DC block
To CDR
Limiting amp
▪ Usually, differential ▪ Small swing - ~ several hundreds mV
Integrated System Design Lab.
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Introduction
▪ Moore’s law
Growing gap limits system performance!!
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Integrated System Design Lab.
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Parallel Bus & Serial Link
Core
Parallel Bus Data
I/O
I/O
Clock
Core
▪ Group data (Bus) ▪ Source synchronous ▪ Matched trace
Core
Serial Link
Serial
Data
I/Oห้องสมุดไป่ตู้
I/O
Detector
Filter
Oscillator
Di 0 1 1 0 1 0 0 1 0 0 0
CKr
Do
Integrated System Design Lab.
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Link Performance Metric
▪ Eye diagram & jitter Tbit
Random bit sequence
Integrated System Design Lab.
11
Link Component
▪ Clock & data recovery (CDR) circuits
Decision circuit
Do
Di
NRZ Phase error Loop- Vctr Voltage-Controlled CKr
Eye diagram Jitter histogram
Integrated System Design Lab.
Tbit Ideal
Timing uncertainty : Jitter Realistic
10 ~ 20 cycles / Arithmetic operation 70 cycles / DRAM access
“Pentium 4”
20 ~ 30 cycles / Arithmetic operation 500 ~ 600 cycles / DRAM access
Integrated System Design Lab.
Integrated System Design Lab.
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Serial Link Architecture
Transmitter
PCS
Serializer
Transmitter + Receiver = Transceiver
Framer
Channel
PLL Receiver
Deserializer PCS
Filter
Oscillator
M
CKo ( fout )
▪ Frequency multiplication: fout = M·fin ▪ Jitter filter ▪ Zero-delay buffer
Integrated System Design Lab.
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Link Component
Latency
Parallel Bus Low Short
Speed
~ 200Mbps / pin
Manufacturing Cost
High
Serial Link High
Long ~ 10Gbps / pin
or more Low
World is moving toward “serial link” or “serial-link-like parallel b us” !!
Integrated System Design Lab.
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Introduction
▪ Moore’s law
– Performance & density improvement in digital system
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High-Speed Serial Link
Deog-Kyoon Jeong
Seoul National University
Outline
▪ Introduction ▪ High-speed I/O overview ▪ Hot design issues ▪ Design examples ▪ Summary