英文资料翻译-倪烨

南京工程学院毕业设计文献资料翻译（原文及译文）原文名称：IIS Multi Audio Interface and WM8960课题名称：基于Linux系统的音频编解码芯片驱动程序设计学生姓名：倪烨学号：208100621指导老师：朱瑾所在院系：通信工程学院专业名称：电子信息工程2014 年 2 月南京IIS MULTI AUDIO INTERFACE1.1 OVERVIEW OF IIS MULTI AUDIO INTERFACEInter-IC Sound (IIS) is one of the popular digital audio interface. The IIS bus handles audio data and the other signals, namely, sub-coding and control, are transferred separately. It is possible to transmit data between two IIS bus. To minimize the number of pins required and to keep wiring simple, basically, a 3-line serial bus is used. This consists of a line for two time-multiplexed data channels, a word select line and a clock line.IIS interface transmits or receives sound data from external stereo audio codec. To transmit and receive data, 32bitsx64 FIFOs (First-In-First-Out) for each channel are included and DMA transfer mode to transmit and receive samples can be supported. IIS-specific clock can be supplied from internal system clock controller through IIS clock divider or direct clock source.IIS V5.1 can handle up to 2 sound sources. For example, OS (Operating Sound)-controlled sound can be delivered to primary sound path and OS-independent sound can be delivered to secondary sound path. IIS V5.1 can mix primary sound source and secondary sound source.1.2 KEY FEATURES OF IIS MULTI AUDIO INTERFACE• Mixes up to two sound sources: Primary and Secondary sound source.• Primary sound source can drive up to 5.1ch IIS-bus for audio interface with external DMA-based operation• Secondary sound source can support stereo sound channels with internal DMA • Serial, 8/16/24-bit per channel data transfers• Supports IIS, MSB-justified and LSB-justified data format• IIS v5.1 interrupt can wake-up system from IDLE and DEEP_IDLE mode.• Master /slave mode support• Auxiliary clock out support for codec chip1.3 FUNCTIONAL DESCRIPTIONSIIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel control block as shown in Figure 2-1. Note that each FIFO has 32-bit width and 64-depth structure, which contains left/right channel data. Thus, FIFO access and data transfer are handled with left/right pair unit. Figure 2-1shows the functional block diagram of IIS interface.1.4 MASTER/SLAVE MODEMaster/Slave mode shows direction of I2SLRCLK and I2SSCLK. If IIS bus interface transmits I2SLRCLK and I2SSCLK to IIS codec, IIS bus is master mode. If IIS bus interface receives I2SLRCLK and I2SSCLK from IIS codec, IIS bus is slave mode. To select master or slave mode, set MSS bit of IISMOD register. TX/RX mode indicates the direction of data flow. If IIS bus interface transmits data to IIS codec, this indicates TX mode. Conversely, IIS bus interface receives data from IIS codec, this indicates RX mode.1.5 Sound MixingIIS can mix primary sound in TXFIFO0 and secondary sound in TXFIFO_S when two sound sources have the same sampling rate and PCM format.• If overflow occurs, then mixer saturates output v alue.• Mixer can handle Different Bit Length. (Controlled by BLC bit at IISMOD SFR) This function has two limitations:1. Normalization should be pre-processed in S/W configurations or settings.2. Synchronization between two sound sources is not guaranteed.WM8960 Sound Chip1.1 DESCRIPTIONThe WM8960 is a low power, high quality stereo codec designed for portable digital audio applications.Stereo class D speaker drivers provide 1W per channel into 8 loads with a 5V supply. Low leakage, excellent PSRR and pop/click suppression mechanisms also allow direct battery connection to the speaker supply. Flexible speaker boost settings allow speaker output power to be maximised while minimising other analogue supplyA highly flexible input configuration for up to three stereo sources is integrated, with a complete microphone interface. External component requirements are drastically reduced as no separate microphone, speaker or headphone amplifiers are required. Advanced on-chip digital signal processing performs automatic level control for the microphone or line input.Stereo 24-bit sigma-delta ADCs and DACs are used with low power over-sampling digital interpolation and decimation filters and a flexible digital audio interface.The master clock can be input directly or generated internally by an onboard PLL, supporting most commonly-used clocking schemes.The WM8960 operates at analogue supply voltages down to 2.7V, although the digital supplies can operate at voltages down to 1.71V to save power. The speaker supply can operate at up to 5.5V, providing 1W per channel into 8 loads. Unused functions can be disabled using software control to save power.The WM8960 is supplied in a very small and thin 5*5mm QFN package, ideal for use in hand-held and portable systems.1.2 ANALOGUE TO DIGITAL CONVERTER(ADC)The WM8960 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduce the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to A VDD. With a 3.3V supply voltage, the full scale level is 1.0V Any voltage greater than full scale may overload the ADC and cause distortion.1.3 AUTOMATIC LEVEL CONTROL(ALC)The WM8960 has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary. Note that when the ALC function is enabled, the settings of registers 0 and 1 (LINVOL, IPVU, LIZC, LINMUTE, RINVOL, RIZC and RINMUTE) are1.4 INPUT SIGNAL PATHThe WM8960 has three flexible stereo analogue input channels which can be configured as line inputs, differential microphone inputs or single-ended microphone inputs. Line inputs and microphone PGA outputs can be routed to the hi-fi ADCs or directly to the output mixers via a bypass path.1.5 OUTPUT SIGNAL PATHThe hi-fi DACs and DAC digital filters are enabled by register bits DACL and DACR. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8960, irrespective of whether the DACs are enabled or not.The WM8960 DACs receive digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions:1.Digital volume control with soft mute and soft un-mute2.Mono mix3.3D stereo enhancement4.De-emphasis5.Sigma-delta modulationHigh performance sigma-delta 24-bit audio DAC converts the digital data into an analogue signal.The analogue outputs from the DACs can then be mixed with the analogue line inputs and the ADC analogue inputs. This mix is fed to the output drivers for headphone or speaker output. OUT3 can provide a mono mix of left and right mixers or a pseudo-ground for capless headphone drive.1.6 APPLICATIONS1.Games consoles.2.Portable media/DVD players3.Mobile multimediaFrom： ：S5PV210_UM_REV1.1 and WM8960__NatertechIIS 多路音频接口1.1 IIS多路音频接口的综述IIS又称内部集成电路声音总线，是目前经常使用的数字音频接口之一。