序列检测器的设计实验报告.docx
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EDA实验报告书
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WHEN OTHERS => NST <= StO; END CASE ; END PROCESS;
REG: PROCESS (CLK,RST)
BEGIN
IF RST='1' THEN ST<=sO;
ELSIF ( CLK'EVENT AND CLK='1') THEN ST<=NST;
END IF;
END PROCESS REG; SOUT<='1'WHEN ST=s8 ELSE '0'; END behav;
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LlBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY SM1 IS
PoRT (
clock : IN STD_LOGIC; reset : IN STD_LOGIC := '0';
in put1 : IN STD_LOGIC := '0';
in put2 : IN STD_LOGIC := '0';
OUtPUtI : OUT STD_LOGIC
);
END SM1;
ARCHITECTURE BEHA VIOR OF SM1 IS
实验结果
TYPE type_fstate IS (st1,st2,st3,st4,st5,st6,st7,st8,stθ);
SIGNAL fstate : type_fstate;
SIGNAL reg_fstate : type_fstate;
BEGIN
PROCESS (CIoCk,reset,reg_fstate)
BEGIN
IF (reset='1') THEN
fstate <= st1;
ELSIF (clock='1' AND clock'event) THEN
fstate <= reg_fstate;
END IF;
END PROCESS;
PROCESS (fstate,i nput1,i nput2)
BEGIN
OUtPUtI <= '0';
CASE fstate IS
WHEN st1 =>
IF (((i nput1 = '1') AND (in put2 = '1'))) THEN reg_fstate <= st2;
ELSE
reg_fstate <= st0;
END IF;
OUtPUtI <= '0';
WHEN st2 =>
IF (((i nput1 = '1') AND (in put2 = '1'))) THEN reg_fstate <= st3;
ELSE reg_fstate <= st0;
END IF;
OUtPUtI <= '0';
WHEN st3 =>
IF (((i nput1 = '1') AND (in put2 = '1'))) THEN reg_fstate <= st4;
ELSE reg_fstate <= st0;
END IF;
OUtPUtI <= '0';
WHEN st4 =>
IF (((i nput1 = '1') AND (in put2 = '1'))) THEN reg_fstate <= st5;
ELSE reg_fstate <= st0;
END IF;
OUtPUtI <= '0';
WHEN st5 =>
IF (((i nput1 = '1') AND (in put2 = '1'))) THEN reg_fstate <= st6;
ELSE reg_fstate <= st0;
END IF;
OUtPUtI <= '0';
WHEN st6 =>
IF (((i nput1 = '1') AND (in put2 = '1'))) THEN reg_fstate <= st7;
ELSE reg_fstate <= st0;
END IF;
OUtPUtI <= '0';
WHEN st7 =>
IF (((i nput1 = '1') AND (in put2 = '1'))) THEN reg_fstate <= st8;
ELSE reg_fstate <= st0;
END IF;
OUtPUtI <= '0';
WHEN st8 =>