DDR 物理层信号品质测试技术和方案

N5451A InfiniiMax Long Wire ZIF Tip Wider span than standard ZIF Tip to probe signal like DDR system
Two different wire length: 7 mm (>6GHz) and 11 mm (>4.5GHz)
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2002
2000 Impact on Design and Validation Clock Speeds reaching 1GHz Parallel buses reaching the speeds of serial technology Tighter timing margins require calibration and bus training for DRAM, controller, and analyzer capture Crosstalk, impedance, EMI, and jitter issues Noise susceptibility Probe load effects are critical
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Probing Solutions
Probing is an important consideration for DDR measurement. Since the JEDEC is specified at the balls of the DRAM BGA package, getting a good measurement can be a challenge. Many designs have vias or designed-in probe points but they do not always produce good signal integrity. Probing at the wrong locations could cause a lot of reflection or non-monotonic edges. The load of your probing system is also another important consideration. It can affect the signals on your system as well as what you measure.
SDR Clock Synchronous
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2010+ 2008+
DDR Double Data Rate, Differential Clock, Data Strobe (DQS), Delayed Locked Loop
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DDR 400 MT/s
2005
SDR 100 MT/s
DDR2 On-Die Termination (ODT), Off-Chip Driver (OCD), Differential DQS
1.5GHz Active Probe
The left one is not a good waveform with a big ISI. This is due to a difference in load capacity, 10pF for the passive probe, and only 0.1pF for the active probe (Agilent Infiniimax). It does not mean that active probe is always good. If you use a wrong accessory, such a long lead, your waveform can be distorted as the left one.
Strobe (DQS) Read Write Data (DQ)
Read and Write DDR Data (DQ) signals have a different timing compared to the Data Strobe (DQS). DQS and DQ edges are aligned for Read signals.DQS edge is 90deg phase shifted from the DQ edge for Write signals. And since the DQS and DQ are on the same bus, if you simply trigger on the DQS edge, you will get nested eye patterns. You can easily understand that it will be tough to make your validation with such eyes.
DRAM
Clock (CLK) Strobe (DQS)
8 lines 6 lines 12 lines
Clock (CLK)
Compliance is measured at the balls of the DRAM where JEDEC standard is defined.
Strobe (DQS) Data (DQ) Control Address
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Serial vs. DDR Compliance
Connector
Tx
Rx
Rx Tx
Compliance to the standards is at the interface of the connector.
PCI-Express, SATA, FB-DIMM
Memory Controller
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N54பைடு நூலகம்6A ZIF Tip
N5450A/N5451A More InfiniiMax Probe Innovations
N5450A InfiniiMax Extreme Temperature Cable Extension
Solution with Gore Cable Extension specially developed for InfiniiMax Perfect solution for the environmental chamber testing Agilent exclusive solution with 36 inches long (92cm) reach Two Different Operating Temp depending of the probe head N5381A solder-in: -55 to +150°C E2677A solder-in: -25 to +80°C
Your DDR waveform can be distorted with a long probe accessory. It is desirable to use a probe with accessories specified at the end of the probe. All Agilent Probe Heads and Accessories are Specified.
DDR3 Point-to-Point Data, Fly-by Addr/Cmd, Self-calibrated driver impedance and ODT
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Benefits of good signal integrity
Guarantees interoperability with different vendors Improved device performance More design margin
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Scope Probing
These two screenshots are the same DDR2 400 waveform with the same oscilloscope. Only the probes used are different.
500MHz Passive Probe
There a lot of clock jitter spec in JEDEC. That means how important is clock jitter in DDR. This is a new technical challenge.
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DDR Difficulty 2 : Read and Write Timing
Read and Write separation is necessary to validate DDR signals with an oscilloscope.
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DDR Physical Layer Validation
There is an addendum from Intel and Jedec, in which Electrical, Timing and Clock Jitter specifications are mentioned.
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DDR Technology Trend and Validation Challenge
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About DDR DRAM memory
Key New Technologies
Memory Speed Roadmap
DDR2 800 MT/s
DDR4 3.2 GT/s DDR3 1.6 GT/s
DDR Physical Layer Test Solution
孙灯亮
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Table of Content
DDR Technology Trend and Validation Challenge Probing Solutions New Innovative Methods to Separate Read and Write Signals Automated DDR1/2/3 Measurements Debug Idea Summary